Browse Patents by Publication Date

Publication Number Title
US10163690 2-D interconnections for integrated circuits
US10163691 Low-K dielectric interconnect systems
US10163692 Structure and formation method of interconnection structure of semiconductor device structure
US10163693 Methods for processing semiconductor dice and fabricating assemblies incorporating same
US10163695 Self-forming barrier process
US10163696 Selective cobalt removal for bottom up gapfill
US10163697 Method for forming BEOL metal levels with multiple dielectric layers for improved dielectric to metal adhesion
US10163698 Interconnect structure and manufacturing method thereof
US10163699 Cu wiring forming method and semiconductor device manufacturing method
US10163700 Method for forming conductive structure using polishing process
US10163701 Multi-stack package-on-package structures
US10163703 Method for forming self-aligned contact
US10163704 Semiconductor device and a method for fabricating the same
US10163705 Profile of through via protrusion in 3DIC interconnect
US10163706 Alignment marks in substrate having through-substrate via (TSV)
US10163707 Method for forming group III-V device structure
US10163708 Integrated antenna on interposer substrate
US10163709 Semiconductor device and method
US10163710 Method of manufacturing semiconductor device by applying molding layer in substrate groove
US10163711 Methods of packaging semiconductor devices including placing semiconductor devices into die caves
US10163713 Wafer dicing using femtosecond-based laser and plasma etch
US10163714 Semi-sequential 3D integration
US10163715 FinFET device and method of forming same
US10163716 Symmetric tunnel field effect transistor
US10163717 Method of forming FinFET device by adjusting etch selectivity of dielectric layer
US10163718 Semiconductor device and a method for fabricating the same
US10163719 Method of forming self-alignment contact
US10163720 Method of forming source/drain contact
US10163721 Hybridization fin reveal for uniform fin reveal depth across different fin pitches
US10163722 Method and structure for FinFet isolation
US10163723 Self-aligned nanowire formation using double patterning
US10163724 Integrated circuit device and method of manufacturing same
US10163725 High mobility transistors
US10163726 FinFET devices and methods of forming
US10163727 MOS devices with thinned gate spacers and methods of thinning the gate spacers
US10163728 Semiconductor device having a stacked fin structure and manufacturing method thereof
US10163729 Silicon and silicon germanium nanowire formation
US10163730 Semiconductor device structure with gate spacer having protruding bottom portion and method for forming the same
US10163731 FinFET semiconductor structure having hybrid substrate and method of fabricating the same
US10163732 Moving pyrometer for use with a substrate chamber
US10163733 Method of extracting defects
US10163734 Method for manufacturing semiconductor structure
US10163735 Pressure-activated electrical interconnection by micro-transfer printing
US10163736 Electroluminescent light source with an adjusted or adjustable luminance parameter and method for adjusting a luminance parameter of the electroluminescent light source
US10163737 Semiconductor device and method of forming build-up interconnect structures over carrier for testing at interim stages
US10163738 Structure and method for overlay marks
US10163739 Solid-state imaging device and method for producing the same
US10163740 Semiconductor device
US10163741 Scribe lane structure in which pad including via hole is arranged on sawing line
US10163742 Customized module lid
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130