Browse Patents by Publication Date

Publication Number Title
US10163794 Capping layer for improved deposition selectivity
US10163795 Electro-migration barrier for Cu interconnect
US10163796 Surface treatment for semiconductor structure
US10163797 Forming interlayer dielectric material by spin-on metal oxide deposition
US10163798 Embedded multi-die interconnect bridge packages with lithotgraphically formed bumps and methods of assembling same
US10163799 Semiconductor structure and method of manufacturing the same
US10163800 Package structure with dummy feature in passivation layer
US10163801 Structure and formation method of chip package with fan-out structure
US10163802 Fan-out package having a main die and a dummy die, and method of forming
US10163803 Integrated fan-out packages and methods of forming the same
US10163804 Molding structure for wafer level package
US10163805 Package structure and method for forming the same
US10163806 Photolithography alignment mark structures and semiconductor structures
US10163807 Alignment pattern for package singulation
US10163808 Module with embedded side shield structures and method of fabricating the same
US10163809 Shielding for through-silicon-via noise coupling
US10163810 Electromagnetic interference shielding for system-in-package technology
US10163811 Semiconductor package structure based on cascade circuits
US10163812 Device having substrate with conductive pillars
US10163813 Chip package structure including redistribution structure and conductive shielding film
US10163814 Semiconductor package having a metal paint layer
US10163815 Semiconductor device with dummy metal protective structure around semiconductor die for localized planarization of insulating layer
US10163816 Structure and formation method of chip package with lid
US10163818 Package structure and method for forming the same
US10163819 Surface mount package and manufacturing method thereof
US10163820 Chip carrier and method thereof
US10163821 Packaging devices and methods for semiconductor devices
US10163822 Chip-on-substrate packaging on carrier
US10163823 Method and apparatus of ESD protection in stacked die semiconductor device
US10163824 Integrated fan-out package and method of fabricating the same
US10163825 Semiconductor structure and manufacturing method thereof
US10163826 Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
US10163827 Package structure with protrusion structure
US10163828 Semiconductor device and fabricating method thereof
US10163829 Compound semiconductor substrate and power amplifier module
US10163830 Bonding pads with thermal pathways
US10163831 Semiconductor device with post passivation structure and fabrication method therefor
US10163832 Integrated fan-out package, redistribution circuit structure, and method of fabricating the same
US10163833 Multichip modules and methods of fabrication
US10163834 Chip package structure comprising encapsulant having concave surface
US10163835 Solder bump stretching method
US10163836 Conductive external connector structure and method of forming
US10163837 Cu pillar bump with L-shaped non-metal sidewall protection structure
US10163838 Semiconductor device
US10163839 Bump on pad (BOP) bonding structure in semiconductor packaged device
US10163840 Methods of fluxless micro-piercing of solder balls, and resulting devices
US10163841 Multi-chip package and method of formation
US10163842 Semiconductor structure and manufacturing method thereof
US10163843 Semiconductor device structure and manufacturing method
US10163844 Semiconductor device having conductive bumps of varying heights
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