Browse Patents by Publication Date

Publication Number Title
US10163896 Integrated circuit having a MOM capacitor and method of making same
US10163897 Inter-level connection for multi-layer structures
US10163898 FinFETs and methods of forming FinFETs
US10163899 Temperature compensation circuits
US10163900 Integration of vertical field-effect transistors and saddle fin-type field effect transistors
US10163901 Method and device for embedding flash memory and logic integration in FinFET technology
US10163902 FinFET transistor with fin back biasing
US10163903 FETS and methods of forming FETS
US10163904 Semiconductor device structure
US10163905 Method and structure for FinFET device
US10163906 Circuit and layout for single gate type precharge circuit for data lines in memory device
US10163907 Method of maintaining the state of semiconductor memory having electrically floating body transistor
US10163908 Array of conductive lines individually extending transversally across and elevationally over a mid-portion of individual active area regions
US10163909 Methods for fabricating a semiconductor memory device
US10163910 Method of manufacturing semiconductor device
US10163911 SRAM cell with T-shaped contact
US10163912 Method for semiconductor device fabrication with improved source drain proximity
US10163913 Semiconductor device and method for fabricating the same
US10163914 Method of reducing fin width in FinFET SRAM array to mitigate low voltage strap bit fails
US10163915 Vertical SRAM structure
US10163916 Compact anti-fuse memory cell using CMOS process
US10163917 Cell disturb prevention using a leaker device to reduce excess charge from an electronic device
US10163918 Semiconductor device and method of manufacturing the same
US10163919 Embedded flash memory device with floating gate embedded in a substrate
US10163920 Memory device and memory cell
US10163921 Semiconductor device and manufacturing method of the same
US10163922 Semiconductor device and method of manufacturing the semiconductor device
US10163924 Manufacturing method of three-dimensional semiconductor memory device
US10163925 Integrated circuit device
US10163926 Memory device and method for fabricating the same
US10163927 Semiconductor memory device
US10163928 Memory having memory cell string and coupling components
US10163929 Semiconductor device including barrier pattern and metal pattern
US10163930 Semiconductor device and manufacturing method thereof
US10163931 Non-volatile semiconductor storage device and method of manufacturing the same
US10163932 Memory device based on heterostructures of ferroelectric and two-dimensional materials
US10163933 Ferro-FET device with buried buffer/ferroelectric layer stack
US10163934 Fully-depleted silicon-on-insulator transistors
US10163935 Thin film transistor, array substrate and display device
US10163936 Display device
US10163937 Pixel structure and fabricating method thereof
US10163938 Array substrate and manufacturing method thereof, and display device
US10163939 Thin film transistor array substrate and display device
US10163940 Display device
US10163941 Display apparatus
US10163942 Source driver, an image display assembly and an image display apparatus
US10163943 Display device
US10163944 Thin film transistor substrate having a plurality of stacked storage capacitors
US10163945 Printable device wafers with sacrificial layers
US10163946 Three-layer stacked image sensor
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