Great research starts with great data.

Learn More
More >
Patent Analysis of

Matrix circuit detecting failure location in common signal

Updated Time 12 June 2019

Patent Registration Data

Publication Number

US10002060

Application Number

US14/974465

Application Date

18 December 2015

Publication Date

19 June 2018

Current Assignee

FANUC CORPORATION

Original Assignee (Applicant)

FANUC CORPORATION

International Classification

G01R31/08,G01R31/02,G06F11/22

Cooperative Classification

G06F11/2221,G01R31/024,G01R31/086

Inventor

OKITA, HIROSHI

Patent Images

This patent contains figures and images illustrating the invention and its embodiment.

US10002060 Matrix circuit detecting failure location 1 US10002060 Matrix circuit detecting failure location 2 US10002060 Matrix circuit detecting failure location 3
See all images <>

Abstract

A matrix circuit includes, besides a plurality of common signal lines and a plurality of data signal lines arranged in a matrix, a plurality of monitoring signal lines that allow states of the common signal lines to be monitored. Inputs to the monitoring signal lines during one scan of the common signal lines are stored such that a fault including a ground fault, a short circuit, or disconnection on any of the common signal lines is detected and a location of the faulty common signal line is identified based on the stored inputs to the monitoring signal lines.

Read more

Claims

1. A matrix circuit of a sink type, the matrix circuit comprising: m common signal lines and n data signal lines, where m is a natural number and n is a natural number, the common signal lines and the data signal lines being arranged in a matrix; m×n switches each connected between one of the common signal lines and one of the data signal lines intersecting each other, the matrix circuit being configured such that states of keys are scanned by driving the common signal lines to a low level one by one while reading states of the data signal lines; p monitoring signal lines to allow states of the common signal lines to be monitored, where p is a natural number; a storage unit in which inputs to the monitoring signal lines during one scan of the common signal lines are stored; and a detection unit that detects occurrence of a fault including a ground fault, a short circuit, or disconnection on any of the common signal lines to identify the faulty common signal line, whereinwhen a ground fault has occurred on any of the common signal lines, the detection unit: determines that a ground fault has occurred on the common signal line when all of the inputs to the monitoring signal lines are not 0 or at a high level during a non-scan period when none of the common signal lines are driven, and determines a location of the ground fault on the common signal line based on data input to the monitoring signal lines.

2. A matrix circuit of a sink type, the matrix circuit comprising: m common signal lines and n data signal lines, where m is a natural number and n is a natural number, the common signal lines and the data signal lines being arranged in a matrix; m×n switches each connected between one of the common signal lines and one of the data signal lines intersecting each other, the matrix circuit being configured such that states of keys are scanned by driving the common signal lines to a low level one by one while reading states of the data signal lines; p monitoring signal lines to allow states of the common signal lines to be monitored, where p is a natural number; a storage unit in which inputs to the monitoring signal lines during one scan of the common signal lines are stored; and a detection unit that detects occurrence of a fault including a ground fault, a short circuit, or disconnection on any of the common signal lines to identify the faulty common signal line, whereinwhen a ground fault has occurred on any of the common signal lines, the detection unit: detects occurrence of a fault on the common signal line and stores the inputs to the monitoring signal lines for one scan in the storage unit when the inputs to the monitoring signal lines during the scan are different from the inputs to the monitoring signal lines during a normal period, further determines that the fault on the common signal line is a ground fault when the stored inputs to the monitoring signal lines are constantly 1 or at a low level, and determines a location of the ground fault on the common signal line based on data input to the monitoring signal lines and stored in the storage unit.

3. A matrix circuit of a sink type, the matrix circuit comprising: m common signal lines and n data signal lines, where m is a natural number and n is a natural number, the common signal lines and the data signal lines being arranged in a matrix; m×n switches each connected between one of the common signal lines and one of the data signal lines intersecting each other, the matrix circuit being configured such that states of keys are scanned by driving the common signal lines to a low level one by one while reading states of the data signal lines; p monitoring signal lines to allow states of the common signal lines to be monitored, where p is a natural number; a storage unit in which inputs to the monitoring signal lines during one scan of the common signal lines are stored; and a detection unit that detects occurrence of a fault including a ground fault, a short circuit, or disconnection on any of the common signal lines to identify the faulty common signal line, whereinwhen a short circuit has occurred on any of the common signal lines, the detection unit: detects occurrence of a fault on the common signal line and stores the inputs to the monitoring signal lines for one scan in the storage unit when the inputs to the monitoring signal lines during the scan are different from the inputs to the monitoring signal lines during a normal period, further determines that the fault on the common signal line is a short circuit when the stored inputs to the monitoring signal lines are the same as the inputs to the monitoring signal lines during a different scan of the common signal lines, and determines a location of the short circuit on the common signal line based on data input to the monitoring signal lines and stored in the storage unit.

4. A matrix circuit of a sink type, the matrix circuit comprising: m common signal lines and n data signal lines, where m is a natural number and n is a natural number, the common signal lines and the data signal lines being arranged in a matrix; m×n switches each connected between one of the common signal lines and one of the data signal lines intersecting each other, the matrix circuit being configured such that states of keys are scanned by driving the common signal lines to a low level one by one while reading states of the data signal lines; p monitoring signal lines to allow states of the common signal lines to be monitored, where p is a natural number; a storage unit in which inputs to the monitoring signal lines during one scan of the common signal lines are stored; and a detection unit that detects occurrence of a fault including a ground fault, a short circuit, or disconnection on any of the common signal lines to identify the faulty common signal line, whereinwhen disconnection has occurred on any of the common signal lines, the detection unit: detects occurrence of a fault on the common signal line and stores the inputs to the monitoring signal lines for one scan in the storage unit when the inputs to the monitoring signal lines during the scan are different from the inputs to the monitoring signal lines during a normal period, further determines that the fault on the common signal line is disconnection when all of the stored inputs to the monitoring signal line are 0 or at a high level, and determines a location of the disconnection on the common signal line based on data input to the monitoring signal lines and stored in the storage unit.

5. A matrix circuit of a sink type, the matrix circuit comprising: m common signal lines and n data signal lines, where m is a natural number and n is a natural number, the common signal lines and the data signal lines being arranged in a matrix; m×n switches each connected between one of the common signal lines and one of the data signal lines intersecting each other, the matrix circuit being configured such that states of keys are scanned by driving the common signal lines to a low level one by one while reading states of the data signal lines; p monitoring signal lines to allow states of the common signal lines to be monitored, where p is a natural number; and a detection unit that detects a ground fault on any of the common signal lines and that identifies the common signal line on which the ground fault has occurred, whereinwhen a ground fault has occurred on any of the common signal lines, the detection unit: determines that a ground fault has occurred on the common signal line when all of the inputs to the monitoring signal lines are not 0 or at a high level during a non-scan period when none of the common signal lines are driven, and determines a location of the ground fault on the common signal line based on data input to the monitoring signal lines.

6. A matrix circuit of a source type, the matrix circuit comprising: m common signal lines and n data signal lines, where m is a natural number and n is a natural number, the common signal lines and the data signal lines being arranged in a matrix; m×n switches each connected between one of the common signal lines and one of the data signal lines intersecting each other, the matrix circuit being configured such that states of keys are scanned by driving the common signal lines to a high level one by one while reading states of the data signal lines; p monitoring signal lines to allow states of the common signal lines to be monitored, where p is a natural number; a storage unit in which inputs to the monitoring signal lines during one scan of the common signal lines are stored; and a detection unit that detects occurrence of a fault including a ground fault, a short circuit, or disconnection on any of the common signal lines to identify the faulty common signal line, whereinwhen a ground fault or disconnection has occurred on any of the common signal lines, the detection unit: detects occurrence of a fault on the common signal line and stores the inputs to the monitoring signal lines for one scan in the storage unit when the inputs to the monitoring signal lines during the scan are different from the inputs to the monitoring signal lines during a normal period, further determines that the fault on the common signal line is a ground fault or disconnection when all of the stored inputs to the monitoring signal line are 0 or at a high level, and determines a location of the ground fault or the disconnection on the common signal line based on data input to the monitoring signal lines and stored in the storage unit.

Read more

Claim Tree

  • 1
    1. A matrix circuit of a sink type, the matrix circuit comprising:
    • m common signal lines and n data signal lines, where m is a natural number and n is a natural number, the common signal lines and the data signal lines being arranged in a matrix
    • m×n switches each connected between one of the common signal lines and one of the data signal lines intersecting each other, the matrix circuit being configured such that states of keys are scanned by driving the common signal lines to a low level one by one while reading states of the data signal lines
    • p monitoring signal lines to allow states of the common signal lines to be monitored, where p is a natural number
    • a storage unit in which inputs to the monitoring signal lines during one scan of the common signal lines are stored
    • and a detection unit that detects occurrence of a fault including a ground fault, a short circuit, or disconnection on any of the common signal lines to identify the faulty common signal line, whereinwhen a ground fault has occurred on any of the common signal lines, the detection unit: determines that a ground fault has occurred on the common signal line when all of the inputs to the monitoring signal lines are not 0 or at a high level during a non-scan period when none of the common signal lines are driven, and determines a location of the ground fault on the common signal line based on data input to the monitoring signal lines.
  • 2
    2. A matrix circuit of a sink type, the matrix circuit comprising:
    • m common signal lines and n data signal lines, where m is a natural number and n is a natural number, the common signal lines and the data signal lines being arranged in a matrix
    • m×n switches each connected between one of the common signal lines and one of the data signal lines intersecting each other, the matrix circuit being configured such that states of keys are scanned by driving the common signal lines to a low level one by one while reading states of the data signal lines
    • p monitoring signal lines to allow states of the common signal lines to be monitored, where p is a natural number
    • a storage unit in which inputs to the monitoring signal lines during one scan of the common signal lines are stored
    • and a detection unit that detects occurrence of a fault including a ground fault, a short circuit, or disconnection on any of the common signal lines to identify the faulty common signal line, whereinwhen a ground fault has occurred on any of the common signal lines, the detection unit: detects occurrence of a fault on the common signal line and stores the inputs to the monitoring signal lines for one scan in the storage unit when the inputs to the monitoring signal lines during the scan are different from the inputs to the monitoring signal lines during a normal period, further determines that the fault on the common signal line is a ground fault when the stored inputs to the monitoring signal lines are constantly 1 or at a low level, and determines a location of the ground fault on the common signal line based on data input to the monitoring signal lines and stored in the storage unit.
  • 3
    3. A matrix circuit of a sink type, the matrix circuit comprising:
    • m common signal lines and n data signal lines, where m is a natural number and n is a natural number, the common signal lines and the data signal lines being arranged in a matrix
    • m×n switches each connected between one of the common signal lines and one of the data signal lines intersecting each other, the matrix circuit being configured such that states of keys are scanned by driving the common signal lines to a low level one by one while reading states of the data signal lines
    • p monitoring signal lines to allow states of the common signal lines to be monitored, where p is a natural number
    • a storage unit in which inputs to the monitoring signal lines during one scan of the common signal lines are stored
    • and a detection unit that detects occurrence of a fault including a ground fault, a short circuit, or disconnection on any of the common signal lines to identify the faulty common signal line, whereinwhen a short circuit has occurred on any of the common signal lines, the detection unit: detects occurrence of a fault on the common signal line and stores the inputs to the monitoring signal lines for one scan in the storage unit when the inputs to the monitoring signal lines during the scan are different from the inputs to the monitoring signal lines during a normal period, further determines that the fault on the common signal line is a short circuit when the stored inputs to the monitoring signal lines are the same as the inputs to the monitoring signal lines during a different scan of the common signal lines, and determines a location of the short circuit on the common signal line based on data input to the monitoring signal lines and stored in the storage unit.
  • 4
    4. A matrix circuit of a sink type, the matrix circuit comprising:
    • m common signal lines and n data signal lines, where m is a natural number and n is a natural number, the common signal lines and the data signal lines being arranged in a matrix
    • m×n switches each connected between one of the common signal lines and one of the data signal lines intersecting each other, the matrix circuit being configured such that states of keys are scanned by driving the common signal lines to a low level one by one while reading states of the data signal lines
    • p monitoring signal lines to allow states of the common signal lines to be monitored, where p is a natural number
    • a storage unit in which inputs to the monitoring signal lines during one scan of the common signal lines are stored
    • and a detection unit that detects occurrence of a fault including a ground fault, a short circuit, or disconnection on any of the common signal lines to identify the faulty common signal line, whereinwhen disconnection has occurred on any of the common signal lines, the detection unit: detects occurrence of a fault on the common signal line and stores the inputs to the monitoring signal lines for one scan in the storage unit when the inputs to the monitoring signal lines during the scan are different from the inputs to the monitoring signal lines during a normal period, further determines that the fault on the common signal line is disconnection when all of the stored inputs to the monitoring signal line are 0 or at a high level, and determines a location of the disconnection on the common signal line based on data input to the monitoring signal lines and stored in the storage unit.
  • 5
    5. A matrix circuit of a sink type, the matrix circuit comprising:
    • m common signal lines and n data signal lines, where m is a natural number and n is a natural number, the common signal lines and the data signal lines being arranged in a matrix
    • m×n switches each connected between one of the common signal lines and one of the data signal lines intersecting each other, the matrix circuit being configured such that states of keys are scanned by driving the common signal lines to a low level one by one while reading states of the data signal lines
    • p monitoring signal lines to allow states of the common signal lines to be monitored, where p is a natural number
    • and a detection unit that detects a ground fault on any of the common signal lines and that identifies the common signal line on which the ground fault has occurred, whereinwhen a ground fault has occurred on any of the common signal lines, the detection unit: determines that a ground fault has occurred on the common signal line when all of the inputs to the monitoring signal lines are not 0 or at a high level during a non-scan period when none of the common signal lines are driven, and determines a location of the ground fault on the common signal line based on data input to the monitoring signal lines.
  • 6
    6. A matrix circuit of a source type, the matrix circuit comprising:
    • m common signal lines and n data signal lines, where m is a natural number and n is a natural number, the common signal lines and the data signal lines being arranged in a matrix
    • m×n switches each connected between one of the common signal lines and one of the data signal lines intersecting each other, the matrix circuit being configured such that states of keys are scanned by driving the common signal lines to a high level one by one while reading states of the data signal lines
    • p monitoring signal lines to allow states of the common signal lines to be monitored, where p is a natural number
    • a storage unit in which inputs to the monitoring signal lines during one scan of the common signal lines are stored
    • and a detection unit that detects occurrence of a fault including a ground fault, a short circuit, or disconnection on any of the common signal lines to identify the faulty common signal line, whereinwhen a ground fault or disconnection has occurred on any of the common signal lines, the detection unit: detects occurrence of a fault on the common signal line and stores the inputs to the monitoring signal lines for one scan in the storage unit when the inputs to the monitoring signal lines during the scan are different from the inputs to the monitoring signal lines during a normal period, further determines that the fault on the common signal line is a ground fault or disconnection when all of the stored inputs to the monitoring signal line are 0 or at a high level, and determines a location of the ground fault or the disconnection on the common signal line based on data input to the monitoring signal lines and stored in the storage unit.
See all independent claims <>

Description

RELATED APPLICATIONS

The present application claims priority to Japanese Application Number 2014-257498, filed Dec. 19, 2014, the disclosure of which is hereby incorporated by reference herein in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a matrix circuit that detects a fault location in a common signal.

2. Description of the Related Art

An input apparatus using a matrix circuit is well known. As an example of such an input apparatus, a circuit for a keyboard using a general sinking matrix circuit as disclosed in Japanese Patent Application Laid-open No. S61-058025 will be described with reference to FIG. 17.

In a general sinking matrix circuit, common signal lines (XCOM) and data signal lines (XKEYD) are arranged like a lattice, with key switches arranged on these lines. An example in FIG. 17 is a sinking matrix circuit with seven common signal lines and eight data signal lines. The matrix circuit allows detection of inputs (key information) the number of which results from multiplication of the number of common signal lines by the number of data signal lines. Thus, in this circuit allows information on 56 keys to be detected. Diodes in FIG. 17 are connected together in order to prevent signals from sneaking when a plurality of key are depressed.

The key information is scanned using an ASIC or the like to drive the common signal lines in order to allow data on the data signal lines to be loaded. When a key is depressed, the common signal line to which the key is connected is driven to enable bits on the data signal line to which the key is connected, allowing the depression of the key to be recognized. For example, in FIG. 17, when a circled key switch is depressed, a common signal line XCOM2 to which the key switch is connected is driven to enable a data signal line XKEYD4. This is detected to allow the depression of the key switch at the corresponding position to be recognized.

The circuit in FIG. 17 is a sink circuit, and the common signal line is scanned by being driven low. At this time, when a data signal is low, the corresponding key switch is determined to have been depressed. Some matrix circuits are of a source type. In a sourcing matrix circuit, the common signal line is scanned by being driven high. A high input to the data signal line allows depression of the key to be recognized.

The matrix circuit allows a large amount of input information to be obtained using a smaller number of signal lines. However, a possible ground fault, short-circuit, or disconnection on the common signal lines and the data signal lines causes an erroneous input to be detected, leading to malfunction. Thus, whether a ground fault, a short-circuit, or disconnection has occurred or not and the location of the occurrence need to be determined.

When a fault occurs on the data signal lines, a phenomenon resulting from the fault and an occurrence condition for the phenomenon other than the fault on the data line are as follows.

<Ground Fault on the Data Signal Line>

    • Phenomenon: all the keys connected to the data line on which a ground fault has occurred are input even when the keys are not depressed.
    • Failure portion on the data signal lines: the data signal line to which the input keys are connected
    • Cause of a fault on the common signal line leading to the phenomenon: none

      <Short Circuit on the Data Signal Line>

    • Phenomenon: depressing one key causes another short-circuited key to be input.
    • Failure portion on the data signal lines: the data signal line to which the two input keys are connected
    • Cause of a fault on the common signal line leading to the phenomenon: a short circuit on the common signal line

      <Disconnection of the Data Signal Line>

    • Phenomenon: nothing is input in spite of depression of a key.
    • Failure portion on the data signal lines: the data signal line to which the key that has failed to be input is connected.
    • Cause of a fault on the common signal line leading to the phenomenon: disconnection of the common signal line

As described above, when a fault occurs on any data signal line, the location of the fault on the data signal lines can be relatively easily detected if the fault is determined not to have been caused by any common signal line. However, when a fault occurs on any common signal line, the location of the fault disadvantageously fails to be easily detected depending on the contents of the fault.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a matrix circuit that enables determination of the cause of a fault occurring on common signal lines and the location of the fault.

A first aspect of a matrix circuit according to the present invention is a matrix circuit of a sink type having m (m is a natural number) common signal lines and n (n is a natural number) data signal lines, the common signal lines and the data signal lines being arranged in a matrix, and m×n switches each connected between the common signal line and the data signal line intersecting each other, the matrix circuit being configured such that states of keys are scanned by driving the common signal lines to a low level one by one while reading states of the data signal lines, the matrix circuit having p (p is a natural number) monitoring signal lines that allow states of the common signal lines to be monitored, a storage unit in which inputs to the monitoring signal lines during one scan of the common signal lines are stored, and a detection unit that detects occurrence of a fault including a ground fault, a short circuit, or disconnection on any of the common signal lines to identify the faulty common signal line.

When a ground fault has occurred on any of the common signal lines, the detection unit may determine that a ground fault has occurred on the common signal line when all of the inputs to the monitoring signal lines are not 0 or at a high level during a non-scan period when none of the common signal lines are driven, and determine a location of the ground fault on the common signal line based on data input to the monitoring signal lines.

When a ground fault has occurred on any of the common signal lines, the detection unit may detect occurrence of a fault on the common signal line and store the inputs to the monitoring signal lines for one scan in the storage unit when the inputs to the monitoring signal lines during the scan are different from the inputs to the monitoring signal lines during a normal period, further determine that the fault on the common signal line is a ground fault when the stored inputs to the monitoring signal lines are constantly 1 (low level), and determine a location of the ground fault on the common signal line based on data input to the monitoring signal lines and stored in the storage unit.

When a short circuit has occurred on any of the common signal lines, the detection unit may detect occurrence of a fault on the common signal line and store the inputs to the monitoring signal lines for one scan in the storage unit when the inputs to the monitoring signal lines during the scan are different from the inputs to the monitoring signal lines during a normal period, further determine that the fault on the common signal line is a short circuit when the stored inputs to the monitoring signal lines are the same as the inputs to the monitoring signal lines during a different scan of the common signal lines, and determine a location of the short circuit on the common signal line based on data input to the monitoring signal lines and stored in the storage unit.

When disconnection has occurred on any of the common signal lines, the detection unit may detect occurrence of a fault on the common signal line and store the inputs to the monitoring signal lines for one scan in the storage unit when the inputs to the monitoring signal lines during the scan are different from the inputs to the monitoring signal lines during a normal period, further determine that the fault on the common signal line is disconnection when all of the stored inputs to the monitoring signal line are 0 (high level) and determine a location of the disconnection on the common signal line based on data input to the monitoring signal lines and stored in the storage unit.

In the matrix circuit, the inputs to the monitoring signal lines during a non-scan period and during a scan period may be output to a display unit when the fault occurs.

A second aspect of a matrix circuit according to the present invention is a matrix circuit of a sink type having m (m is a natural number) common signal lines and n (n is a natural number) data signal lines, the common signal lines and the data signal lines being arranged in a matrix, and m×n switches each connected between the common signal line and the data signal line intersecting each other, the matrix circuit being configured such that states of keys are scanned by driving the common signal lines to a low level one by one while reading states of the data signal lines, the matrix circuit having p (p is a natural number) monitoring signal lines that allow states of the common signal lines to be monitored, and a detection unit that detects a ground fault on any of the common signal lines and that identifies the common signal line on which the ground fault has occurred.

When a ground fault has occurred on any of the common signal lines, the detection unit may determine that a ground fault has occurred on the common signal line when all of the inputs to the monitoring signal lines are not 0 or at a high level during a non-scan period when none of the common signal lines are driven, and determine a location of the ground fault on the common signal line based on data input to the monitoring signal lines.

In the matrix circuit, the inputs to the monitoring signal lines during a non-scan period may be output to a display unit when the fault occurs.

A third aspect of a matrix circuit according to the present invention is a matrix circuit of a source type having m (m is a natural number) common signal lines and n (n is a natural number) data signal lines, the common signal lines and the data signal lines being arranged in a matrix, and m×n switches each connected between the common signal line and the data signal line intersecting each other, the matrix circuit being configured such that states of keys are scanned by driving the common signal lines to a high level one by one while reading states of the data signal lines, the matrix circuit having p (p is a natural number) monitoring signal lines that allow states of the common signal lines to be monitored, a storage unit in which inputs to the monitoring signal lines during one scan of the common signal lines are stored, and a detection unit that detects occurrence of a fault including a ground fault, a short circuit, or disconnection on any of the common signal lines to identify the faulty common signal line.

When a short circuit has occurred on any of the common signal lines, the detection unit may detect occurrence of a fault on the common signal line and store the inputs to the monitoring signal lines for one scan in the storage unit when the inputs to the monitoring signal lines during the scan are different from the inputs to the monitoring signal lines during a normal period, further determine that the fault on the common signal line is a short circuit when the stored inputs to the monitoring signal lines are the same as the inputs to the monitoring signal lines during a different scan of the common signal lines, and determine a location of the short circuit on the common signal line based on data input to the monitoring signal lines and stored in the storage unit.

In the matrix circuit, the inputs to the monitoring signal lines during a non-scan period and during a scan period are output to a display unit when the fault occurs.

When a ground fault or disconnection has occurred on any of the common signal lines, the detection unit may detect occurrence of a fault on the common signal line and store the inputs to the monitoring signal lines for one scan in the storage unit when the inputs to the monitoring signal lines during the scan are different from the inputs to the monitoring signal lines during a normal period, further determine that the fault on the common signal line is a ground fault or disconnection when all of the stored inputs to the monitoring signal line are 0 (high level), and determine a location of the ground fault or the disconnection on the common signal line based on data input to the monitoring signal lines and stored in the storage unit.

According to the present invention, the p (p is a natural number) monitoring signal lines (XCOMD0 to XCOMDp−1) are added to the common signal lines in the matrix circuit such that the inputs to the monitoring signal lines during sequential scan of all of the common signals are stored and analyzed. This enables detection of occurrence of a ground fault, a short circuit, or disconnection on the common signal lines and identification of the faulty common signal line, which are impossible with the related art.

BRIEF DESCRIPTION OF THE DRAWINGS

The forgoing and other objects and features of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings, in which:

FIG. 1 is a diagram of a configuration of a first embodiment of a matrix circuit according to the present invention;

FIG. 2 is a table illustrating inputs to monitoring signal lines in the matrix circuit in FIG. 1 during a normal period;

FIG. 3 is a table illustrating inputs to the monitoring signal lines in the matrix circuit in FIG. 1 during a non-scan period when a ground fault has occurred;

FIG. 4 is a table illustrating inputs to the monitoring signal lines in the matrix circuit in FIG. 1 during a scan period when a ground fault has occurred;

FIG. 5 is a table illustrating inputs to the monitoring signal lines in the matrix circuit in FIG. 1 during a scan period when a ground fault has occurred;

FIG. 6 is a table illustrating inputs the monitoring signal lines in the matrix circuit in FIG. 1 during a scan period when disconnection has occurred;

FIG. 7 is a diagram illustrating a display example of a diagnosis screen of the matrix circuit in FIG. 1;

FIG. 8 is a flowchart of a fault diagnosis process by the matrix circuit in FIG. 1;

FIG. 9 is a diagram of a configuration of a second embodiment of the matrix circuit according to the present invention;

FIG. 10 is a is a table illustrating inputs to monitoring signal lines in the matrix circuit in FIG. 9 during a non-scan period when a ground fault has occurred;

FIG. 11 is a diagram of a configuration of the second embodiment of the matrix circuit according to the present invention;

FIG. 12 is a table illustrating inputs to monitoring signal lines in the matrix circuit in FIG. 11 during a normal period;

FIG. 13 is a table illustrating inputs to the monitoring signal lines in the matrix circuit in FIG. 11 during a scan period when a ground fault or disconnection has occurred;

FIG. 14 is a table illustrating inputs to the monitoring signal lines in the matrix circuit in FIG. 11 during a scan period when a short circuit has occurred;

FIG. 15 is a diagram illustrating a display example of a diagnosis screen of the matrix circuit in FIG. 11;

FIG. 16 is a flowchart of a fault diagnosis process by the matrix circuit in FIG. 11; and

FIG. 17 is a diagram of a configuration of a matrix circuit according to the related art.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

First, a first embodiment of a matrix circuit according to the present invention will be described using FIGS. 1 to 8.

FIG. 1 is a diagram depicting the matrix circuit according to the first embodiment of the present invention.

The matrix circuit according to the present embodiment is a sinking matrix circuit with seven common signal lines (XCOMs, XCOM1 to XCOM7) and eight data signal lines (XKEYDs, XKEYD0 to XKEYD7). The matrix circuit depicted in FIG. 1 corresponds to a general sinking matrix circuit to which monitoring signal lines (XCOMD) are added.

In the present embodiment, the monitoring signal lines are connected so as to convert data on the common signal lines into binary codes, allowing the seven common signal lines to be monitored by the three monitoring signal lines, XCOMD2, the XCOMD1, and the XCOMD0. In the matrix circuit depicted in FIG. 1, diodes are assembled in the circuit in order to prevent possible sneaking of signals. In scan processing, the common signal lines are driven to allow key information to be loaded through the data signal lines. At this time, inputs to the monitoring signal lines are loaded to allow the states of the common signal lines to be monitored.

A table in FIG. 2 indicates inputs to the monitoring signal lines during a normal period. Three-digit binary values in the table represent values for the XCOMD2, the XCOMD1, and the XCOMD0 in accordance with negative logic (low input is represented as 1, and high input is represented as 0) and are arranged in order. During a non-scan period when none of the common signal lines is driven, “000” is input to the monitoring signal lines. During a scan period when the common signal lines are driven in order, signals with the binarized numbers of the common signal lines being driven are input through the monitoring signal lines.

In the matrix circuit configured as depicted in FIG. 1, when a fault such as a ground fault, a short-circuit, or disconnection occurs on the common signal lines, the inputs to the monitoring signal lines are detected which are different from inputs to the monitoring signal lines during the normal period indicated in the table in FIG. 2. When inputs different from the inputs during the normal period are detected, the inputs for one scan are stored in a memory 2 provided in an ASIC 1 and used to determine the location of the fault. A method for detecting the location of a fault will be described below for each cause of the fault.

<1.1 Method for Detecting the Location of a Ground Fault on the Common Signal Lines>

A table in FIG. 3 indicates input values input to the monitoring signal lines during the non-scan period (state where none of the common signal lines is driven).

As indicated in the table in FIG. 3, when the common signal lines are normal, a value “000” is input through the signal lines during the non-scan period. However, when a ground fault occurs on any of the common signal lines, 1 (low level) is detected in some of the monitoring signal lines during the non-scan period when none of the common signal lines is driven. As in the table in FIG. 3, the inputs to the monitoring signal lines each indicate the number of the common signal line on which a ground fault has occurred.

A table in FIG. 4 illustrates another detection method used when a ground fault has occurred on the common signal lines.

The table in FIG. 4 indicates input values input to the monitoring signal lines when a ground fault has occurred on any of the common signal lines. When a ground fault occurs on the common signal lines, a signal with a value fixed to 1 is observed in the inputs to the monitoring signal lines during a scan period. In this case, the location of the ground fault can be determined by performing an AND operation on data on the monitoring signal lines for one scan. For example, when a ground fault occurs on the common signal line XCOM3, the data for one scan is “011”, “011”, “011”, “111”, “111”, “111”, and “111”. Performing an AND operation on all of these values results in “011”, whereby it is possible to determine that a ground fault has occurred on the common signal line XCOM3.

<1.2 Method for Detecting the Location of a Short Circuit on the Common Signal Lines>

A table in FIG. 5 indicates input values input to the monitoring signal lines when a short circuit occurs on the common signal lines. When a short circuit occurs on the common signal lines, the same input is detected at two or three locations on the monitoring signal lines.

When the same input is detected at two locations, a short circuit has occurred on common signal lines being driven when the same input is detected. For example, when the common signal line XCOM2 and the common signal line XCOM3 are short-circuited, a pattern in which both common signal lines involve the input “011” is detected at two locations. The common signal lines XCOM2 and XCOM3 being driven when the same input is detected at the two locations are determined to be the locations of the short circuit.

When the same input is detected at three locations, a short circuit has occurred at two locations other than the common signal line indicated by the input (the common signal line for which, during the normal period, the input is detected through the monitoring signal lines when the common signal line is driven). For example, when the XCOM3 and the XCOM4 are short-circuited, the input of “111” is detected at three locations. In this case, the common signal lines indicated by “111” other than the XCOM7, that is, the XCOM3 and the XCOM4, are the locations of the short circuit.

The table in FIG. 5 indicates only the short circuits on the adjacent signals. However, when a short circuit is likely to occur on any other combination of common signal lines, the combination may be added to the table in FIG. 5 and used to detect the short circuit.

<1.3 Method for Detecting the Location of Disconnection on the Common Signal Lines>

A table in FIG. 6 indicates input values input to the monitoring signal lines when disconnection occurs on the common signal lines. When disconnection occurs on the common signal lines, the inputs to the monitoring signal lines are “000” when the common signal line on which disconnection has occurred is driven. The common signal line being driven when “000” is detected in the inputs to the monitoring signal line can be detected as the location of disconnection.

<1.4 Screen Display of the Monitoring Signal Lines>

The states of the monitoring signal lines saved in the memory 2 can be displayed on a diagnosis screen along with values expected to be detected through the monitoring signal lines during the normal period. FIG. 7 depicts a display example of the diagnosis screen. When the common signal lines to be driven, the values expected to be detected through the monitoring signal lines during the normal period, and measured values detected through the monitoring signal lines are arranged in the screen as depicted in FIG. 7, an operator can determine a failure occurring on the common signal lines.

<1.5 Flowchart of a Fault Diagnosis Process through the Monitoring Signal Lines>

FIG. 8 is a flowchart of a fault diagnosis process using the monitoring signal lines.

    • [Step SA01] It is determined whether or not the input to each of the monitoring signal lines during the non-scan period for the common signal lines is “000”. When the input to the monitoring signal line during the non-scan period for the common signal lines is not “000”, the process proceeds to step SA02. When the input to the monitoring signal line during the non-scan period for the common signal lines is “000”, the process proceeds to step SA05.
    • [Step SA02] It is determined whether or not the inputs to the monitoring signal lines during the non-scan period has a corresponding pattern in the table in FIG. 3. When the inputs to the monitoring signal lines during the non-scan period has a corresponding pattern in the table in FIG. 3, the process proceeds to step SA03. When the inputs to the monitoring signal lines during the non-scan period has no corresponding pattern in the table in FIG. 3, the process proceeds to step SA04.
    • [Step SA03] It is determined that a ground fault has occurred on the corresponding common signal line in the table in FIG. 3.
    • [Step SA04] It is determined that a fault other than a ground fault, a short circuit, and disconnection has occurred.
    • [Step SA05] It is determined whether or not the inputs to the monitoring signal lines during a scan of the common signal lines are the same as normal values. When the inputs to the monitoring signal lines during the scan are the same as the normal values, the process returns to step SA01. When the inputs to the monitoring signal lines during the scan are different from the normal values, the process proceeds to step SA06.
    • [Step SA06] The inputs to the monitoring signal lines during one scan of the common signal lines are stored in the memory.
    • [Step SA07] It is determined whether or not the inputs to the monitoring signal lines for one scan stored in step SA06 include a value “000”. When the inputs to the monitoring signal lines for one scan stored in step SA06 include the value “000”, the process proceeds to SA08. When the inputs to the monitoring signal lines for one scan stored in step SA06 do not include the value “000”, the process proceeds to SA11.
    • [Step SA08] It is determined to whether or not the inputs to the monitoring signal lines for one scan stored in step SA06 correspond to any of the patterns in the table in FIG. 6. When the inputs to the monitoring signal lines for one scan stored in step SA06 correspond to one of the patterns in the table in FIG. 6, the process proceeds to step SA09. When the inputs to the monitoring signal lines for one scan stored in step SA06 correspond to none of the patterns in the table in FIG. 6, the process proceeds to step SA10.
    • [Step SA09] It is determined that disconnection has occurred on the corresponding common signal line in the table in FIG. 6.
    • [Step SA10] It is determined that a fault other than a ground fault, a short circuit, and disconnection has occurred.
    • [Step SA11] It is determined whether or not the inputs to the monitoring signal lines for one scan stored in step SA06 are the same at certain locations on the monitoring signal lines. When the inputs to the monitoring signal lines for one scan stored in step SA06 are the same at certain locations on the monitoring signal lines, the process proceeds to step SA12. When the inputs to the monitoring signal lines for one scan stored in step SA06 are not the same at any locations on the monitoring signal lines, the process proceeds to step SA15.
    • [Step SA12] It is determined whether or not the inputs to the monitoring signal lines for one scan stored in step SA06 correspond to any of the patterns in the table in FIG. 5. When the inputs to the monitoring signal lines for one scan stored in step SA06 correspond to one of the patterns in the table in FIG. 5, the process proceeds to step SA13. When the inputs to the monitoring signal lines for one scan stored in step SA06 correspond to none of the patterns in the table in FIG. 5, the process proceeds to step SA14.
    • [Step SA13] It is determined that a short circuit has occurred on the corresponding common signal line in the table in FIG. 5.
    • [Step SA14] It is determined that a fault other than a ground fault, a short circuit, and disconnection has occurred.
    • [Step SA15] It is determined that a fault other than a ground fault, a short circuit, and disconnection has occurred.

Now, a second embodiment of the matrix circuit according to the present invention will be described using FIG. 9 and FIG. 10.

FIG. 9 is a diagram depicting a matrix circuit according to the second embodiment of the present invention.

The matrix circuit according to the present embodiment is a sinking matrix circuit with seven common signal lines (XCOMs, XCOM1 to XCOM7) and eight data signal lines (XKEYDs, XKEYD0 to XKEYD7). Unlike in the first embodiment, the matrix circuit depicted in FIG. 9 limits the fault location detection target to ground faults only and implements detection of a ground fault using only input signals input through the monitoring signal lines (XCOMD). In the matrix circuit in FIG. 9, diodes are assembled in the circuit in order to prevent sneaking of signals.

During the non-scan period when none of the common signal lines is driven, “000” is detected in the inputs to the monitoring signal lines during the normal period. However, when a ground fault occurs, any of the inputs to the monitoring signal lines exhibits a value other than “000” as illustrated in the table in FIG. 10. Thus, monitoring the monitoring signal lines allows detection of occurrence of a ground fault on the common signal lines.

Now, a third embodiment of the matrix circuit according to the present invention will be described using FIGS. 11 to 16.

FIG. 11 is a diagram depicting a matrix circuit according to the third embodiment of the present invention.

The matrix circuit according to the present embodiment is a sourcing matrix circuit with seven common signal lines (COMs, COM1 to COM7) and eight data signal lines (KEYDs, KEYD0 to KEYD7). The matrix circuit depicted in FIG. 11 corresponds to a general sinking matrix circuit to which monitoring signal lines (COMD) are added.

In the present embodiment, the monitoring signal lines are connected so as to convert data on the common signal lines into binary codes, allowing seven common signal lines to be monitored using three monitoring signal lines COMD2, COMD1, and COMD0. In the matrix circuit in FIG. 11, diodes are assembled in the circuit in order to prevent sneaking of signals. In scan processing, the common signal lines are driven to allow key information to be loaded through the data signal lines. At this time, the inputs to the monitoring signal lines are loaded to allow the states of the common signal lines to be monitored.

A table in FIG. 12 indicates inputs to the monitoring signal lines during the normal period. Three-digit binary values in the table represent values for the COMD2, the COMD1, and the COMD0 in accordance with positive logic (low input is represented as 0, and high input is represented as 1) and are arranged in order. During the non-scan period when none of the common signal lines is driven, “000” is input to the monitoring signal lines. During the scan period when the common signal lines are driven in order, signals with the binarized numbers of the common signal lines being driven are input through the monitoring signal lines.

In the matrix circuit configured as depicted in FIG. 11, when a fault such as a ground fault, a short-circuit, or disconnection occurs on the common signal lines, inputs to the monitoring signal lines are detected which are different from the inputs to the monitoring signal lines during the normal period indicated in the table in FIG. 12. When inputs different from the inputs during the normal period are detected, the inputs for one scan are stored in the memory 2 provided in the ASIC 1 and used to determine the location of the fault. A method for detecting the location of a fault will be described below for each cause of the fault.

<3.1 Method for Detecting the Location of a Ground Fault or Disconnection on the Common Signal Lines>

A table in FIG. 13 indicates input values input to the monitoring signal lines when a ground fault or disconnection occurs on the common signal lines.

When a ground fault or disconnection occurs on any of the common signal lines, the inputs to corresponding monitoring signal lines exhibit “000” when the faulty common signal line is driven. Therefore, the common signal line being driven when “000” is detected in the inputs to the monitoring signal line is determined to be the location of the ground fault or disconnection.

<3.2 Method for Detecting the Location of a Short Circuit on the Common Signal Lines>

A table in FIG. 14 indicates input values input to the monitoring signal lines when a short circuit occurs on the common signal lines.

When a short circuit occurs on the common signal lines, the same input is detected at two or three locations on the monitoring signal lines.

When the same input is detected at two locations, a short circuit has occurred on common signal lines being driven. For example, when the common signal line COM2 and the common signal line COM3 are short-circuited, the input “011” is detected at two locations. The common signal lines COM2 and COM3 being driven when the same input is detected at the two locations are determined to be the locations of the short circuit.

When the same input is detected at three locations, a short circuit has occurred at two locations other than the common signal line indicated by the input (the common signal line for which, during the normal period, the input is detected through the monitoring signal lines when the common signal line is driven). For example, when the COM3 and the COM4 are short-circuited, the input of “111” is detected at three locations. In this case, the common signal lines indicated by “111” other than the COM7, that is, the COM3 and the COM4, are the locations of the short circuit.

The table in FIG. 14 indicates only the short circuits on the adjacent signals. However, when a short circuit is likely to occur on any other combination of common signal lines, the combination may be added to the table in FIG. 14 and used to detect the short circuit.

<3.3 Screen Display of the Monitoring Signal Lines>

The states of the monitoring signal lines saved in the memory 2 can be displayed on a diagnosis screen along with values expected to be detected through the monitoring signal lines during the normal period. FIG. 15 depicts a display example of the diagnosis screen. When the common signal lines to be driven, the values expected to be detected through the monitoring signal lines during the normal period, and measured values detected through the monitoring signal lines are arranged in the screen as depicted in FIG. 15, an operator can determine a failure occurring on the common signal lines.

<3.4 Flowchart of a Fault Diagnosis Process through the Monitoring Signal Lines>

FIG. 16 is a flowchart of a fault diagnosis process using the monitoring signal lines.

    • [Step SB01] It is determined whether or not the input to each of the monitoring signal lines during a scan of the common signal lines is the same as the normal value. When the input to the monitoring signal line during the scan of the common signal lines is the same as the normal value, the process returns to step SB01. When the input to the monitoring signal line during the scan of the common signal lines is different from the normal value, the process proceeds to step SB02.
    • [Step SB02] The inputs to the monitoring signal lines during one scan of the common signal lines are stored in the memory.
    • [Step SB03] It is determined whether or not the inputs to the monitoring signal lines for one scan stored in step SB02 include the value “000”. When the inputs to the monitoring signal lines for one scan of the common signal lines include the value “000”, the process proceeds to step SB04. When the inputs to the monitoring signal lines for one scan of the common signal lines do not include the value “000”, the process proceeds to step SB07.
    • [Step SB04] It is determined whether or not the inputs to the monitoring signal lines for one scan stored in step SB02 correspond to any of the patterns in the table in FIG. 13. When the inputs to the monitoring signal lines for one scan stored in step SB02 correspond to one of the patterns in the table in FIG. 13, the process proceeds to step SB05. When the inputs to the monitoring signal lines for one scan stored in step SB02 correspond to none of the patterns in the table in FIG. 13, the process proceeds to step SB06.
    • [Step SB05] It is determined that a ground fault or disconnection has occurred on the corresponding common signal line in the table in FIG. 13.
    • [Step SB06] It is determined that a fault other than a ground fault, a short circuit, and disconnection has occurred.
    • [Step SB07] It is determined whether or not the inputs to the monitoring signal lines for one scan stored in step SB02 are the same at certain locations on the monitoring signal lines. When the inputs to the monitoring signal lines for one scan stored in step S302 are the same at certain locations on the monitoring signal lines, the process proceeds to step SB08. When the inputs to the monitoring signal lines for one scan stored in step SB02 are not the same at any locations on the monitoring signal lines, the process proceeds to step SB11.
    • [Step SB08] It is determined whether or not the inputs to the monitoring signal lines for one scan stored in step SB02 correspond to any of the patterns in the table in FIG. 14. When the inputs to the monitoring signal lines for one scan stored in step SB02 correspond to one of the patterns in the table in FIG. 14, the process proceeds to step SB09. When the inputs to the monitoring signal lines for one scan stored in step SB02 correspond to none of the patterns in the table in FIG. 14, the process proceeds to step SB10.
    • [Step SB09] It is determined that a short circuit has occurred on the corresponding common signal line in the table in FIG. 14.
    • [Step SB10] It is determined that a fault other than a ground fault, a short circuit, and disconnection has occurred.
    • [Step SB11] It is determined that a fault other than a ground fault, a short circuit, and disconnection has occurred.

The embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, but may be implemented in other aspects by making appropriate changes to the embodiments.

Read more
PatSnap Solutions

Great research starts with great data.

Use the most comprehensive innovation intelligence platform to maximise ROI on research.

Learn More

Patent Valuation

$

Reveal the value <>

31.82/100 Score

Market Attractiveness

It shows from an IP point of view how many competitors are active and innovations are made in the different technical fields of the company. On a company level, the market attractiveness is often also an indicator of how diversified a company is. Here we look into the commercial relevance of the market.

65.0/100 Score

Market Coverage

It shows the sizes of the market that is covered with the IP and in how many countries the IP guarantees protection. It reflects a market size that is potentially addressable with the invented technology/formulation with a legal protection which also includes a freedom to operate. Here we look into the size of the impacted market.

68.36/100 Score

Technology Quality

It shows the degree of innovation that can be derived from a company’s IP. Here we look into ease of detection, ability to design around and significance of the patented feature to the product/service.

51.0/100 Score

Assignee Score

It takes the R&D behavior of the company itself into account that results in IP. During the invention phase, larger companies are considered to assign a higher R&D budget on a certain technology field, these companies have a better influence on their market, on what is marketable and what might lead to a standard.

15.99/100 Score

Legal Score

It shows the legal strength of IP in terms of its degree of protecting effect. Here we look into claim scope, claim breadth, claim quality, stability and priority.

Citation

Patents Cited in This Cited by
Title Current Assignee Application Date Publication Date
Self-diagnosis circuit for conductive pattern BROTHER IND LTD 17 April 1987 28 October 1988
Fault cutting-off system FUJITSU LTD 29 August 1985 04 March 1987
Key entry device TOSHIBA HEATING APPLIANCES CO 07 November 1989 26 June 1991
表示装置及び検査方法 ソニー株式会社 31 May 2004 15 December 2005
Light emitting display panel and method for inspecting the light emitting display panel TOHOKU PIONEER CORPORATION 08 February 2006 17 August 2006
See full citation <>

More like this

Title Current Assignee Application Date Publication Date
Self-testing ground fault circuit interrupter COOPER TECHNOLOGIES COMPANY 24 August 2015 21 April 2016
Ground fault point locating system, control method for ground fault point locating device, and program THE CHUGOKU ELECTRIC POWER CO., INC. 15 February 2016 24 August 2017
Fault detection and direction determination S&C ELECTRIC COMPANY 01 December 2015 09 September 2016
Apparatus and method for ground fault detection OTIS ELEVATOR COMPANY,HERKEL, PETER 10 September 2015 16 March 2017
DETECTING GROUND ISOLATION FAULT IN ETHERNET PoDL SYSTEM LINEAR TECHNOLOGY CORPORATION 19 November 2015 26 May 2016
Circuit and method for detecting arc faults GE AVIATION SYSTEMS LIMITED 20 January 2017 03 August 2017
Method, system and apparatus for fault detection in line protection for power transmission system ABB SCHWEIZ AG,LIU, KAI,LI, YOUYI,WANG, JIANPING 14 April 2016 19 October 2017
Predictive control-based open-circuit fault diagnosis method for matrix converter switch CENTRAL SOUTH UNIVERSITY 14 November 2016 06 July 2017
Phase selection for traveling wave fault detection systems SCHWEITZER ENGINEERING LABORATORIES, INC. 13 June 2017 21 December 2017
Method and system for locating ground faults in a network of drives GENERAL ELECTRIC COMPANY 05 October 2015 13 April 2017
Ground fault point locating system and measurement device THE CHUGOKU ELECTRIC POWER CO., INC. 15 February 2016 24 August 2017
Ground fault detection device, method for controlling same, and control program OMRON CORPORATION 09 March 2017 12 October 2017
Delay circuit for circuit interrupting device HUBBELL INCORPORATED 18 December 2015 22 June 2017
Liquid crystal display panel, and gate driving circuit and fault detection method therefor SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. 05 January 2015 07 July 2016
Apparatus for determination of a ground fault and associated method GENERAL ELECTRIC TECHNOLOGY GMBH 14 February 2017 24 August 2017
Display panel having touch function and fault detection method SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. 05 January 2015 07 July 2016
Apparatuses and methods for passive fault monitoring of current sensing devices in protective circuit interrupters HUBBELL INCORPORATED 19 November 2015 02 June 2016
Ground fault circuit interrupter containing a dual-function test button HUANG HUADAO 06 December 2006 30 October 2007
Automated ground fault interrupt tester COOPER TECHNOLOGIES COMPANY 23 September 2016 06 April 2017
See all similar patents <>

More Patents & Intellectual Property

PatSnap Solutions

PatSnap solutions are used by R&D teams, legal and IP professionals, those in business intelligence and strategic planning roles and by research staff at academic institutions globally.

PatSnap Solutions
Search & Analyze
The widest range of IP search tools makes getting the right answers and asking the right questions easier than ever. One click analysis extracts meaningful information on competitors and technology trends from IP data.
Business Intelligence
Gain powerful insights into future technology changes, market shifts and competitor strategies.
Workflow
Manage IP-related processes across multiple teams and departments with integrated collaboration and workflow tools.
Contact Sales
Clsoe
US10002060 Matrix circuit detecting failure location 1 US10002060 Matrix circuit detecting failure location 2 US10002060 Matrix circuit detecting failure location 3