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Patent Analysis of

Method of designing layout of semiconductor device

Updated Time 12 June 2019

Patent Registration Data

Publication Number

US10002223

Application Number

US15/711390

Application Date

21 September 2017

Publication Date

19 June 2018

Current Assignee

SAMSUNG ELECTRONICS CO., LTD.

Original Assignee (Applicant)

SAMSUNG ELECTRONICS CO., LTD.

International Classification

G06F17/50

Cooperative Classification

G06F17/5072,G06F17/5068

Inventor

JEONG, KWANGOK

Patent Images

This patent contains figures and images illustrating the invention and its embodiment.

US10002223 Method designing layout 1 US10002223 Method designing layout 2 US10002223 Method designing layout 3
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Abstract

A method of designing a layout of a semiconductor device includes receiving information on a size of a target chip and a unit placement width for forming a gate line through a self-align double patterning process by a layout design system. The method also includes allocating an input and output area, a hard macro area, and a standard cell area at the target chip, and adjusting a width of the standard cell area by applying a gate generation rule for setting a width of at least one cell row located in the standard cell area to an odd number multiple of the unit placement width. The unit placement width corresponds to a width between centers of a pair of gate lines in the self-align double patterning process.

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Claims

1. A method of manufacturing a semiconductor device through a self-align double patterning (SADP) process, the method comprising: receiving information on a width of a gate line of a target chip and geometric information on an interval between paired gate lines; allocating an input and output area, in which an input and output pad is formed, at least one hard macro area, and a standard cell area at the target chip; checking a gate generation rule for detecting whether a row-directional width of each cell row of the standard cell area is an odd number multiple of the interval between the paired gate lines; adjusting the row-directional width of each cell row of the standard cell area, which violates the gate generation rule, to an odd number multiple of the interval between the paired gate lines based on a result of the detecting; and forming a set of gate lines according to the SADP process in the standard cell area having adjusted-width cell rows, such that adjacent gate lines of the set of gate lines are spaced apart from respective centers thereof by a unit placement width, the set of gate lines extends across an entirety of the standard cell area, and a quantity of gate lines, of the set of gate lines, in the standard cell area is an even number multiple of gate lines.

2. The method of claim 1, wherein the row-directional width of each cell row of the standard cell area violating the gate generation rule is adjusted based on changing a size of a halo of a hard macro area adjacent thereto.

3. The method of claim 1, wherein the row-directional width of each cell row of the standard cell area violating the gate generation rule is adjusted by moving positions of end cells at both sides of the standard cell area.

4. The method of claim 1, wherein the gate generation rule sets a row-directional width of a hard macro, closed by the standard cell area, from among the at least one hard macro area to an even number multiple of an interval between the paired gate lines and a row-directional width of another hard macro, of which at least one face is not adjacent to the standard cell area and which not adjacent to the standard cell area, to an odd number multiple of the interval between the paired gate lines.

5. The method of claim 4, further comprising: adjusting a row-directional width of a hard macro area which violates the gate generation rule.

6. The method of claim 1, further comprising: forming the paired gate lines through a SADP process.

7. The method of claim 6, wherein the interval between the paired gate lines corresponds to a width between centers of the gate lines constituting the paired gate lines.

8. The method of claim 1, wherein the width of the standard cell area is adjusted by a unit of at least one cell row.

9. A method of manufacturing a layout of a semiconductor device to which a SADP process is applied, the method comprising: allocating at least one hard macro area and a standard cell area at a chip; and adjusting a width of each cell row of the standard cell area so as to be set to an odd number multiple of a unit placement width in which a pair of gate lines are formed; and forming a set of gate lines according to the SADP process in the standard cell area having adjusted-width cell rows, such that adjacent gate lines of the set of gate lines are spaced apart from respective centers thereof by the unit placement width, the set of gate lines extends across an entirety of the standard cell area, and a quantity of gate lines, of the set of gate lines, in the standard cell area is an even number multiple of gate lines.

10. The method of claim 9, wherein the unit placement width corresponds to a width in which the pair of gate lines is formed.

11. The method of claim 9, wherein the unit placement width corresponds to a distance between respective centers of the pair of gate lines.

12. The method of claim 10, wherein the adjusting of the width comprises: moving a position of an end cell formed in a cell row of the standard cell area.

13. The method of claim 10, wherein the adjusting of the width comprises: adjusting a size of a halo of the hard macro area.

14. The method of claim 10, further comprising: adjusting a row-directional width of a hard macro area which violates a gate generation rule.

15. A computer-based system for designing a layout of a semiconductor device, the system comprising: an input/output device configured to receive a size of a target chip and a unit placement width for forming a gate line through a self-align double patterning (SADP) process; a working memory configured to load a gate generation module; a central processing unit configured to execute the gate generation module depending on information provided from the input/output device,wherein the central processing unit executes the gate generation module to form a set of gate lines according to the SADP process in a standard cell area having cell rows, the cell rows each having a common particular width determined based on the unit placement width, such that all adjacent gate lines of the set of gate lines are spaced apart from respective centers thereof by the unit placement width, the set of gate lines extends across an entirety of the standard cell area, and a quantity of gate lines, of the set of gate lines, in the standard cell area is an even number multiple of gate lines.

16. The computer-based system of claim 15, wherein the gate generation module sets a width of a hard macro located in a first area of a hard macro area to an even number multiple of the unit placement width and a width of another hard macro located in a second area thereof to an odd number multiple of the unit placement width.

17. The computer-based system of claim 16, wherein the first area corresponds to a chip area of a rectangular shape of which at least one face is not adjacent to the standard cell area.

18. The computer-based system of claim 16, wherein the second area corresponds to a chip area of a rectangular shape of which four faces are adjacent to the standard cell area.

19. The computer-based system of claim 15, wherein the gate generation module moves positions of gate lines of the standard cell area to a left side or a right side to adjust a width of the standard cell area to an odd number multiple of the unit placement width.

20. The computer-based system of claim 15, wherein the gate generation module adjusts a width of the standard cell area by changing a size of a halo of a hard macro.

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Claim Tree

  • 1
    1. A method of manufacturing a semiconductor device through a self-align double patterning (SADP) process, the method comprising:
    • receiving information on a width of a gate line of a target chip and geometric information on an interval between paired gate lines
    • allocating an input and output area, in which an input and output pad is formed, at least one hard macro area, and a standard cell area at the target chip
    • checking a gate generation rule for detecting whether a row-directional width of each cell row of the standard cell area is an odd number multiple of the interval between the paired gate lines
    • adjusting the row-directional width of each cell row of the standard cell area, which violates the gate generation rule, to an odd number multiple of the interval between the paired gate lines based on a result of the detecting
    • and forming a set of gate lines according to the SADP process in the standard cell area having adjusted-width cell rows, such that adjacent gate lines of the set of gate lines are spaced apart from respective centers thereof by a unit placement width, the set of gate lines extends across an entirety of the standard cell area, and a quantity of gate lines, of the set of gate lines, in the standard cell area is an even number multiple of gate lines.
    • 2. The method of claim 1, wherein
      • the row-directional width of each cell row of the standard cell area violating the gate generation rule is adjusted based on changing a size of a halo of a hard macro area adjacent thereto.
    • 3. The method of claim 1, wherein
      • the row-directional width of each cell row of the standard cell area violating the gate generation rule is adjusted by moving positions of end cells at both sides of the standard cell area.
    • 4. The method of claim 1, wherein
      • the gate generation rule sets a row-directional width of a hard macro, closed by the standard cell area, from among the at least one hard macro area to an even number multiple of an interval between the paired gate lines and a row-directional width of another hard macro, of which at least one face is not adjacent to the standard cell area and which not adjacent to the standard cell area, to an odd number multiple of the interval between the paired gate lines.
    • 6. The method of claim 1, further comprising:
      • forming the paired gate lines through a SADP process.
    • 8. The method of claim 1, wherein
      • the width of the standard cell area is adjusted by a unit of at least one cell row.
  • 9
    9. A method of manufacturing a layout of a semiconductor device to which a SADP process is applied, the method comprising:
    • allocating at least one hard macro area and a standard cell area at a chip
    • and adjusting a width of each cell row of the standard cell area so as to be set to an odd number multiple of a unit placement width in which a pair of gate lines are formed
    • and forming a set of gate lines according to the SADP process in the standard cell area having adjusted-width cell rows, such that adjacent gate lines of the set of gate lines are spaced apart from respective centers thereof by the unit placement width, the set of gate lines extends across an entirety of the standard cell area, and a quantity of gate lines, of the set of gate lines, in the standard cell area is an even number multiple of gate lines.
    • 10. The method of claim 9, wherein
      • the unit placement width corresponds to a width in which
    • 11. The method of claim 9, wherein
      • the unit placement width corresponds to a distance between respective centers of the pair of gate lines.
  • 15
    15. A computer-based system for designing a layout of a semiconductor device, the system comprising:
    • an input/output device configured to receive a size of a target chip and a unit placement width for forming a gate line through a self-align double patterning (SADP) process
    • a working memory configured to load a gate generation module
    • a central processing unit configured to execute the gate generation module depending on information provided from the input/output device,wherein the central processing unit executes the gate generation module to form a set of gate lines according to the SADP process in a standard cell area having cell rows, the cell rows each having a common particular width determined based on the unit placement width, such that all adjacent gate lines of the set of gate lines are spaced apart from respective centers thereof by the unit placement width, the set of gate lines extends across an entirety of the standard cell area, and a quantity of gate lines, of the set of gate lines, in the standard cell area is an even number multiple of gate lines.
    • 16. The computer-based system of claim 15, wherein
      • the gate generation module sets a width of a hard macro located in a first area of a hard macro area to an even number multiple of the unit placement width and a width of another hard macro located in a second area thereof to an odd number multiple of the unit placement width.
    • 19. The computer-based system of claim 15, wherein
      • the gate generation module moves positions of gate lines of the standard cell area to a left side or a right side to adjust a width of the standard cell area to an odd number multiple of the unit placement width.
    • 20. The computer-based system of claim 15, wherein
      • the gate generation module adjusts a width of the standard cell area by changing a size of a halo of a hard macro.
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Description

BACKGROUND

Example embodiments of the inventive concepts described herein relate to a semiconductor device, and more particularly, relate to a method of designing a layout of a semiconductor device.

Usage of mobile devices such as a smart-phone, a tablet personal computer (PC), a digital camera, a MP3 player, and a personal digital assistant (PDA) is significantly increasing. As driving of multimedia and throughput of various data increase in this mobile device, a high-speed processor is largely applied to the mobile device. Various application programs may be driven on a mobile device. To drive various application programs, semiconductor devices such as a working memory (e.g., DRAM), a nonvolatile memory, and an application processor (AP) are used in the mobile device.

Lithography equipment may be quickly developed as compared with a scaled-down version of a design rule. Accordingly, example embodiments of methods of implementing a smaller pitch than a minimum and/or desired pitch implemented using lithography equipment are being studied. In at least one example embodiment, the method includes a self-align double patterning (hereafter referred to as “SADP”) process. A structure of a smaller pitch than a minimum and/or desired pitch implemented using the lithography equipment may be formed using the SADP process. Accordingly, a semiconductor device having a fine pattern or a high degree of integration over a limitation of the lithography equipment may be easily formed using the SADP process.

When a layout design for the SADP is performed, constraint conditions based on a characteristic of the SADP is observed. Example embodiments of the inventive concepts may provide design and verification methods for easily implementing a layout of the semiconductor device manufactured using a SADP process.

SUMMARY

In at least one example embodiment of the inventive concepts, a method of forming a design capable of meeting constraint conditions of a layout design is based on a double patterning process of a semiconductor device and a layout design system.

In at least one example embodiment of the inventive concepts, a method of designing a layout of a semiconductor device includes receiving information on a size of a target chip and a unit placement width for forming a gate line through a SADP process by a layout design system, allocating an input and output area, a hard macro area, and a standard cell area at the target chip, and adjusting a width of the standard cell area by applying a gate generation rule for setting a width of at least one cell row located in the standard cell area to an odd number multiple of the unit placement width. The unit placement width corresponds to a width between centers of a pair of gate lines in the SADP process.

In accordance with another example embodiment of the inventive concepts, a method of designing a layout of a semiconductor device to which a SADP process is applied includes receiving a size of a chip and a design rule, allocating at least one hard macro area and a standard cell area at the chip, and adjusting a width of each cell row of the standard cell area so as to be set to an odd number multiple of a unit placement width in which a pair of gate lines are formed.

In accordance with still another example embodiment of the inventive concepts, a computer based system for designing a layout of a semiconductor device includes an input and output device for receiving geometric information of the semiconductor device or a design rule, a working memory configured to load a gate generation module for generating a gate line to be formed according to a SADP process and a placement and interconnection tool configured to generate a layout of the semiconductor device, and a central processing unit configured to execute the placement and interconnection tool and the gate generation module based on information provided from the input and output device, wherein the gate generation module sets a width of each cell row of a standard cell area allocated to the semiconductor device with an odd number multiple of a unit placement width.

In another example embodiment of the inventive concepts, a method of designing a placement and an interconnection of a semiconductor device includes receiving information on a width of a gate line of a target chip and geometric information on an interval between paired gate lines, allocating an input and output area in which an input and output pad is formed, at least one hard macro area and a standard cell area at the target chip, checking a gate generation rule for detecting whether a row-directional width of each cell row of the standard cell area is an odd number multiple of an interval between the paired gate lines, and adjusting the row-directional width of each cell row of the standard cell area, which violates the gate generation rule, to an odd number multiple of the interval between the paired gate lines based on the detection results.

A method of designing a layout and a layout design system according to at least one example embodiment of the inventive concepts may solve constraint conditions of a pattern generation rule due to a double patterning process.

In at least one example embodiment, a method of designing a placement and an interconnection of a semiconductor device is provided. The method includes receiving information on a width of a gate line of a target chip, allocating an input and output area in which an input and output pad is formed and a standard cell area of the target chip, checking a gate generation rule for detecting whether a row-directional width of each cell row of the standard cell area is an odd number multiple of an interval between paired gate lines, and adjusting the row-directional width of each cell row of the standard cell area, which violates the gate generation rule.

In at least one example embodiment, the adjusting operation includes adjusting the row-directional width of each cell row violating the gate rule to an odd number multiple of the interval between the paired gate lines based on the detection results. The row-directional width of each cell row of the standard cell area violating the gate generation rule may be adjusted by changing a size of a halo of a hard macro area adjacent thereto. In at least one example embodiment, the row-directional width of each cell row of the standard cell area violating the gate generation rule may be adjusted by moving positions of end cells at both sides of the standard cell area. The method may also include adjusting the row-directional width of a hard macro area which violates the gate generation rule, and forming the paired gate lines through a SADP process.

BRIEF DESCRIPTION OF THE FIGURES

The various features and advantages of the non-limiting embodiments herein may become more apparent upon review of the detailed description in conjunction with the accompanying drawings. The accompanying drawings are merely provided for illustrative purposes and should not be interpreted to limit the scope of the claims. The accompanying drawings are not to be considered as drawn to scale unless explicitly noted. For purposes of clarity, various dimensions of the drawings may have been exaggerated.

FIG. 1 is a block diagram illustrating a layout design system according to at least one example embodiment of the inventive concepts.

FIGS. 2A to 2E are diagrams schematically illustrating a SADP process.

FIGS. 3A and 3B are diagrams schematically illustrating the number of gate line patterns formed when the SADP process is applied according to at least one example embodiment.

FIGS. 4A and 4B are diagrams schematically illustrating a width of a placement site on a specific chip area, according to a gate generation rule of at least one example embodiment of the inventive concepts.

FIG. 5 is a flow chart illustrating a layout design method of a layout design system of at least one example embodiment of the inventive concepts.

FIGS. 6 and 7 are chip plan views illustrating operations described in FIG. 5.

FIG. 8 is a diagram schematically illustrating a standard cell area of FIG. 7.

FIG. 9 is a diagram schematically illustrating a standard cell area of FIG. 7.

FIG. 10 is a diagram schematically illustrating a standard cell area of FIG. 7.

FIG. 11 is a diagram illustrating a method of adjusting the number of gates in a standard cell area according to another example embodiment of the inventive concepts.

DETAILED DESCRIPTION

It should be understood that when an element or layer is referred to as being “on,”“connected to,”“coupled to,” or “covering” another element or layer, it may be directly on, connected to, coupled to, or covering the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,”“directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numbers refer to like elements throughout the specification. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It should be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers, and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Thus, a first element, component, region, layer, or section discussed below could be termed a second element, component, region, layer, or section without departing from the teachings of example embodiments.

Spatially relative terms (e.g., “beneath,”“below,”“lower,”“above,”“upper,” and the like) may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” may encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing various embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,”“an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “includes,”“including,”“comprises,” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, including those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Although corresponding plan views and/or perspective views of some cross-sectional view(s) may not be shown, the cross-sectional view(s) of device structures illustrated herein provide support for a plurality of device structures that extend along two different directions as would be illustrated in a plan view, and/or in three different directions as would be illustrated in a perspective view. The two different directions may or may not be orthogonal to each other. The three different directions may include a third direction that may be orthogonal to the two different directions. The plurality of device structures may be integrated in a same electronic device. For example, when a device structure (e.g., a memory cell structure or a transistor structure) is illustrated in a cross-sectional view, an electronic device may include a plurality of the device structures (e.g., memory cell structures or transistor structures), as would be illustrated by a plan view of the electronic device. The plurality of device structures may be arranged in an array and/or in a two-dimensional pattern.

FIG. 1 is a block diagram illustrating a layout design system 100 according to at least one example embodiment of the inventive concepts. Referring to FIG. 1, a layout design system 100 may include a central processing unit (CPU) 110, a working memory 130, an input and output device 150, a storage device 170, and a system bus 190. In at least one example embodiment, the layout design system 100 may be provided as an exclusive device for designing a layout of a semiconductor device. The layout design system 100 may be a computer for operating various simulation tools or design tools.

The CPU 110 may execute software (e.g., an application program, an operating system (OS), and device drivers) to be performed in the layout design system 100. The CPU 110 may perform an operating system (OS) (not illustrated) loaded onto the working memory 130. The CPU 110 may perform various application programs or design and verification tools which are based on the OS. For example, the CPU 110 may execute layout design tools, layout verification tools or design rule checker (DRC) tools which are loaded onto the working memory 130. The CPU 110 may drive a gate generation module 132 provided as a layout design tool in at least one example embodiment of the inventive concepts. The gate generation module 132 may be configured such that an even-number of gates are formed in the SADP process regardless of their locations or environment in the whole chip. This gate placement or generation rule is referred to as an even gate rule. Moreover, the CPU 110 may drive a placement and routing (P&R) tool 134 for placing and routing various hard macros or cells at an optimal position in a chip.

An OS or application program may be loaded onto the working memory 130. During booting of the layout design system 100, an OS image (not illustrated) stored in the storage device 170 may be loaded to the working memory based on a booting sequence. An overall input and output operation of the layout design system 100 may be supported by the OS. Likewise, application programs which are selected by a user or to provide a basic service may be loaded to the working memory 130. The gate generation module 132 and the P&R tool 134 may be loaded to the working memory 130.

The gate generation module 132 or the P&R tool 134 may be loaded from the storage device 170 to the working memory 130 as a layout design tool. Although not illustrated, the working memory 130 may further include tools for designing and verifying a schematic circuit or layout design tools for automatically changing a schematic circuit into a layout. The working memory 130 may be a volatile memory such as a static random access memory (SRAM) or a dynamic random access memory (DRAM) or a nonvolatile memory such as a phase-change random access memory (PRAM), a magnetic random access memory (MRAM), a resistive random access memory (ReRAM), a ferroelectrics random access memory (FRAM), and a NOR flash memory.

The gate generation module 132 may provide the gate placement rule in which an even number of gates are formed in the SADP process regardless of conditions. For example, the gate generation module 132 may apply an even number gate rule such that an even number of gates are formed in the SADP process to form standard cells regardless of their positions or environment in a chip. Gates generated through the SADP process may be formed with an even number to prevent and/or mitigate an increase in a cost due to an additional correction process. Accordingly, the gate generation module 132 may adjust a placement or an array of gates such that an even number of gates are formed in an area of standard cells regardless of any position or condition. The P&R tool 134 may use a netlist provided for a layout design or place an area of a hard macro or a standard cell at a position determined by a user.

The input and output device 150 may control a user input and a user output through user interface devices. For example, the input and output device 150 may include an input device such as a keyboard, a mouse, and a touch pad and an output device such as a monitor that receives a layout when the schematic verification is completed. The input and output device 150 may display a layout design procedure or simulation and verification results of the layout design system 100.

The storage device 170 may be provided as a storage medium of the layout design system 100. The storage device 170 may store an application program, an OS image, and various kinds of data. The storage device 170 may be provided as a memory card (e.g., a multimedia card (MMC), an embedded multimedia card (eMMC), a secure card (SD), a micro secure card (MicroSD)) or a hard disk drive (HDD). The storage device 170 may include a NAND Flash memory having a mass storage capacity. Also, the storage device 170 may include next-generation nonvolatile memories such as a PRAM, a MRAM, a ReRAM, a FRAM or a NOR flash memory.

The system bus 190 may be provided as an interconnector for providing a network in the layout design system 100. The CPU 110, the working memory 130, the input and output device 150, and the storage device 170 may be electrically connected through the system bus 190 to exchange data. However, the scope and spirit of the inventive concepts may not be limited thereto. For example, arbitration means may be further provided for effective management.

According to at least one example embodiment, the layout design system 100 may design a layout of a chip based on information about various gate levels provided for a layout design. The layout design system 100 may apply an even number gate rule allowing an even number of gates to be formed in the SADP process regardless of an environment condition or a position of a standard cell area, thereby making it possible to reduce errors and additional costs which occur in designing a layout of a semiconductor device to be manufactured in the SADP process based on the even number gate rule.

FIGS. 2A to 2E are diagrams schematically illustrating a SADP process. Referring to FIGS. 2A to 2E, an even number of patterns may be formed once a pattern is formed based on the SADP process.

Referring to FIG. 2A, a poly-silicon layer 220 for a gate electrode may be formed on a substrate 210, and a first pattern 232 and a second pattern 234 to be used as a mandrel may be formed on the poly-silicon layer 220. The first pattern 232 and the second pattern 234 may be formed through a lithography process.

Referring to FIG. 2B, a spacer layer 240 may be formed on the first pattern 232 and the second pattern 234. The spacer layer 240 may be formed of a material having an etch selectivity with respect to the first pattern 232 and the second pattern 234. The spacer layer 240 may be formed using a silicon oxide such as a middle-temperature oxide (MTO), a high-temperature oxide (HTO), or an atomic layer deposition (ALD) oxide.

Referring to FIG. 2C, a portion of the spacer layer 240 may be removed, and thus spacers 242, 244, 246, and 248 may be formed on sidewalls of the first pattern 232 and the second pattern 234. For example, a process for removing a portion of the spacer layer 240 may include an etch-back process. The spacers 242, 244, 246, and 248 may be formed on the sidewalls of the first pattern 232 and the second pattern 234 by performing the etch-back process on the spacer layer 240.

Referring to FIG. 2D, a shape in which the first pattern 232, the second pattern 234, and a portion of the poly-silicon layer 220 being an etch target layer are removed may be illustrated. The spacer layer 240 may be a material having an etch selectivity with respect to the first pattern 232 and the second pattern 234, and thus, the first and second patterns 232 and 234 may be removed using an etchant that etches the first and second patterns 232 and 234 but hardly etches the spacers 242, 244, 246, and 248. Moreover, the poly-silicon layer 220 may also be etched to form poly-silicon patterns 222, 224, 226, and 228 under the spacers 242, 244, 246, and 248.

Referring to FIG. 2E, when the spacers 242, 244, 246, and 248 are removed, the poly-silicon patterns 222, 224, 226, and 228 to be used as gates may remain. As described above, two gates 222 and 224 may be formed by means of the first pattern 232 and two gates 226 and 228 may be formed by means of the second pattern 234. A distance W between centers of the gates 222 and 224 formed by means of the first pattern 232 may be referred to as a unit placement width. In short, two gates may be formed by means of one mandrel pattern.

According to at least one example embodiment of the SADP process described above, an even number of gates may be formed. In accordance with a gate generation method of at least one example embodiment of the inventive concepts, when conditions with respect to a specific chip are provided, a placement rule may be applied such that the even number of gate lines may be formed in the standard cell area.

FIGS. 3A and 3B are diagrams schematically illustrating the number of gate line patterns formed when the SADP process is applied according to at least one example embodiment. FIG. 3A illustrates a structure of a placement site PS determined by one mandrel pattern. FIG. 3B illustrates gate line patterns G1 to G6 of PSs PS1 to PS5 determined by three mandrel patterns.

Referring to FIG. 3A, two gates GA and GB may be formed in one placement site PS. A gate width d of each of the two gates GA and GB and a unit placement width W may be formed as illustrated. When one unit placement width W is defined, two gate lines may be generated in a layout design operation. One unit placement width W may correspond to a distance between centers of gates GA and GB. That is, two gates may be allocated in one unit placement width W. For example, three gate lines may be generated in a placement width 2 W to keep a distance of the unit placement width W.

Referring to FIG. 3B, six gates G1 to G6 may be formed in a plurality of placement sites PS1 to PS5. A gate width d and a unit placement width W of each of the six gates G1 to G6 may be formed as illustrated in FIG. 3A. That is, the six gates G1 to G6 may be generated in a placement width 5 W allocated in a standard cell area. Finally, in the standard cell area, (n+1) gates formed to have an interval of the unit placement width W may be disposed within a width nW (i.e., n is a natural number) of total placement sites. However, when the width nW of a placement site is not properly limited in a standard cell area, an odd number of gates may be generated. That is, constraint conditions on the width nW of a placement site of a standard cell area may be required to generate an even number of gates. The width nW of a placement site of a standard cell area may be adjusted in determining the width nW of a placement site of a standard cell area to define a size of this placement site such that an even number of gates are formed.

FIGS. 4A and 4B are diagrams schematically illustrating a width of a placement site PS on a specific chip area determined according to a gate generation rule according to at least one example embodiment of the inventive concepts.

Referring to FIG. 4A, a placement site width on each of a hard macro area and standard cell areas may be defined. Here, “w” denotes a unit placement width.

Above all, a placement site width W1 of each of cell rows CR0, CR1, and CR2 which share the same gates may be defined as (2n2−1)w. Here, n2 is a natural number. That is, a placement site width W1, in which an even number of gates are formed, may be set to an odd number multiple of a unit site width w so as to have the same unit placement width w in a standard cell area.

A placement site width W2 of each of standard cell areas formed on a left side of cell rows CR3 to CR5 may be defined as (2n3−1)w. Here, n3 is a natural number. For example, a placement site width W2 for providing an even number of gates at a standard cell area of which the left side is adjacent to an input and output area and the right side is adjacent to a hard macro area may be set to an odd number multiple of the unit site width w.

A placement site width W3 of each standard cell area formed in a center area of the cell lows CR3 to CR5 may be defined as (2n5−1)w. Here, n5 is a natural number. The placement site width W3 for providing an even number of gates at a standard cell area located between hard macros may be set to an odd number multiple of the unit site width w.

A placement site width W4 of each of standard cell areas formed on a right side of cell rows CR3 to CR5 may be defined as (2n7−1)w. Here, n7 is a natural number. The placement site width W4 for providing an even number of gates at a standard cell area, of which the left side is adjacent to a hard macro area and the right side is adjacent to an input and output area, may be set to an odd number multiple of the unit site width w.

A placement site width W5 of each of standard cell areas corresponding to cell rows CR6 to CR9 in which the whole area of a cell row is allocated to a standard cell area may be defined as (2n8−1)w. Here, n8 is a natural number.

A gate generation rule concerning the placement site widths W1, W2, W3, W4, and W5 may provide an even number of gates at a standard cell area. That is, a placement site width Wi (i.e., “i” being a natural number) of a standard cell area allocated to an arbitrary area in a chip may be set to an odd number multiple of the unit site width w.

Moreover, a width of a hard macro may be set to an odd number multiple or an even number multiple of the unit site width w based on its position. For example, a width L1 of a hard macro placed on a left side of cell rows CR0, CR1, and CR2 may be defined as (2n1)w. Here, n1 is a natural number. That is, the width L1 of a hard macro, which is adjacent to an outside of a chip or an input and output area, may be an even number multiple of the unit site width w. A width L2 of a hard macro, which is placed on a right side of cell rows CR0, CR1, and CR2 may be defined as (2n9)w.

However, widths L3 and L4 of hard macros surrounded with standard cell areas may be defined as (2n4−1)w and (2n6−1)w, respectively. That is, a width of a hard macro surrounded with standard cell areas may be set to an odd number multiple of the unit site width w. Whenever this gate generation rule is applied, the number of gates of a standard cell area located around hard macros may be an even number. When a width of a hard macro and a width of a standard cell area satisfy the described conditions, the gate generation rule may be applied all together and a violation may not occur.

FIG. 4B is a layout in which gates are allocated according to a gate generation rule shown in FIG. 4A. Referring to FIG. 4B, when a gate generation rule according to at least one example embodiment of the inventive concepts is applied, the number of gates divided by a hard macro area in a chip area 300b may be an even number. Moreover, the number of gates included in standard cell areas may be an even number.

FIG. 5 is a flow chart illustrating a layout design method of a layout design system, according to an example embodiment of the inventive concepts. Referring to FIG. 5, chip specification information or verification information on a schematic circuit such as a gate-level netlist may be provided.

In operation S110, geometric information or a chip size may be determined. The chip size may be determined based on the number of various standard cells to be formed in a chip for providing various functions determined at a schematic design level, a memory size, and a core block size.

In operation S120, an input and output area in which an input and output circuit and a pad of the chip will be formed may be determined. Moreover, a position of a hard macro or a hard block may be determined in a core area except for an input and output area. For example, a hard macro, in which an analog circuit block, a static random access memory (SRAM), and a CPU are formed, may be formed to be independent of a standard cell area.

In operation S130, a halo may be set in a hard macro. The halo may correspond to an edge area of a hard macro for distinguishing an integrated circuit formed in the hard macro and a standard cell area. A width of a standard cell area may be adjusted by adjusting the size of a halo area.

In operation S140, a layout design system may determine whether a width of a standard cell area violates a gate generation rule. When a width of a standard cell area or a hard macro area satisfies the gate generation rule, the method may end. On the other hand, when a width of a standard cell area or a hard macro area violates a gate generation rule, the method may proceed to operation S150.

In operation S150, a width of a standard cell area may be adjusted. When a width of a standard cell area corresponds to an even number multiple of a unit placement width w, a position of a cell including a start point or an end point of a cell row of a standard cell area may be adjusted. Here, a width of a standard cell area may be adjusted by adjusting a position of a start point or an end point of a standard cell, but the inventive concepts may be not limited hereto. This gate generation rule may be applied in practically displaying various cells in a standard cell area.

FIGS. 6 and 7 are chip plan views illustrating operations described in FIG. 5.

FIG. 6 illustrates a shape in which an input and output (hereinafter referred to as “I/O”) area and a hard macro of a chip 400 are implemented. FIG. 7 illustrates cell rows concerning each of standard cell areas of a chip 400.

Referring to FIG. 6, an I/O area and a hard macro area may be allocated when a size of a chip is determined. For example, a size of an I/O area 410, in which I/O pads for exchanging data or signals with the outside of a chip, I/O buffers, and drivers are formed, may be determined to allocate the I/O area and the hard macro area. Moreover, hard macro areas 420, 430, 440, and 450 in a chip 400 may be determined to allocate the I/O area and the hard macro area. Positions of the hard macro areas 420, 430, 440, and 450 may be determined based on a distance between an I/O pad and each of the hard macro areas 420, 430, 440, and 450, a configuration of a power rail, or a relative distance between other cores and each of the hard macro areas 420, 430, 440, and 450. The remainder may be allocated to a standard cell area 460 when the I/O area 410 and the hard macro areas 420, 430, 440, and 450 are determined.

FIG. 7 is a plan view of a width of a standard cell area. Referring to FIG. 7, a standard cell area may be classified based on three attributes. The standard cell area may be classified into a standard cell area 470 in which hard macro areas 420 and 430 are located on both sides thereof, a standard cell area 480 located between an I/O area 410 and a hard macro area 440, and a standard cell area 490 not overlapped with a hard macro in the I/O area 410.

Above all, a width W1 of the standard cell area 470, in which the hard macro areas 420 and 430 are located at both sides thereof, may correspond to an odd number multiple of a unit placement width w. A size of a width of this cell area may be identically applied to a width W3 of a standard cell area. A width W2 of the standard cell area 480 located between the I/O area 410 and the hard macro area 440 may be also set to an odd number multiple of the unit placement width w. Likewise, a width W4 of a standard cell area may be also set to an odd number multiple of the unit placement width w. This rule may be identically applied to the standard cell area 490.

FIG. 8 is a diagram schematically illustrating a standard cell area 470 of FIG. 7. Referring to FIG. 8, in at least one example embodiment, a standard cell area between hard macros HM1 and HM2 may be formed over three cell rows SCR0, SCR1, and SCR2.

A left end cell FC_L may be located at a left side of the cell row SCR0 of a standard cell area. Moreover, a right end cell FC_R may be placed at a right side of the cell row SCR0. Each of the end cells FC_L and FC_R may protect cells included in a standard cell area between a standard cell area and hard macros. That is, the end cells FC_L and FC_R configured to substantially prevent and/or mitigate various interferences which occur in a manufacture process due to a configuration difference between a core formed in a hard macro and various cells formed in a standard cell area may be placed. A width of the left end cell FC_L may be D1 and a width of the right end cell FC_R may be D2. Here, the widths D1 and D2 of the end cells FC_L and FC_R may be set to be identical to each other or to be different from each other.

According to an example embodiment of the inventive concepts, positions of the end cells FC_L and FC_R may be moved to a left side or a right side to adjust a width W1 of a standard cell area. For example, the width W1 of a standard cell area may be reduced by moving the left end cells FC_L to a right side as much as an interval d1. Moreover, a position of the right end cell FC_R may be moved to set a width W1 of a standard cell area to an odd number multiple of the unit placement width w. A width W1 of a standard cell area may be adjusted to be set to an odd number multiple of the unit placement width w by moving a position of the end cells FC_L and FC_R in a hard macro direction and increasing the width W1 of a standard cell area.

In at least one example embodiment, a configuration of the end cells FC_L and FC_R may be applied to cell rows SCR1 and SCR2, because cell rows SCR0, SCR1 and SCR2 located between hard macros HM1 and HM2 share the same gates.

FIG. 9 is a diagram schematically illustrating a standard cell area 480. Referring to FIG. 9, a standard cell area between an input and output area and a hard macro HM3 may be formed over three cell rows SCR3, SCR4, and SCR5.

A left end cell FC_L may be located on a left side of the cell row SCR3 of a standard cell area. Moreover, a right end cell FC_R may be placed at a right side of the cell row SCR3. Each of the end cells FC_L and FC_R may protect cells included in a standard cell area between a standard cell area and hard macros. That is, the end cells FC_L and FC_R for preventing and/or mitigating various interferences which occur in a manufacture process due to a configuration difference between a core formed in a hard macro and various cells formed in a standard cell area may be placed. A width of the left end cell FC_L may be D1′ and a width of the right end cell FC_R may be D2′. Here, the width D1′ of the left end cells FC_L and the width D2′ of the right end cells FC_R may be set to be equal to widths D1 and D2 of the end cells FC_L and FC_R shown in FIG. 8 or to be different from widths D1 and D2 of the end cells FC_L and FC_R shown in FIG. 8.

According to an example embodiment of the inventive concepts, positions of end cells FC_L and FC_R may be moved to a left side or a right side to adjust a width W2 of a standard cell area. For example, the width W2 of a standard cell area may be reduced by moving the left end cells FC_L to a right side as much as a specific distance. Moreover, a position of the right end cell FC_R may be moved to set a width W2 of a standard cell area to an odd number multiple of the unit placement width w. A width W2 of a standard cell area may be adjusted to be set to an odd number multiple of the unit placement width w by moving a position of the end cells FC_L and FC_R in an arbitrary direction and increasing the width W2 of a standard cell area. A configuration of the end cells FC_L and FC_R may be applied to both cell rows SCR4 and SCR5.

FIG. 10 is a diagram schematically illustrating a standard cell area 490. Referring to FIG. 10, a standard cell area 490 between an input and output areas may be formed over four cell rows SCR6, SCR7, SCR8, and SCR9.

A left end cell FC_L may be located on a left side of the cell row SCR6 of a standard cell area. Moreover, a right end cell FC_R may be placed at a right side of the cell row SCR6. Each of the end cells FC_L and FC_R may protect cells included in a standard cell area between a standard cell area and hard macros. That is, the end cells FC_L and FC_R for preventing various interferences which occur in a manufacture process due to a configuration difference between a core formed in a hard macro and various cells formed in a standard cell area may be placed. A width of the left end cell FC_L may be D1″ and a width of the right end cell FC_R may be D2″. Here, the width D1″ of the left end cells FC_L and the width D2″ of the right end cells FC_R may be set to be equal to widths D1 and D2 of the end cells FC_L and FC_R shown in FIG. 8 or to be different from widths D1 and D2 of the end cells FC_L and FC_R shown in FIG. 8.

According to an example embodiment of the inventive concepts, positions of end cells FC_L and FC_R may be moved to a left side or a right side to adjust a width W0 of a standard cell area. For example, the width W0 of a standard cell area may be reduced by moving the left end cells FC_L to a right side as much as a specific distance. Moreover, a position of the right end cell FC_R may be moved to set a width W0 of a standard cell area to an odd number multiple of the unit placement width w. A width W0 of a standard cell area may be adjusted to be set to an odd number multiple of the unit placement width w by moving a position of the end cells FC_L and FC_R in an arbitrary direction and increasing the width W0 of a standard cell area. A configuration of the end cells FC_L and FC_R may be applied to both cell rows SCR7, SCR8 and SCR9.

FIG. 11 is a diagram illustrating a method of adjusting the number of gates in a standard cell area, according to another example embodiment of the inventive concepts. Referring to FIG. 11, a standard cell area between hard macros HM1 and HM2 may be formed over three cell rows SCR0, SCR1, and SCR2. However, a width of the standard cell area may be determined in placing a plurality of standard cells 471 to 478. That is, a gate generation rule of at least one example embodiment of the inventive concepts may be applied to dispose a plurality of standard cells 471 to 478.

Meanwhile, a memory system according to at least one example embodiment of the inventive concepts may be installed using a package of various shapes. For example, a semiconductor device may be installed using packages such as a package on package (PoP), a ball grid arrays (BGAs), a chip scale packages (CSPs), a plastic leaded chip carrier (PLCC), a plastic dual in-line package (PDIP), a die in waffle pack, a die in wafer form, a chip on board (COB), a ceramic dual in-line package (CERDIP), a plastic metric quad flat pack (MQFP), a thin quad flat pack (TQFP), a small outline integrated circuit (SOIC), a shrink small outline package (SSOP), a thin small outline package (TSOP), a thin quad flat pack (TQFP), a system in package (SIP), a multi chip package (MCP), a wafer-level fabricated package (WFP), and a wafer-level processed stack package (WSP).

While the inventive concepts have been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention. Therefore, it should be understood that the above embodiments are not limiting, but illustrative.

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34.0/100 Score

Market Attractiveness

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84.0/100 Score

Market Coverage

It shows the sizes of the market that is covered with the IP and in how many countries the IP guarantees protection. It reflects a market size that is potentially addressable with the invented technology/formulation with a legal protection which also includes a freedom to operate. Here we look into the size of the impacted market.

73.21/100 Score

Technology Quality

It shows the degree of innovation that can be derived from a company’s IP. Here we look into ease of detection, ability to design around and significance of the patented feature to the product/service.

46.0/100 Score

Assignee Score

It takes the R&D behavior of the company itself into account that results in IP. During the invention phase, larger companies are considered to assign a higher R&D budget on a certain technology field, these companies have a better influence on their market, on what is marketable and what might lead to a standard.

11.61/100 Score

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Citation

Patents Cited in This Cited by
Title Current Assignee Application Date Publication Date
半導体装置、半導体装置のレイアウト装置、及び半導体装置のレイアウト方法 ルネサスエレクトロニクス株式会社 29 March 2011 17 November 2011
画像形成装置 CANON INC 08 November 2001 21 May 2003
半導体集積回路の設計方法および半導体集積回路 TOSHIBA CORP 18 November 2003 09 June 2005
ヒステリシス電圧幅測定用のテスト回路およびそのテスト回路を用いたヒステリシス電圧幅の測定方法 MATSUSHITA ELECTRIC IND CO LTD 06 August 2001 21 February 2003
半導体装置のオープンテスト回路、オープンテスト回路を備えた半導体チップ及び半導体装置 ELPIDA MEMORY INC 13 May 2009 25 November 2010
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