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Patent Analysis of

Gate drive on array unit, gate drive on array circuit and display apparatus

Updated Time 12 June 2019

Patent Registration Data

Publication Number

US10002560

Application Number

US14/388500

Application Date

05 December 2013

Publication Date

19 June 2018

Current Assignee

BOE TECHNOLOGY GROUP CO., LTD.,BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.

Original Assignee (Applicant)

BOE TECHNOLOGY GROUP CO., LTD.,BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.

International Classification

G09G3/36,G06F3/038,G09G3/20,G09G3/3266

Cooperative Classification

G09G3/2096,G09G3/20,G09G3/3266,G09G3/3688,G09G2300/0408

Inventor

ZHENG, YI,WANG, ZHIYONG,ZHANG, ZHENGXIN,YU, YAO,SHI, LINGYUN

Patent Images

This patent contains figures and images illustrating the invention and its embodiment.

US10002560 Gate drive array unit, 1 US10002560 Gate drive array unit, 2 US10002560 Gate drive array unit, 3
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Abstract

A gate drive on array unit, a gate drive on array circuit and a display device are disclosed. The gate drive on array unit including: a control module configured to output a clock signal under control of a gate driving signal of a previous stage of gate drive on array unit or a start input signal; an output module connected to the control module and configured to output a high voltage signal (VGH) as a gate driving signal of the present stage under control of the clock signal outputted from the control module, and output a low voltage signal under the control of the clock signal outputted from the control module; and a reset module connected to the output module, and configured to reset the gate driving signal of the present stage under the control of a gate driving signal of a next stage of gate drive on array unit.

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Claims

1. A gate drive on array unit, comprising: a control module having a first input terminal that receives a gate driving signal of a previous stage of the gate drive on array unit or a start input signal, and a second input terminal that receives a periodic clock signal which has a fixed period, configured to output the periodic clock signal under control of the gate driving signal of the previous stage of the gate drive on array unit or the start input signal received by the first input terminal of the control module; an output module having a first input terminal connected to the control module, a second input terminal connected to a high voltage signal terminal, and a third input terminal connected to a low voltage signal terminal, the output module configured to output a high voltage signal received by the high voltage signal terminal as a gate driving signal of a present stage under control of the periodic clock signal outputted from the control module and output a low voltage signal received by the low voltage signal terminal under the control of the periodic clock signal outputted from the control module; and a reset module connected to the output module and configured to reset the gate driving signal of the present stage under control of a gate driving signal of a next stage of the gate drive on array unit, wherein the control module comprises a first thin film transistor, wherein the output module comprises a second thin film transistor and a third thin film transistor, wherein the reset module comprises a fourth thin film transistor, wherein a gate of the first thin film transistor is connected to an output terminal of the gate driving signal of the previous stage of the gate drive on array unit or the start input signal, a first electrode of the first thin film transistor is connected to a clock signal input terminal, and a second electrode of the first thin film transistor is connected to a gate of the second thin film transistor and a gate of the third thin film transistor, wherein a first electrode of the second thin film transistor is connected to a high level output terminal, and a second electrode of the second thin film transistor is connected to a first electrode of the third thin film transistor and an output terminal of the gate driving signal of the present stage, wherein a second electrode of the third thin film transistor is connected to a low level output terminal and a first electrode of the fourth thin film transistor, wherein a gate of the fourth thin film transistor is connected to an output terminal of the gate driving signal of the next stage of the gate drive on array unit, and a second electrode of the fourth thin film transistor is connected to the output terminal of the gate driving signal of the present stage, wherein the first thin film transistor of a first stage of the gate drive on array unit is a N-type thin film transistor, and except the first stage of the gate drive on array unit, the first thin film transistor of other stages of the gate drive on array unit is a P-type thin film transistor, and wherein the second thin film transistor and the fourth thin film transistor of a first stage of the gate drive on array unit are N-type thin film transistors; and wherein the third thin film transistor thereof is a P-type thin film transistor.

2. The gate drive on array unit according to claim 1, wherein, except the first stage of the gate drive on array unit, the third thin film transistor of odd stages of the gate drive on array unit is a P-type thin film transistor, and the second thin film transistor and the fourth thin film transistor thereof are N-type thin film transistors; and the second thin film transistor of even stages of the gate drive on array unit is a P-type thin film transistors, and the third thin film transistor and the fourth thin film transistor thereof are N-type thin film transistors.

3. A gate drive on array circuit, comprising a plurality of the gate drive on array units according to claim 1, wherein except a first stage of the gate drive on array unit, a signal input terminal of each stage of the gate drive on array unit is connected to an output terminal of the gate driving signal of the previous stage of the gate drive on array unit; and except a last stage of the gate drive on array unit, a reset terminal of each stage of the gate drive on array unit is connected to an output terminal of the gate driving signal of the next stage of the gate drive on array unit.

4. A display apparatus, comprising the gate drive on array circuit according to claim 3.

5. The display apparatus according to claim 4, wherein the second thin film transistor and the fourth thin film transistor of the first stage of the gate drive on array unit are N-type thin film transistors, and the third thin film transistor thereof is a P-type thin film transistor.

6. The display apparatus according to claim 5, wherein, except the first stage of the gate drive on array unit, the third thin film transistor of odd stages of the gate drive on array units is a P-type thin film transistors, and the second thin film transistor and the fourth thin film transistor thereof are N-type thin film transistors; and the second thin film transistor of even stages of the gate drive on array units is a P-type thin film transistors, and the third thin film transistor and the fourth thin film transistor thereof are N-type thin film transistors.

7. The gate drive on array circuit according to claim 3, wherein, except the first stage of the gate drive on array unit, the third thin film transistor of odd stages of the gate drive on array units is a P-type thin film transistors, and the second thin film transistor and the fourth thin film transistor thereof are N-type thin film transistors; and the second thin film transistor of even stages of the gate drive on array units is a P-type thin film transistors, and the third thin film transistor and the fourth thin film transistor thereof are N-type thin film transistors.

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Claim Tree

  • 1
    1. A gate drive on array unit, comprising:
    • a control module having a first input terminal that receives a gate driving signal of a previous stage of the gate drive on array unit or a start input signal, and a second input terminal that receives a periodic clock signal which has a fixed period, configured to output the periodic clock signal under control of the gate driving signal of the previous stage of the gate drive on array unit or the start input signal received by the first input terminal of the control module
    • an output module having a first input terminal connected to the control module, a second input terminal connected to a high voltage signal terminal, and a third input terminal connected to a low voltage signal terminal, the output module configured to output a high voltage signal received by the high voltage signal terminal as a gate driving signal of a present stage under control of the periodic clock signal outputted from the control module and output a low voltage signal received by the low voltage signal terminal under the control of the periodic clock signal outputted from the control module
    • and a reset module connected to the output module and configured to reset the gate driving signal of the present stage under control of a gate driving signal of a next stage of the gate drive on array unit, wherein the control module comprises a first thin film transistor, wherein the output module comprises a second thin film transistor and a third thin film transistor, wherein the reset module comprises a fourth thin film transistor, wherein a gate of the first thin film transistor is connected to an output terminal of the gate driving signal of the previous stage of the gate drive on array unit or the start input signal, a first electrode of the first thin film transistor is connected to a clock signal input terminal, and a second electrode of the first thin film transistor is connected to a gate of the second thin film transistor and a gate of the third thin film transistor, wherein a first electrode of the second thin film transistor is connected to a high level output terminal, and a second electrode of the second thin film transistor is connected to a first electrode of the third thin film transistor and an output terminal of the gate driving signal of the present stage, wherein a second electrode of the third thin film transistor is connected to a low level output terminal and a first electrode of the fourth thin film transistor, wherein a gate of the fourth thin film transistor is connected to an output terminal of the gate driving signal of the next stage of the gate drive on array unit, and a second electrode of the fourth thin film transistor is connected to the output terminal of the gate driving signal of the present stage, wherein the first thin film transistor of a first stage of the gate drive on array unit is a N-type thin film transistor, and except the first stage of the gate drive on array unit, the first thin film transistor of other stages of the gate drive on array unit is a P-type thin film transistor, and wherein the second thin film transistor and the fourth thin film transistor of a first stage of the gate drive on array unit are N-type thin film transistors
    • and wherein the third thin film transistor thereof is a P-type thin film transistor.
    • 2. The gate drive on array unit according to claim 1, wherein
      • , except the first stage of the gate drive on array unit, the third thin film transistor of odd stages of the gate drive on array unit is a P-type thin film transistor, and the second thin film transistor and the fourth thin film transistor thereof are N-type thin film transistors; and the second thin film transistor of even stages of the gate drive on array unit is a P-type thin film transistors, and the third thin film transistor and the fourth thin film transistor thereof are N-type thin film transistors.
  • 3
    3. A gate drive on array circuit, comprising
    • a plurality of the gate drive on array units according to claim 1, wherein except a first stage of the gate drive on array unit, a signal input terminal of each stage of the gate drive on array unit is connected to an output terminal of the gate driving signal of the previous stage of the gate drive on array unit
    • and except a last stage of the gate drive on array unit, a reset terminal of each stage of the gate drive on array unit is connected to an output terminal of the gate driving signal of the next stage of the gate drive on array unit.
    • 7. The gate drive on array circuit according to claim 3, wherein
      • , except the first stage of the gate drive on array unit, the third thin film transistor of odd stages of the gate drive on array units is a P-type thin film transistors, and the second thin film transistor and the fourth thin film transistor thereof are N-type thin film transistors; and the second thin film transistor of even stages of the gate drive on array units is a P-type thin film transistors, and the third thin film transistor and the fourth thin film transistor thereof are N-type thin film transistors.
  • 4
    4. A display apparatus, comprising
    • the gate drive on array circuit according to claim 3.
    • 5. The display apparatus according to claim 4, wherein
      • the second thin film transistor and the fourth thin film transistor of the first stage of the gate drive on array unit are N-type thin film transistors, and the third thin film transistor thereof is a P-type thin film transistor.
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Description

The application is a U.S. National Phase Entry of International Application No. PCT/CN2013/088684, filed on Dec. 5, 2013, designating the United States of America and claiming priority to Chinese Patent Application No. 201310370143.7, filed on Aug. 22, 2013. The present application claims priority to and the benefit of all the above-identified applications and all of the above-identified applications are incorporated by reference herein in their entireties.

FIELD OF THE INVENTION

The present disclosure relates to the field of display technique, and in particular to a gate drive on array (GOA, Gate Drive on Array) unit, a gate drive on array circuit and a display apparatus.

BACKGROUND

GOA technique is a technique that integrates a liquid crystal display gate driving circuit (Gate Driver IC) on an array substrate, having the following advantages: (1) integrating a gate driving circuit on the array substrate enables to effectively reduce production cost and power consumption; (2) saving bonding yield processes enables to upgrade product yield and production capacity; (3) saving gate driving circuit bonding (gate IC bonding) areas enables a display panel to have a symmetrical structure, so as to realize the narrowing of the frame of the display panel.

However, the existing GOA technique adopts a relatively large quantity of thin film transistors (TFT), thereby causing existence of multi-layer overlap in the wiring of the circuit board, so that the following problems may occur: (1) process fluctuation easily leads to a parasitic capacitance coupling change inside the GOA, thereby causing an abnormal output of the gate; (2) due to a great number of crossover points, a relatively large voltage difference exists between the crossover points, which easily causes Electro-Static Discharge (ESD).

SUMMARY

Given that, the present disclosure provides a GOA unit, a GOA circuit and a display device in view of deficiencies existing in the prior art, which are capable of effectively reducing an abnormal output of a gate driving signal due to a multi-layer overlap of wiring and a problem of electro-static discharge due to existence of a relatively large voltage difference between the crossover points.

Technical solutions of the present disclosure can be realized as follows.

An embodiment of the present disclosure provides a gate drive on array unit, comprising: a control module configured to output a clock signal under control of a gate driving signal of a previous stage of gate drive on array unit or a start input signal; an output module connected to the control module and configured to output a high voltage signal as a gate driving signal of a present stage under control of the clock signal outputted from the control module and output a low voltage signal under the control of the clock signal outputted from the control module; and a reset module connected to the output module and configured to reset the gate driving signal of the present stage under control of a gate driving signal of a next stage of gate drive on array unit.

In the above embodiment, the control module comprises a first thin film transistor, the output module comprises a second thin film transistor and a third thin film transistor, and the reset module comprises a fourth thin film transistor, wherein,

a gate of the first thin film transistor is connected to an output terminal of the gate driving signal of the previous stage of gate drive on array unit or the start input signal, a first electrode of the first thin film transistor is connected to a clock signal input terminal, and a second electrode of the first thin film transistor is connected to a gate of the second thin film transistor and a gate of the third thin film transistor respectively;

a first electrode of the second thin film transistor is connected to a high level output terminal, and a second electrode of the second thin film transistor is connected to a second electrode of the third thin film transistor and an output terminal of the gate driving signal of the present stage respectively;

a second electrode of the third thin film transistor is connected to a low level output terminal and a first electrode of the fourth thin film transistor respectively; and

a gate of the fourth thin film transistor is connected to an output terminal of the gate driving signal of the next stage of gate drive on array unit, and a second electrode of the fourth thin film transistor is connected to the output terminal of the gate driving signal of the present stage.

In the above embodiment, the first thin film transistor, the second thin film transistor and the fourth thin film transistor of the first stage of gate drive on array unit are N-type thin film transistors; the third thin film transistor is a P-type thin film transistor.

In the above embodiment, except the first stage of gate drive on array unit, the first thin film transistor and the third thin film transistors of the odd stages of gate drive on array units are P-type thin film transistors, and the second thin film transistor and the fourth thin film transistor thereof are N-type thin film transistors;

the first thin film transistor and the second thin film transistors of the even stages of gate drive on array units are P-type thin film transistors; the third thin film transistor and the fourth thin film transistor thereof are N-type thin film transistors.

An embodiment of the present disclosure further provides an gate drive on array circuit comprising more than one of the gate drive on array units as described above;

except first stage of gate drive on array unit, a signal input terminal of each stage of gate drive on array unit is connected to a gate signal output terminal of a previous stage of gate drive on array unit;

except last stage of gate drive on array unit, a reset terminal of each stage of gate drive on array unit is connected to a gate signal output terminal of a next stage of gate drive on array unit.

An embodiment of the present disclosure further provides a display device comprising the gate drive on array circuit as described in the present disclosure.

The GOA unit, GOA circuit and display device provided in the embodiments of the present disclosure have the following beneficial effects:

The GOA unit adopts four thin film transistors, simplifies the original GOA units, and reduces the wiring of the circuit board, thereby effectively reducing the problem of an abnormal output of the gate driving signal due to the multi-layer overlap of the wiring; in addition, due to the reduction of the crossover points, the problem of electro-static discharge due to existence of a relatively large voltage difference between the crossover points is effectively reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram of a structure of a GOA unit of a first embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a circuit of a GOA unit of a second embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a circuit of a GOA unit of a third embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a circuit of a GOA unit of a fourth embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a circuit of a GOA unit of a fifth embodiment of the present disclosure;

FIG. 6 is a schematic diagram of timing of respective signals when the GOA unit of the fifth embodiment of the present disclosure operates;

FIG. 7 is a schematic diagram of a circuit of a GOA unit of a sixth embodiment of the present disclosure;

FIG. 8 is a schematic diagram of timing of respective signals when the GOA unit of the sixth embodiment of the present disclosure operates.

DETAILED DESCRIPTION

A further detailed specification will be given below in combination with specific embodiments of the present disclosure.

FIG. 1 is a schematic block diagram of a GOA unit of a first embodiment of the present disclosure. As shown in FIG. 1, the GOA unit comprises a control module 11, an output module 12 and a reset module 13.

In the present embodiment, the control module 11 is connected to the output module 12 and configured to output a clock signal CLK to the output module 12 under the control of a gate driving signal of the previous stage of gate drive on array unit or a start input signal.

The output module 12 is configured to output a high voltage signal VGH as a gate driving signal of a present stage under a control of the clock signal, and output a low voltage signal VGL under the control of the clock signal.

The reset module 13 is connected to a gate driving signal of the next stage of gate drive on array unit and an output terminal of a gate driving signal of the present stage respectively, and configured to reset the gate driving signal of the present stage under a control of a gate driving signal of a next stage of gate drive on array unit.

In FIG. 1, the gate driving signal of the previous stage of gate drive on array unit is G(n−1), the gate driving signal of the present stage of gate drive on array unit is G(n), and the gate driving signal of the next stage of gate drive on array signal is G(n+1).

FIG. 2 is a schematic diagram of a circuit of a GOA unit of a second embodiment of the present disclosure. As shown in FIG. 2, the GOA unit provide in the second embodiment is based on the GOA unit provided in the first embodiment, and is a first stage of GOA unit; in the second embodiment, the control module 11 comprises a first thin film transistor M1, the output module 12 comprises a second thin film transistor M2 and a third thin film transistor M3, and the reset module 13 comprises a fourth thin film transistor M4.

In the present embodiment, a gate of the first thin film transistor M1 is connected to a signal input terminal INPUT, a first electrode of the first thin film transistor M1 is connected to the clock signal input terminal CLK, and a second electrode of the first thin film transistor M1 is connected to a gate of the second thin film transistor M2 and a gate of the third thin film transistor M3 respectively.

A first electrode of the second thin film transistor M2 is connected to a high level signal terminal VGH, and a second electrode of the second thin film transistor M2 is connected to a first electrode of the third thin film transistor M3 and an output terminal G(1) of the gate driving signal of the present stage respectively.

A second electrode of the third thin film transistor M3 is connected to a low level signal terminal VGL and a first electrode of the fourth thin film transistor M4 respectively.

A gate of the fourth thin film transistor M4 is connected to a reset terminal RESET, and a second electrode of the fourth thin film transistor M4 is connected to the output terminal G(1) of the gate driving signal of the present stage.

The reset terminal RESET is connected to the output terminal of the gate driving signal of the next stage of array substrate driving unit, that is, the reset terminal RESET of the first stage of gate drive on array unit is connected to G(2).

As an example, the first thin film transistor, the second thin film transistor and the fourth thin film transistor are N-type thin film transistors; the third thin film transistor is a P-type thin film transistor.

The first electrodes and second electrodes of the thin film transistors in the present embodiment can be sources or drains of the thin film transistors.

FIG. 3 is a schematic diagram of a circuit of a GOA unit of the third embodiment of the present disclosure. As shown in FIG. 3, the gate drive on array unit of the third embodiment is based on the GOA unit provided in the first embodiment, and is an even stage of GOA unit. In the third embodiment, the control module 11 comprises the first thin film transistor M1, the output module 12 comprises the second thin film transistor M2 and the third thin film transistor M3, and the reset module 13 comprises the fourth thin film transistor M4.

In the present embodiment, a gate of the first thin film transistor M1 is connected to the output terminal G(n−1) of the gate driving signal of the previous stage of gate drive on array unit, a first electrode of the first thin film transistor M1 is connected to the clock signal input terminal CLK, and a second electrode of the first thin film transistor M1 is connected to a gate of the second thin film transistor M2 and a gate of the third thin film transistor M3.

A first electrode of the second thin film transistor M2 is connected to the high level signal terminal VGH, and a second electrode of the second thin film transistor M2 is connected to a first electrode of the third thin film transistor M3 and an output terminal G(n) of the gate driving signal of the present stage respectively.

A second electrode of the third thin film transistor M3 is connected to the low level signal terminal VGL and a first electrode of the fourth thin film transistor M4 respectively.

A gate of the fourth thin film transistor M4 is connected to the reset terminal RESET, and a second electrode of the fourth thin film transistor M4 is connected to the output terminal G(n) of the gate driving signal of the present stage.

In the present embodiment, the reset terminal RESET is connected to the output terminal of the gate driving signal of the next stage of gate drive on array unit, that is, the reset terminal RESET is connected to G(n+1).

As an example, the first thin film transistor and the second thin film transistor are P-type thin film transistors; the third thin film transistor and the fourth thin film transistor are N-type thin film transistors.

The first electrodes and second electrodes of the thin film transistors in the present embodiment can be sources or drains of the thin film transistors.

FIG. 4 is a schematic diagram of a circuit of a GOA unit of the fourth embodiment of the present disclosure. As shown in FIG. 4, the GOA unit provided in the fourth embodiment is based on the GOA unit provided in the first embodiment, and is an odd stage of GOA unit except the first stage of GOA unit. In the fourth embodiment, the control module 11 comprises the first thin film transistor M1, the output module 12 comprises the second thin film transistor M2 and the third thin film transistor M3, and the reset module 13 comprises the fourth thin film transistor M4.

In the present embodiment, a gate of the first thin film transistor M1 is connected to the output terminal G(n−1) of the gate driving signal the previous stage of gate drive on array unit; a first electrode of the first thin film transistor M1 is connected to the clock signal input terminal CLK, and a second electrode of the first thin film transistor M1 is connected to a gate of the second thin film transistor M2 and a gate of the third thin film transistor M3.

A first electrode of the second thin film transistor M2 is connected to the high level signal terminal VGH, and a second electrode of the second thin film transistor M2 is connected to a first electrode of the third thin film transistor M3 and an output terminal G(n) of the gate driving signal of the present stage respectively.

A second electrode of the third thin film transistor M3 is connected to the low level signal terminal VGL and a first electrode of the fourth thin film transistor M4 respectively.

A gate of the fourth thin film transistor M4 is connected to the reset terminal RESET, and a second electrode of the fourth thin film transistor M4 is connected to the output terminal G(n) of the gate driving signal of the present stage.

The reset terminal RESET is connected to the output terminal of the gate driving signal of the next stage of gate drive on array unit, that is, the reset terminal RESET is connected to G(n+1).

As an example, the first thin film transistor M1 and the third thin film transistor M3 are P-type thin film transistors; the second thin film transistor M2 and the fourth thin film transistor M4 are N-type thin film transistors.

The first electrodes and second electrodes of the thin film transistors in the present embodiment can be sources or drains of the thin film transistors.

FIG. 5 is a schematic diagram of a circuit of a GOA unit of the fifth embodiment of the present disclosure. As shown in FIG. 5, the circuit comprises first and second stages of GOA units. In the fifth embodiment, the first and second stages of GOA units comprise the control module 11, the output module 12 and the reset module 13 respectively. Herein, the control module 11 of the first stage of gate drive on array unit comprises the first thin film transistor M1, the output module 12 thereof comprises the second thin film transistor M2 and the third thin film transistor M3, and the reset module 13 thereof comprises the fourth thin film transistor M4. The control module 11 of the second stage of gate drive on array unit comprises a fifth thin film transistor M5, the output module thereof comprises a sixth thin film transistor M6 and a seventh thin film transistor M7, and the reset module 13 thereof comprises an eighth thin film transistor M8.

In the present embodiment, a gate of the first thin film transistor M1 is connected to the signal input terminal INPUT; a first electrode of the first thin film transistor M1 is connected to the clock signal input terminal CLK, and a second electrode of the first thin film transistor M1 is connected to a gate of the second thin film transistor M2 and a gate of the third thin film transistor M3;

A first electrode of the second thin film transistor M2 is connected to the high level signal terminal VGH, and a second electrode of the second thin film transistor M2 is connected to a first electrode of the third thin film transistor M3 and an output terminal G(1) of the gate driving signal of the present stage respectively.

A second electrode of the third thin film transistor M3 is connected to the low level signal terminal VGL and a first electrode of the fourth thin film transistor M4 respectively.

A gate of the fourth thin film transistor M4 is connected to an output terminal G(2) of a gate driving signal of a second stage, and a second electrode of the fourth thin film transistor M4 is connected to the output terminal G(1) of a gate driving signal of a first stage.

A gate of the fifth thin film transistor M5 is connected to the output terminal G(1) of the gate driving signal of the first stage, a first electrode of the fifth thin film transistor M5 is connected to the clock signal input terminal CLK, and a second electrode of the fifth thin film transistor M5 is connected to a gate of the sixth thin film transistor M6 and a gate of the seventh thin film transistor M7 respectively.

A first electrode of the sixth thin film transistor M6 is connected to the high level signal terminal VGH, and a second electrode of the sixth thin film transistor M6 is connected to a first electrode of the seventh thin film transistor M7 and the output terminal G(2) of the gate driving signal of the second stage respectively.

A second electrode of the seventh thin film transistor M7 is connected to the low level signal terminal VGL and a first electrode of the eighth thin film transistor M8 respectively.

A gate of the eighth thin film transistor M8 is connected to the reset terminal RESET which is connected to an output terminal G(3) of a gate driving signal of a third stage, and a second electrode of the eighth thin film transistor M8 is connected to the output terminal G(2) of the gate driving signal of the second stage.

As an example, the first thin film transistor M1, the second thin film transistor M2, the fourth thin film transistor M4, the seventh thin film transistor M7, and the eighth thin film transistor M8 are N-type thin film transistors; the third thin film transistor M3, the fifth thin film transistor M5, and the sixth thin film transistor M6 are P-type thin film transistors.

The first electrodes and second electrodes of the thin film transistors in the present embodiment can be sources or drains of the thin film transistors.

FIG. 6 is a schematic diagram of timing of respective signals when the GOA unit of the fifth embodiment of the present disclosure operates. According to the timing diagram as shown in FIG. 6, by taking the first stage of gate drive on array unit as an example, the operation process of the gate drive on array unit is divided into an output signal phase t1 and a reset phase t2.

In the output signal phase t1, an input INPUT is at a high level. Since the first thin film transistor M1 is the N-type thin film transistor, M1 is turned on. At this time, the clock signal CLK is also at the high level. Since the second thin film transistor M2 is the N-type thin film transistor and the third thin film transistor M3 is the P-type thin film transistor, M2 is turned on and M3 is stilled off. At this time, G(1) outputs the high level.

In the reset phase t2, the clock signal CLK is at a low level, and then the second thin film transistor M2 is turned off and the third thin film transistor M3 is turned on. At this time, the output terminal G(1) outputs the low level. Since the output terminal G(1) is connected to the gate of the fifth thin film transistor M5 and the fifth thin film transistor M5 and the sixth thin film transistor M6 are P-type thin film transistors, M5 is turned on, and since the clock signal CLK is at the low level at this time, M6 is turned on. At this time, the output terminal G(2) outputs the high level; since G(2) is connected to the gate of the fourth thin film transistor M4 and M4 is the N-type thin film transistor, M4 is turned on and the output terminal G(1) is maintained to output the low level thereby completing the reset operation on the output terminal G(1).

FIG. 7 is a schematic diagram of a circuit of a GOA unit of a sixth embodiment of the present disclosure. As shown in FIG. 7, the circuit comprises the (2n)-th, the (2n+1)-th, and the (2n+2)-th stages of gate drive on array units. In the sixth embodiment, the (2n)-th, the (2n+1)-th, and the (2n+2)-th stages of gate drive on array units comprise the control module 11, the output module 12 and the reset module 13. Herein, the control module 11 of the (2n)-th stage of gate drive on array unit comprises the first thin film transistor M1, the output module 12 thereof comprises the second thin film transistor M2 and the third thin film transistor M3, and the reset module 13 thereof comprises the fourth thin film transistor M4; the control module 11 of the (2n+1)-th stage of gate drive on array unit comprises the fifth thin film transistor M5, the output module 12 thereof comprises the sixth thin film transistor M6 and the seventh thin film transistor M7, and the reset module 13 thereof comprises the eighth thin film transistor M8; the control module 11 of the (2n+2)-th stage of gate drive on array unit comprises a ninth thin film transistor M9, the output module 12 thereof comprises a tenth thin film transistor M10 and an eleventh thin film transistor M11, and the reset module 13 thereof comprises a twelfth thin film transistor M12.

In the present embodiment, a gate of the first thin film transistor M1 is connected to the output terminal G(2n−1) of the gate driving signal of the previous stage; a first electrode of the first thin film transistor M1 is connected to the clock signal input terminal CLK, and a second electrode of the first thin film transistor M1 is connected to a gate of the second thin film transistor M2 and a gate of the third thin film transistor M3.

A first electrode of the second thin film transistor M2 is connected to the high level signal terminal VGH, and a second electrode of the second thin film transistor M2 is connected to a first electrode of the third thin film transistor M3 and an output terminal G(2n) of the gate driving signal of the present stage respectively.

A second electrode of the third thin film transistor M3 is connected to the low level signal terminal VGL and a first electrode of the fourth thin film transistor M4 respectively.

A gate of the fourth thin film transistor M4 is connected to the output terminal G(2n+1) of the gate driving signal of the next stage, and a second electrode of the fourth thin film transistor M4 is connected to the output terminal G(n) of the gate driving signal of the present stage.

A gate of the fifth thin film transistor M5 is connected to the output terminal G(2n) of the gate driving signal of the previous stage, a first electrode of the fifth thin film transistor M5 is connected to the clock signal input terminal CLK, and a second electrode of the fifth thin film transistor M5 is connected to a gate of the sixth thin film transistor M6 and a gate of the seventh thin film transistor M7 respectively.

A first electrode of the sixth thin film transistor M6 is connected to the high level signal terminal VGH, and a second electrode of the sixth thin film transistor M6 is connected to a first electrode of the seventh thin film transistor M7 and the output terminal G(2n+1) of the gate driving signal of the present stage respectively.

A second electrode of the seventh thin film transistor M7 is connected to the low level signal terminal VGL and a first electrode of the eighth thin film transistor M8 respectively.

A gate of the eighth thin film transistor M8 is connected to an output terminal G(2n+2) of the gate driving signal of the next stage, and a second electrode of the eighth thin film transistor M8 is connected to the output terminal G(2n+1) of the gate driving signal of the present stage.

A gate of the ninth thin film transistor M9 is connected to the output terminal G(2n+1) of the gate driving signal of the previous stage, a first electrode of the ninth thin film transistor M9 is connected to the clock signal input terminal CLK, and a second electrode of the ninth thin film transistor M9 is connected to a gate of the tenth thin film transistor M10 and a gate of the eleventh thin film transistor M11 respectively;

A first electrode of the tenth thin film transistor M10 is connected to the high level signal terminal VGH, and a second electrode of the tenth thin film transistor M10 is connected to a first electrode of the eleventh thin film transistor M11 and the output terminal G(2n+2) of the gate driving signal of the present stage respectively;

A second electrode of the eleventh thin film transistor M11 is connected to the low level signal terminal VGL and a first electrode of the twelfth thin film transistor M12 respectively.

A gate of the twelfth thin film transistor M12 is connected to an output terminal G(2n+3) of the gate driving signal of the next stage, and a second electrode of the twelfth thin film transistor M12 is connected to the output terminal G(2n+2) of the gate driving signal of the present stage.

As an example, the first thin film transistor M1, the second thin film transistor M2, the fifth thin film transistor M5, the seventh thin film transistor M7, the ninth thin film transistor M9 and the tenth thin film transistor M10 are P-type thin film transistors; the third thin film transistor M3, the fourth thin film transistor M4, the sixth thin film transistor M6, the eighth thin film transistor M8, the eleventh thin film transistor M11 and the twelfth thin film transistor M12 are N-type thin film transistors.

FIG. 8 is a schematic diagram of timing of respective signals when a GOA unit of a sixth embodiment of the present disclosure operates. According to the timing diagram as shown in FIG. 6, the operation process of the gate drive on array unit is divided into t1, t2, t3 phases, wherein the t1 phase is an output signal phase of the (2n)-th stage of gate drive on array unit, the t2 phase is an output signal phase of the (2n+1)-th stage of gate drive on array unit, and the t3 phase is an output signal phase of the (2n+2)-th stage of gate drive on array unit. Correspondingly, the output signal phase of each stage of gate drive on array unit is the reset phase of the previous stage of gate drive on array unit.

In the phase t1, since G(2n−1) is at the low level and the first thin film transistor M1 is the P-type thin film transistor, M1 is turned on. At this time, the clock signal CLK is at the low level. Since the second thin film transistor M2 is the P-type thin film transistor and the third thin film transistor M3 is the N-type thin film transistor, M2 is turned on and M3 is stilled off. At this time, G(2n) outputs the high level.

In the phase t2, the clock signal CLK is at the high level, and then the second thin film transistor M2 is turned off and the third thin film transistor M3 is turned on. At this time, G(2n) outputs the low level. Since G(2n) is connected to the gate of the fifth thin film transistor M5 and the fifth thin film transistor M5 is the P-type thin film transistors, M5 is turned on, and since the clock signal CLK is at the high level at this time, and the sixth thin film transistor M6 is the N-type thin film transistor and the seventh thin film transistor M7 is the P-type thin film transistor, M6 is turned on, M7 is turned off, and the output terminal G(2n+1) outputs the high level; since G(2n+1) is connected to the gate of the fourth thin film transistor M4 and M4 is the N-type thin film transistor, M4 is turned on and G(2n) is maintained to output the low level, thereby completing the reset operation on G(2n).

In the phase t3, the clock signal CLK is at the low level, and then M6 is turned off and M7 is turned on. At this time, G(2n+1) outputs the low level. Since G(2n+1) is connected to the gate of the ninth thin film transistor M9 and M9 is the P-type thin film transistor, M9 is turned on, and since CLK is at the low level at this time, the tenth thin film transistor M10 is the P-type thin film transistor, and the eleventh thin film transistor M11 is the N-type thin film transistor, M9 is turned on, M10 is turned off, and G(2n+2) outputs the high level; since G(2n+2) is connected to the gate of the eighth thin film transistor M8 and M8 is the N-type thin film transistor, M8 is turned on. G(2n+1) is maintained to output the low level thereby completing the reset operation on G(2n+1).

Based on the above gate drive on array unit, there further provides in embodiments of the present disclosure an gate drive on array circuit comprising more than one gate drive on array unit as described above; and

except the first stage of gate drive on array unit, the signal input terminal of each stage of gate drive on array unit is connected to the output terminal of the gate driving signal of the previous stage of gate drive on array unit;

except the last stage of gate drive on array unit, the reset terminal of each stage of gate drive on array unit is connected to the output terminal of the gate driving signal of the next stage of gate drive on array unit.

There is also disclosed herein a display device of the embodiments of the present disclosure. The display device comprises the above display panel. The display device may be any product or elements having the displaying function, such as a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal TV, a liquid crystal display, a digital photo frame, a mobile phone and a tablet computer and the like.

The above descriptions are just exemplary embodiments of the present disclosure and not used to limit the protection scope of the present disclosure. Any amendments, equivalent replacements, improvements and so on made within the spirit and scope of the present disclosure are included in the protection scope of the present disclosure.

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21.0/100 Score

Market Attractiveness

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47.0/100 Score

Market Coverage

It shows the sizes of the market that is covered with the IP and in how many countries the IP guarantees protection. It reflects a market size that is potentially addressable with the invented technology/formulation with a legal protection which also includes a freedom to operate. Here we look into the size of the impacted market.

68.69/100 Score

Technology Quality

It shows the degree of innovation that can be derived from a company’s IP. Here we look into ease of detection, ability to design around and significance of the patented feature to the product/service.

84.0/100 Score

Assignee Score

It takes the R&D behavior of the company itself into account that results in IP. During the invention phase, larger companies are considered to assign a higher R&D budget on a certain technology field, these companies have a better influence on their market, on what is marketable and what might lead to a standard.

20.64/100 Score

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Citation

Patents Cited in This Cited by
Title Current Assignee Application Date Publication Date
ゲート駆動回路及びそれを有する表示装置 三星ディスプレイ株式會社,SAMSUNG DISPLAY CO.,LTD. 21 December 2010 17 November 2011
半导体电路、显示装置及具有该显示装置的电子设备 株式会社半导体能源研究所 02 December 2005 13 September 2006
移位寄存器及其驱动方法、栅极驱动装置与显示装置 京东方科技集团股份有限公司,成都京东方光电科技有限公司 28 November 2011 03 October 2012
栅极集成驱动电路、移位寄存器及显示屏 北京京东方光电科技有限公司 22 August 2011 08 August 2012
移位寄存器单元及其驱动方法、栅极驱动电路及显示装置 北京京东方光电科技有限公司 16 April 2013 07 August 2013
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