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Patent Analysis of

Signal quality detection circuit for generating signal quality detection result according to two-dimensional nominal sampling point pattern and associated signal quality detection method

Updated Time 12 June 2019

Patent Registration Data

Publication Number

US10002650

Application Number

US15/387602

Application Date

21 December 2016

Publication Date

19 June 2018

Current Assignee

MEDIATEK INC.

Original Assignee (Applicant)

MEDIATEK INC.

International Classification

G11C7/06,G01R31/317,H03K5/24,G11C8/18,G11C7/22

Cooperative Classification

G11C7/22,G01R31/31708,G11C8/18,H03K5/24,G11C7/222

Inventor

HSU, PIN-HUAN

Patent Images

This patent contains figures and images illustrating the invention and its embodiment.

US10002650 Signal quality detection circuit 1 US10002650 Signal quality detection circuit 2 US10002650 Signal quality detection circuit 3
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Abstract

A signal quality detection circuit has a sampling circuit and a comparing circuit. The sampling circuit samples an input signal associated with a target device according to a plurality of nominal sampling points, and generates a plurality of sampled bits corresponding to the nominal sampling points, respectively. The nominal sampling points are set by different combinations of sampling time and sampling reference voltage, and the number of the nominal sampling points is larger than four. The comparing circuit generates a signal quality detection result by performing comparison according to the sampled bits.

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Claims

1. A signal quality detection circuit comprising: a sampling circuit, configured to sample an input signal associated with a target device according to a plurality of nominal sampling points, and generate a plurality of sampled bits corresponding to the nominal sampling points, respectively, wherein the nominal sampling points are set by different combinations of sampling time and sampling reference voltage, and a number of the nominal sampling points is larger than four; and a comparing circuit, configured to generate a plurality of comparison results each derived from comparing two of the sampled bits, and generate a signal quality detection result according to the comparison results; wherein the signal quality detection circuit is included in a memory chip, and the comparing circuit is further configured to write the signal quality detection result into a mode register of the memory chip.

2. The signal quality detection circuit of claim 1, wherein the target device is the memory chip.

3. The signal quality detection circuit of claim 2, wherein the input signal is received by a data pin of the memory chip.

4. The signal quality detection circuit of claim 2, wherein the input signal is received by a command pin of the memory chip.

5. The signal quality detection circuit of claim 2, wherein the input signal is received by an address pin of the memory chip.

6. The signal quality detection circuit of claim 2, wherein the input signal is a loopback signal of an output signal generated to an output pin of the memory chip.

7. The signal quality detection circuit of claim 1, wherein the number of the nominal sampling points is not smaller than nine.

8. The signal quality detection circuit of claim 1, wherein the nominal sampling points comprises at least three nominal sampling points that are set by same sampling time but different sampling reference voltages.

9. The signal quality detection circuit of claim 1, wherein the nominal sampling points comprises at least three nominal sampling points that are set by a same sampling reference voltage but different sampling time.

10. A signal quality detection method comprising: setting a plurality of nominal sampling points by different combinations of sampling time and sampling reference voltage, wherein a number of the nominal sampling points is larger than four; sampling an input signal associated with a target device according to the nominal sampling points, and generating a plurality of sampled bits corresponding to the nominal sampling points, respectively; generating a plurality of comparison results each derived from comparing two of the sampled bits, and generating a signal quality detection result according to the comparison results; and writing the signal quality detection result into a mode register of a memory chip, wherein the signal quality detection method is performed by the memory chip.

11. The signal quality detection method of claim 10, wherein the target device is the memory chip.

12. The signal quality detection method of claim 11, wherein the input signal is received by a data pin of the memory chip.

13. The signal quality detection method of claim 11, wherein the input signal is received by a command pin of the memory chip.

14. The signal quality detection method of claim 11, wherein the input signal is received by an address pin of the memory chip.

15. The signal quality detection method of claim 11, wherein the input signal is a loopback signal of an output signal generated to an output pin of the memory chip.

16. The signal quality detection method of claim 10, wherein the number of the nominal sampling points is not smaller than nine.

17. The signal quality detection method of claim 10, wherein the nominal sampling points comprises at least three nominal sampling points that are set by same sampling time but different sampling reference voltages.

18. The signal quality detection method of claim 10, wherein the nominal sampling points comprises at least three nominal sampling points that are set by a same sampling reference voltage but different sampling time.

19. A signal quality detection circuit comprising: a sampling circuit, configured to sample an input signal associated with a target device according to a plurality of nominal sampling points, and generate a plurality of sampled bits corresponding to the nominal sampling points, respectively, wherein the nominal sampling points are set by different combinations of sampling time and sampling reference voltage, and a number of the nominal sampling points is larger than four; and a comparing circuit, configured to generate a plurality of comparison results each derived from comparing two of the sampled bits, and generate a signal quality detection result according to the comparison results; wherein the input signal is used to transmit a bit sequence having each bit transmitted in one bit period; the sampled bits comprise at least a first sampled bit, a second sampled bit and a third sampled bit that are generated at different sampling time during a same bit period; and the comparison results comprise at least a first comparison result derived from comparing the first sampled bit and the second sampled bit and a second comparison result derived from comparing the third sampled bit and the second sampled bit.

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Claim Tree

  • 1
    1. A signal quality detection circuit comprising:
    • a sampling circuit, configured to sample an input signal associated with a target device according to a plurality of nominal sampling points, and generate a plurality of sampled bits corresponding to the nominal sampling points, respectively, wherein the nominal sampling points are set by different combinations of sampling time and sampling reference voltage, and a number of the nominal sampling points is larger than four
    • and a comparing circuit, configured to generate a plurality of comparison results each derived from comparing two of the sampled bits, and generate a signal quality detection result according to the comparison results
    • wherein the signal quality detection circuit is included in a memory chip, and the comparing circuit is further configured to write the signal quality detection result into a mode register of the memory chip.
    • 2. The signal quality detection circuit of claim 1, wherein
      • the target device is the memory chip.
    • 7. The signal quality detection circuit of claim 1, wherein
      • the number of the nominal sampling points is not smaller than nine.
    • 8. The signal quality detection circuit of claim 1, wherein
      • the nominal sampling points comprises
    • 9. The signal quality detection circuit of claim 1, wherein
      • the nominal sampling points comprises
  • 10
    10. A signal quality detection method comprising:
    • setting a plurality of nominal sampling points by different combinations of sampling time and sampling reference voltage, wherein a number of the nominal sampling points is larger than four
    • sampling an input signal associated with a target device according to the nominal sampling points, and generating a plurality of sampled bits corresponding to the nominal sampling points, respectively
    • generating a plurality of comparison results each derived from comparing two of the sampled bits, and generating a signal quality detection result according to the comparison results
    • and writing the signal quality detection result into a mode register of a memory chip, wherein the signal quality detection method is performed by the memory chip.
    • 11. The signal quality detection method of claim 10, wherein
      • the target device is the memory chip.
    • 16. The signal quality detection method of claim 10, wherein
      • the number of the nominal sampling points is not smaller than nine.
    • 17. The signal quality detection method of claim 10, wherein
      • the nominal sampling points comprises
    • 18. The signal quality detection method of claim 10, wherein
      • the nominal sampling points comprises
  • 19
    19. A signal quality detection circuit comprising:
    • a sampling circuit, configured to sample an input signal associated with a target device according to a plurality of nominal sampling points, and generate a plurality of sampled bits corresponding to the nominal sampling points, respectively, wherein the nominal sampling points are set by different combinations of sampling time and sampling reference voltage, and a number of the nominal sampling points is larger than four
    • and a comparing circuit, configured to generate a plurality of comparison results each derived from comparing two of the sampled bits, and generate a signal quality detection result according to the comparison results
    • wherein the input signal is used to transmit a bit sequence having each bit transmitted in one bit period
    • the sampled bits comprise at least a first sampled bit, a second sampled bit and a third sampled bit that are generated at different sampling time during a same bit period
    • and the comparison results comprise at least a first comparison result derived from comparing the first sampled bit and the second sampled bit and a second comparison result derived from comparing the third sampled bit and the second sampled bit.
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Description

BACKGROUND

The present invention relates to a signal quality detection scheme, and more particularly, to a signal quality detection circuit for generating a signal quality detection result according to a two-dimensional nominal sampling point pattern and an associated signal quality detection method.

An oscilloscope is a type of electronic test instrument that allows observation of constantly varying signal voltages, and usually displays a two-dimensional plot of one or more signals as a function of time. Hence, the oscilloscope is commonly used to observe the change of an electrical signal (e.g., a voltage signal) over time. The observed waveform can be analyzed for determining signal properties such as amplitude, frequency, distortion and others. However, to use an oscilloscope to measure a signal quality of an electrical signal of a device under test, the associated preparatory work is quite troublesome. Moreover, the oscilloscope is required to use probes to receive signals from the device under test. However, it is possible that the probes of the oscilloscope are unable to have direct contact with the device under test, and are therefore indirectly connected to the device under test via an intermediate medium/structure. As a result, the measured signal quality may be different from the actual signal quality of the electrical signal of the device under test.

The oscilloscope is quite expensive, and may not be affordable for every manufacturer. In addition, the oscilloscope requires calibration, repair, etc. Hence, a considerable maintenance fee of the oscilloscope may be needed. Further, a lot of manpower may be needed to perform the signal quality measurement using the oscilloscope. As a result, using an oscilloscope to measure a signal quality of an electrical signal of a device under test is not a cost-efficient solution.

Thus, there is a need for an innovative signal quality detection scheme capable of detecting actual signal quality of an electrical signal of a device under test (e.g., a dynamic random access memory) without the use of an oscilloscope.

SUMMARY

One of the objectives of the claimed invention is to provide a signal quality detection circuit for generating a signal quality detection result according to a two-dimensional nominal sampling point pattern and an associated signal quality detection method.

According to a first aspect of the present invention, an exemplary signal quality detection circuit is disclosed. The exemplary signal quality detection circuit includes a sampling circuit and a comparing circuit. The sampling circuit is configured to sample an input signal associated with a target device according to a plurality of nominal sampling points, and generate a plurality of sampled bits corresponding to the nominal sampling points, respectively, wherein the nominal sampling points are set by different combinations of sampling time and sampling reference voltage, and a number of the nominal sampling points is larger than four. The comparing circuit is configured to generate a signal quality detection result by performing comparison according to the sampled bits.

According to a second aspect of the present invention, an exemplary signal quality detection method is disclosed. The exemplary signal quality detection method includes: setting a plurality of nominal sampling points by different combinations of sampling time and sampling reference voltage, wherein a number of the nominal sampling points is larger than four; sampling an input signal associated with a target device according to the nominal sampling points, and generating a plurality of sampled bits corresponding to the nominal sampling points, respectively; and generating a signal quality detection result by performing comparison according to the sampled bits.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating a sampling operation performed upon an input signal according to a nominal sampling point.

FIG. 2 is a diagram illustrating a two-dimensional nominal sampling point pattern according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a signal quality detection circuit according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating a memory chip with an internal signal quality detection circuit according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating a circuit design of the sampling circuit and the comparing circuit shown in FIG. 3 according to an embodiment of the present invention.

FIG. 6 is a diagram illustrating a case where the signal quality detection result generated by the proposed signal quality detection indicates “good” signal quality of an ideal input signal with no distortion.

FIG. 7 is a diagram illustrating a case where the signal quality detection result generated by the proposed signal quality detection indicates “poor” signal quality of a distorted input signal with distortion.

FIG. 8 is a diagram illustrating a case where the signal quality detection result generated by the proposed signal quality detection indicates “poor” signal quality of an input signal with timing shift.

FIG. 9 is a diagram illustrating another circuit design of the sampling circuit and the comparing circuit shown in FIG. 3 according to an embodiment of the present invention.

DETAILED DESCRIPTION

Certain terms are used throughout the following description and claims, which refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not in function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

FIG. 1 is a diagram illustrating a sampling operation performed upon an input signal according to a nominal sampling point. As shown in FIG. 1, a nominal sampling point SPN is set by a combination of sampling time TSP and sampling reference voltage Vref. In this example, an input signal SIN is used to transmit a bit sequence “101”, where each bit is transmitted in one bit period TBIT. During the first bit period TBIT, a voltage VSP is sampled at the sampling time TSP of the nominal sampling point SPN, and the sampled voltage VSP is compared with the sampling reference voltage Vref of the nominal sampling point SPN. Since the sampled voltage VSP is higher than the sampling reference voltage Vref (i.e., VSP>Vref), a sampled bit that is represented by the sampled voltage VSP obtained during the first bit period TBIT is judged to be “1”.

During the second bit period TBIT, a voltage VSP is sampled at the sampling time TSP of the nominal sampling point SPN, and the sampled voltage VSP is compared with the sampling reference voltage Vref of the nominal sampling point SPN. Since the sampled voltage VSP is lower than the sampling reference voltage Vref (i.e., VSP<Vref), a sampled bit that is represented by the sampled voltage VSP obtained during the second bit period TBIT is judged to be “0”.

During the third bit period TBIT, a voltage VSP is sampled at the sampling time TSP of the nominal sampling point SPN, and the sampled voltage VSP is compared with the sampling reference voltage Vref of the nominal sampling point SPN. Since the voltage VSP is higher than the sampling reference voltage Vref (i.e., VSP>Vref), a sampled bit that is represented by the sampled voltage VSP obtained during the third bit period TBIT is judged to be “1”.

FIG. 1 shows an ideal waveform of the input signal SIN that transmits the bit sequence “101” with no signal distortion. However, an actual waveform of the input signal SIN that transmits the bit sequence “101” may be distorted due to certain factors. As a result, using the nominal sampling point SPN shown in FIG. 1 may not correctly recover the sampled bits “1”, “0”, “1” from the input signal SIN with a distorted waveform. If the signal quality of the input signal SIN is known, the signal quality may provide information needed for configuring the hardware circuitry to correctly obtain sampled bits from the input signal SIN. In contrast to a typical signal quality measurement design using an oscilloscope, the present invention proposes using a nominal sampling point pattern to achieve the signal quality detection needed.

FIG. 2 is a diagram illustrating a two-dimensional nominal sampling point pattern according to an embodiment of the present invention. In this example, an eye pattern of an input signal may be simply modeled by a hexagon. Hence, a nominal sampling point pattern defined by multiple nominal sampling points (e.g., nine nominal sampling points SPN and SPN_1-SPN_8) may be used for signal quality detection. By way of example, but not limitation, the nominal sampling points SPN and SPN_1-SPN_8 used for signal quality detection may be selected according to the clock frequency, the semiconductor process, etc. As shown in FIG. 2, in addition to the central nominal sampling point SPN (which is set by sampling time TSP and sampling reference voltage Vref), neighboring nominal sampling points SPN_1-SPN_8 are also selected, where the nominal sampling point SPN_1 is set by a combination of sampling time TSP−ΔT and sampling reference voltage Vref−ΔV, the nominal sampling point SPN_2 is set by a combination of sampling time TSP and sampling reference voltage Vref−ΔV, the nominal sampling point SPN_3 is set by a combination of sampling time TSP+ΔT and sampling reference voltage Vref−ΔV, the nominal sampling point SPN_4 is set by a combination of sampling time TSP−ΔT and sampling reference voltage Vref, the nominal sampling point SPN_5 is set by a combination of sampling time TSP+ΔT and sampling reference voltage Vref, the nominal sampling point SPN_6 is set by a combination of sampling time TSP−ΔT and sampling reference voltage Vref+ΔV, the nominal sampling point SPN_7 is set by a combination of sampling time TSP and sampling reference voltage Vref+ΔV, and the nominal sampling point SPN_8 is set by a combination of sampling time TSP+ΔT and sampling reference voltage Vref+ΔV. In this example, the nominal sampling points SPN and SPN_1-SPN_8 are set by different combinations of sampling time and sampling reference voltage, where different sampling reference voltages Vref−ΔV, Vref, Vref+ΔV are equally spaced, and the different sampling time TSP−ΔT, TSP, TSP+ΔT is equally spaced. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. Alternatively, different sampling reference voltages used for configuring different nominal sampling points may be set by other voltage values according to the actual design considerations, and/or different sampling time used for configuring different nominal sampling points may be set by other timing values according to the actual design considerations. To put it simply, the nominal sampling point pattern shown in FIG. 2 is for illustrative purposes only, and is not meant to be a limitation of the present invention.

The sampled bits obtained according to the nominal sampling points SPN and SPN_1-SPN_8 are used for signal quality detection. For example, when one sampled bit obtained by one nominal sampling point during a bit period of the input signal SIN is different from another sampled bit obtained by another nominal sampling point during the same bit period of the input signal SIN, the input signal SIN may be regarded as having a distorted waveform, and the distortion position may be determined correspondingly. Based on this observation, the present invention proposes a signal quality detection circuit which performs signal quality detection upon the input signal SIN according to a nominal sampling point pattern such as the nominal sampling point pattern shown in FIG. 2.

The proposed signal quality detection circuit may be configured to check the signal quality detection requirement as requested by the manufacturer. For example, the setup/hold time requirement may be examined by properly setting the time difference ΔT, and the voltage requirement may be examined by properly setting the voltage difference ΔV. If good signal quality is indicated by the proposed signal quality detection circuit, this means the setup/hold time requirement and the voltage requirement are both met to thereby satisfy the signal quality detection requirement as requested by the manufacturer.

FIG. 3 is a diagram illustrating a signal quality detection circuit according to an embodiment of the present invention. The signal quality detection circuit 300 includes a voltage generator 302, a clock generator 304, a sampling circuit 306, and a comparing circuit 308. In one exemplary design, the voltage generator 302 and the clock generator 304 may be dedicated components of the signal quality detection circuit 300. In another exemplary design, the voltage generator 302 and the clock generator 304 may be common components shared by the signal quality detection circuit 300 and other signal processing circuit(s). The voltage generator 302 is configured to provide different sampling reference voltages Vref−ΔV, Vref, Vref+ΔV. The clock generator 304 is configured to provide a plurality of clocks CLK1, CLK2, CLK3 with the same frequency but different phases. For example, when the sampling circuit 306 is rising-edge triggered, rising edges of the clocks CLK1, CLK2, CLK3 may be used to provide different sampling time TSP−ΔT, TSP, TSP+ΔT. For another example, when the sampling circuit 306 is falling-edge triggered, falling edges of the clocks CLK1, CLK2, CLK3 may be used to provide different sampling time TSP−ΔT, TSP, TSP+ΔT.

The sampling circuit 306 is configured to sample an input signal SIN associated with a target device (e.g., a memory chip) according to a plurality of nominal sampling points (e.g., SPN and SPN_1-SPN_8), and generate a plurality of sampled bits (collectively denoted by “SB”) corresponding to the nominal sampling points, respectively, wherein the nominal sampling points are set by different combinations of sampling time and sampling reference voltage. The number of the nominal sampling points is larger than four, depending upon the nominal sampling point pattern used. In a case where the nominal sampling point pattern shown in FIG. 2 or a larger nominal sampling point pattern is employed, the number of the nominal sampling points is not smaller than nine. The comparing circuit 308 is configured to generate a signal quality detection result SQ by performing comparison according to the sampled bits SB obtained by the sampling circuit 306.

In one exemplary application, the target device with the input signal SIN that is examined by the signal quality detection circuit 300 may be a memory chip such as a low-power double-data-rate memory (LPDDR4) chip. The signal quality detection circuit 300 may be integrated within the memory chip to provide an on-chip signal quality detection function. FIG. 4 is a diagram illustrating a memory chip with an internal signal quality detection circuit according to an embodiment of the present invention. By way of example, but not limitation, the memory chip 400 may be an LPDDR4 chip. As shown in FIG. 4, the memory chip 400 includes memory circuitry 402 (denoted by “CKT”) that may include memory cells, a read circuit, a write circuit, a self-refresh circuit, etc. Hence, the memory circuitry CKT receives a plurality of data signals from a plurality of data pins PDATA of the memory chip 400, receives a plurality of command signals from a plurality of command pins PCMD of the memory chip 400, receives a plurality of address signals from a plurality of address pins PADDR of the memory chip 400, and generates a plurality of output signals (e.g., memory readout signals) to a plurality of output pins POUT of the memory chip 400. The data signals, command signals and address signals may be transmitted from a memory controller (not shown) to the memory chip 400, and the output signals may be transmitted from the memory chip 400 to the memory controller (not shown).

The input signal SIN to be examined by the signal quality detection circuit 300 may be received by one of the data pins PDATA of the memory chip 400, may be received by one of the command pins PCMD of the memory chip 400, may be received by one of the address pins PADDR of the memory chip 400, or may be a loopback signal of an output signal generated to one of the output pins Pour of the memory chip 400. In other words, the signal quality detection circuit 300 can be used to judge the signal quality of the input signal SIN exactly received by the memory chip 400, and can be used to judge the signal quality of the input signal SIN exactly transmitted from the memory chip 400. Hence, signal quality of the input signal SIN actually received by or transmitted from the memory chip 400 can be reflected in the signal quality detection result SQ generated from the signal quality detection circuit 300. In addition, based on the detected signal quality of the input signal SIN, the memory chip 400 can be properly configured to set/adjust the nominal sampling point SPN that is used to recover bits transmitted via the input signal SIN.

With regard to the memory chip 400, there is a multiplexer (MUX) 404 having a plurality of input ports coupled to data pins PDATA, command pins PCMD, and address pins PADDR that are associated with a receiver (RX) end of the memory circuitry 402) and output pins POUT that are associated with a transmitter (TX) end of the memory circuitry 402. An output port of the multiplexer 404 is coupled to the signal quality detection circuit 300. Hence, with proper signal selection control of the multiplexer 404, the same signal quality detection circuit 300 can be used to perform signal quality detection upon one of input signals received by the memory chip 400 and output signals transmitted from the memory chip 400, and then can be reused to perform signal quality detection upon another of input signals received by the memory chip 400 and output signals transmitted from the memory chip 400. The signal selection control of the multiplexer 404 may be achieved by programming a mode register (MR) 406 of the memory chip 400. That is, a source of the input signal SIN can be switched by adjusting one or more bits stored in the mode register 406. Further, the signal quality detection result SQ generated from the signal quality detection circuit 300 may be written into a mode register (MR) 408 of the memory chip 400, and the configuration of the signal quality detection circuit 300 may be adjusted by setting bits in a mode register (MR) 410 of the memory chip 400. It should be noted that the mode registers 406, 408, 410 may be realized using a same mode register or different mode registers, depending upon the actual design considerations. Further details of the signal quality detection circuit 300 are described as below.

FIG. 5 is a diagram illustrating a circuit design of the sampling circuit 306 and the comparing circuit 308 shown in FIG. 3 according to an embodiment of the present invention. To reduce hardware complexity and production cost, the sampled bits corresponding to the nominal sampling points SPN and SPN_1-SPN_8 may be obtained in three bit periods of the input signal SIN. In this embodiment, the sampling circuit 306 includes a plurality of sample and hold circuits (denoted by “S/H”) 502, 504, 506, a multiplexer (MUX) 510, and a plurality of comparators 512, 514, 516; and the comparing circuit 308 includes a plurality of comparators 522, 524. Each of the sample and hold circuits 502, 504, 506 is triggered by a clock received at a clock input port to sample a voltage input received at an input port, and then holds a sampled voltage at an output port. As shown in FIG. 5, the same input signal SIN is fed into input ports of all sample and hold circuits 502, 504, 506. As mentioned above, the clocks CLK1, CLK2, CLK3 have the same frequency but different phases, such that the clocks CLK1, CLK2, CLK3 are used to provide different sampling time TSP−ΔT, TSP, TSP+ΔT. As shown in FIG. 5, the clock CLK1 is fed into the clock input port of the sample and hold circuit 502, the clock CLK2 is fed into the clock input port of the sample and hold circuit 504, and the clock CLK3 is fed into the clock input port of the sample and hold circuit 506. Hence, the waveform of the input signal SIN may be sampled by the sample and hold circuits 502, 504, 506 at different sampling time TSP−ΔT, TSP, TSP+ΔT during the same bit period. The sampled voltages are held at the output ports of the sample and hold circuits 502, 504, 506, and are provided to the comparators 512, 514, 516, respectively.

The comparators 512, 514, 516 receive the same sampling reference voltage from an output port of the multiplexer 510. The comparator 512 is configured to compare a sampled voltage generated from the preceding sample and hold circuit 502 with the received sampling reference voltage to generate a sampled bit B1. The comparator 512 is configured to compare the sampled voltage generated from the preceding sample and hold circuit 502 with the received sampling reference voltage to generate a sampled bit B2. The comparator 514 is configured to compare the sampled voltage generated from the preceding sample and hold circuit 506 with the received sampling reference voltage to generate a sampled bit B3. Concerning each of the comparators 512, 514, 516 in this embodiment, a comparison result (i.e., sampled bit) is set by a logic-high level “1” when the sampled voltage is higher than the sampling reference voltage, and the comparison result (i.e., sampled bit) is set by a logic-low level “0” when the sampled voltage is not higher than the sampling reference voltage.

During one bit period, three sampled bits B1, B2, B3 are obtained according to three nominal sampling points. Since the sampled bits B1, B2, B3 are obtained during the same bit period of the input signal SIN, the sampled bits B1, B2, B3 are expected to have the same value if the input signal SIN is not distorted during the bit period. Hence, the three sampled bits B1, B2, B3 are generated from the sampling circuit 306 to the comparing circuit 308 for signal quality evaluation. The sampled bits B1, B2, B3 are obtained according to three nominal sampling points, including a middle nominal sampling point and two neighboring nominal sampling points. In this embodiment, the comparing circuit 308 generates a partial signal quality detection result associated with the three nominal sampling points by comparing the sampled bit B2 obtained according to the middle nominal sampling point with each of the sampled bits B1 and B3 obtained according to the neighboring nominal sampling points. The comparator 522 is configured to compare the sampled bits B1 and B2 to generate one bit Q1 indicative of the signal quality associated with two nominal sampling points. The comparator 524 is configured to compare the sampled bits B3 and B2 to generate one bit Q2 indicative of the signal quality associated with two nominal sampling points.

Concerning the comparator 522, a comparison result (i.e., bit Q1) is set by “0” to indicate “good” signal quality when the sampled bits B1 and B2 are the same, and the comparison result (i.e., bit Q1) is set by “1” to indicate “poor” signal quality when the sampled bits B1 and B2 are different. Concerning the comparator 524, a comparison result (i.e., bit Q2) is set by “0” to indicate “good” signal quality when the sampled bits B3 and B2 are the same, and the comparison result (i.e., Q1) is set by “1” to indicate “poor” signal quality when the sampled bits B3 and B2 are different. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. Alternatively, the comparing circuit 308 may be modified to output “1” for indicating “good” signal quality and output “0” for indicating “poor” signal quality.

In this embodiment, the sampled bits associated with the nominal sampling points SPN and SPN_1-SPN_8 are obtained by the sampling circuit 306 in more than one bit period of the input signal SIN (e.g., three bit periods of the input signal SIN). Hence, the multiplexer 510 is configured to output the sampling reference voltages Vref−ΔV, Vref, Vref+4V one by one. For example, the sampling reference voltage Vref−ΔV is supplied to the comparators 512, 514, 516 during a first bit period, the sampling reference voltage Vref is supplied to the comparators 512, 514, 516 during a second bit period following the first bit period, and the sampling reference voltage Vref+ΔV is supplied to the comparators 512, 514, 516 during a third bit period following the first bit period.

FIG. 6 is a diagram illustrating a case where the signal quality detection result generated by the proposed signal quality detection indicates “good” signal quality of an ideal input signal with no distortion. During the first bit period TBIT, the sampled bits corresponding to the nominal sampling points SPN_1, SPN_2, SPN_3 are all 1's due to the fact that the associated sampled voltages are all higher than the sampling reference voltage Vref−ΔV. Suppose that “good” signal quality is indicated by “0” and “poor” signal quality is indicated by “1”. Hence, bits Q1 and Q2 generated from the comparing circuit 308 in FIG. 5 are set by 0's correspondingly. During the second bit period TBIT, the sampled bits corresponding to the nominal sampling points SPN_4, SPN, SPN_5 are all 0's due to the fact that the associated sampled voltages are all lower than the sampling reference voltage Vref. Hence, bits Q1 and Q2 generated from the comparing circuit 308 in FIG. 5 are set by 0's correspondingly. During the third bit period TBIT, the sampled bits corresponding to the nominal sampling points SPN_6, SPN_7, SPN_8 are all 1's due to the fact that the associated sampled voltages are all higher than the sampling reference voltage Vref+ΔV. Hence, bits Q1 and Q2 generated from the comparing circuit 308 in FIG. 5 are set by 0's correspondingly. Since the signal quality detection result SQ generated from the signal quality detection circuit 300 is composed of 0's only, the signal quality detection result SQ indicates that the input signal has good signal quality. In a case where the input signal SIN is a data signal, a command signal or an address signal actually received by the memory chip 400, the central nominal sampling point SPN of the nominal sampling point pattern employed for signal quality detection may be directly used to recover bits transmitted in following bit periods of the input signal SIN.

FIG. 7 is a diagram illustrating a case where the signal quality detection result generated by the proposed signal quality detection indicates “poor” signal quality of a distorted input signal with distortion. During the first bit period TBIT, the sampled bits corresponding to the nominal sampling points SPN_1, SPN_2 are 1's due to the fact that the associated sampled voltages are all higher than the sampling reference voltage Vref−ΔV, and the sampled bit corresponding to the nominal sampling point SPN_3 is 0 due to the fact that the associated sampled voltage is lower than the sampling reference voltage Vref−ΔV. Assume that “good” signal quality is indicated by “0”, and “poor” signal quality is indicated by “1”. Hence, bits Q1 and Q2 generated from the comparing circuit 308 in FIG. 5 are set by 0 and 1, respectively. During the second bit period TBIT, the sampled bit corresponding to the nominal sampling point SPN_4 is 1 due to the fact that the associated sampled voltage is higher than the sampling reference voltage Vref, and the sampled bits corresponding to the nominal sampling points SPN, SPN_5 are 0's due to the fact that the associated sampled voltages are lower than the sampling reference voltage Vref. Hence, bits Q1 and Q2 generated from the comparing circuit 308 in FIG. 5 are set by 1 and 0, respectively. During the third bit period TBIT, the sampled bits corresponding to the nominal sampling points SPN_6, SPN_8 are 1's due to the fact that the associated sampled voltages are higher than the sampling reference voltage Vref+ΔV, and the sampled bit corresponding to the nominal sampling point SPN_7 is 0 due to the fact that the associated sampled voltage is lower than the sampling reference voltage Vref+ΔV. Hence, bits Q1 and Q2 generated from the comparing circuit 308 in FIG. 5 are set by 1's. Since the signal quality detection result SQ generated from the signal quality detection circuit 300 is composed of 0's and 1's, the signal quality detection result SQ indicates that the input signal has poor signal quality, where each bit “1” included in the signal quality detection result SQ also indicates the location of the signal error (e.g., signal distortion). When the signal quality detection circuit 300 is implemented in the memory chip 400, a memory controller (not shown) may refer to the signal quality detection result SQ (which indicates “poor” signal quality) to properly adjust memory access settings, such as a timing setting, a voltage setting, a frequency setting, a driving current setting, etc. Further, considering a case where the input signal SIN is a data signal, a command signal or an address signal actually received by the memory chip 400, the central nominal sampling point SPN of the nominal sampling point pattern employed for signal quality detection may be properly adjusted and then used to recover bits in following bit periods of the input signal SIN.

FIG. 8 is a diagram illustrating a case where the signal quality detection result generated by the proposed signal quality detection indicates “poor” signal quality of an input signal with timing shift. In this example, the waveform of the input signal SIN shown in FIG. 8 is same as that of the input signal SIN shown in FIG. 6. However, the timing of the input signal SIN shown in FIG. 8 is shifted due to certain factor (s). During the first bit period TBIT, the sampled bits corresponding to the nominal sampling points SPN_1, SPN_2, SPN_3 are 1's due to the fact that the associated sampled voltages are all higher than the sampling reference voltage Vref−ΔV. Assume that “good” signal quality is indicated by “0”, and “poor” signal quality is indicated by “1”. Hence, bits Q1 and Q2 generated from the comparing circuit 308 in FIG. 5 are set by 0's correspondingly. During the second bit period TBIT, the sampled bit corresponding to the nominal sampling point SPN_4 is 1 due to the fact that the associated sampled voltage is higher than the sampling reference voltage Vref, and the sampled bits corresponding to the nominal sampling points SPN, SPN_5 are 0's due to the fact that the associated sampled voltages are lower than the sampling reference voltage Vref. Hence, bits Q1 and Q2 generated from the comparing circuit 308 in FIG. 5 are set by 1 and 0, respectively. During the third bit period TBIT, the sampled bits corresponding to the nominal sampling points SPN_7, SPN_8 are 1's due to the fact that the associated sampled voltages are higher than the sampling reference voltage Vref+ΔV, and the sampled bit corresponding to the nominal sampling point SPN_6 is 0 due to the fact that the associated sampled voltage is lower than the sampling reference voltage Vref+ΔV. Hence, bits Q1 and Q2 generated from the comparing circuit 308 in FIG. 5 are set by 1 and 0, respectively. Since the signal quality detection result SQ generated from the signal quality detection circuit 300 is composed of 0's and 1's, the signal quality detection result SQ indicates that the input signal has poor signal quality, where each bit “1” included in the signal quality detection result SQ also indicates the location of the signal error (e.g., signal timing shift). When the signal quality detection circuit 300 is implemented in the memory chip 400, a memory controller (not shown) may refer to the signal quality detection result SQ (which indicates “poor” signal quality) to properly adjust memory access settings, such as a timing setting, a voltage setting, a frequency setting, a driving current setting, etc. Further, considering a case where the input signal SIN is a data signal, a command signal or an address signal actually received by the memory chip 400, the central nominal sampling point SPN of the nominal sampling point pattern employed for signal quality detection may be properly adjusted and then used to recover bits in following bit periods of the input signal SIN.

A low-complexity and low-cost circuit design shown in FIG. 5 may be employed to realize the sampling circuit 306 and the comparing circuit 308 of the signal quality detection circuit 300, where the sampled bits associated with the nominal sampling points SPN and SPN_1-SPN_8 may be obtained in more than one bit period of the input signal SIN (e.g., three bit periods of the input signal SIN). However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. Alternatively, the sampled bits associated with the nominal sampling points SPN and SPN_1-SPN_8 may be obtained in a single bit period of the input signal SIN.

FIG. 9 is a diagram illustrating another circuit design of the sampling circuit 306 and the comparing circuit 308 shown in FIG. 3 according to an embodiment of the present invention. In this embodiment, the sampling circuit 306 includes a plurality of sample and hold circuits (denoted by “S/H”) 801-809 and a plurality of comparators 811-819; and the comparing circuit 308 includes a plurality of comparators 821-828. Each of the sample and hold circuits 801-809 is triggered by a clock received at a clock input port to sample a voltage input received at an input port, and then holds a sampled voltage at an output port. As shown in FIG. 9, the same input signal SIN is fed into input ports of all sample and hold circuits 801-809, the clock CLK1 is fed into clock input ports of three sample and hold circuits 801-803, the clock CLK2 is fed into the clock input ports of three sample and hold circuits 804-806, and the clock CLK3 is fed into the clock input ports of three sample and hold circuits 807-809. Further, the sample and hold circuits 801-809 generate sampled voltages to the following comparators 811-819, respectively. In this embodiment, the sampling reference voltage Vref−ΔV is supplied to three comparators 813, 816, 819, the sampling reference voltage Vref is supplied to three comparators 812, 815, 818, and the sampling reference voltage Vref+ΔV is supplied to three comparators 811, 814, 817. In this way, sampled bits corresponding to all of the nominal sampling points SPN and SPN_1-SPN_8 can be obtained during a single bit period of the input signal SIN.

In this embodiment, the comparing circuit 308 generates a signal quality detection result SQ associated with the nominal sampling points SPN and SPN_1-SPN_8 by comparing the sampled bit B5 (which is obtained according to a central nominal sampling point SPN of the nominal sampling point pattern employed for signal quality detection) with each of the sampled bits B1-B4 and B6-B9 (which are obtained according to neighboring nominal sampling points SPN_1-SPN_8 included in the nominal sampling point pattern employed for signal quality detection). Hence, the comparison result Q1 is decided by the comparator 821 according to sampled bits B1 and B5, the comparison result Q2 is decided by the comparator 822 according to sampled bits B2 and B5, the comparison result Q3 is decided by the comparator 823 according to sampled bits B3 and B5, the comparison result Q4 is decided by the comparator 824 according to sampled bits B4 and B5, the comparison result Q5 is decided by the comparator 825 according to sampled bits B6 and B5, the comparison result Q6 is decided by the comparator 826 according to sampled bits B7 and B5, the comparison result Q7 is decided by the comparator 827 according to sampled bits B8 and B5, and the comparison result Q8 is decided by the comparator 828 according to sampled bits B9 and B5. As a person skilled in the art can readily understand details of the circuit design shown in FIG. 9 after reading above paragraphs directed to the circuit design shown in FIG. 5, further description is omitted here for brevity.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

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Citation

Patents Cited in This Cited by
Title Current Assignee Application Date Publication Date
Method and apparatus for determining the errors of a mult-valued data signal that are outside the limits of an eye mask TEKTRONIX, INC. 14 March 2002 18 September 2003
Differential error detection with data stream analysis AGILENT TECHNOLOGIES, INC. 23 December 2002 24 June 2004
Systems and Arrangements for Clock and Data Recovery in Communications GLOBALFOUNDRIES INC. 11 December 2006 12 June 2008
Method and apparatus for test and characterization of semiconductor components RAMBUS INC. 30 January 2004 23 September 2004
Partial response receiver RAMBUS INC. 16 September 2003 14 October 2004
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US10002650 Signal quality detection circuit 1 US10002650 Signal quality detection circuit 2 US10002650 Signal quality detection circuit 3