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Patent Analysis of

Method for operating a serial non-volatile semiconductor memory

Updated Time 12 June 2019

Patent Registration Data

Publication Number

US10002674

Application Number

US15/651157

Application Date

17 July 2017

Publication Date

19 June 2018

Current Assignee

CONTINENTAL AUTOMOTIVE GMBH

Original Assignee (Applicant)

CONTINENTAL AUTOMOTIVE GMBH

International Classification

G11C16/34,G11C7/10

Cooperative Classification

G11C16/3418,G11C7/1006,G11C7/1072,G11C16/10

Inventor

STUHLFELNER, FRIEDBERT

Patent Images

This patent contains figures and images illustrating the invention and its embodiment.

US10002674 Method operating serial 1 US10002674 Method operating serial 2 US10002674 Method operating serial 3
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Abstract

A method for operating a serial non-volatile semiconductor memory in which, for safely writing data into the semiconductor memory, a serial write sequence is applied to an input terminal. The sequence is formed at least with a sequence of command bits, a sequence of address bits and a sequence of data bytes. During the transmission of the bits of the write sequence, a clock signal is present at a clock input and a sufficiently high supply voltage is present at a supply voltage terminal. On occurrence of a supply voltage that is too low, the write sequence and/or the clock signal is subsequently transmitted incorrectly during the transmission of the write sequence and of the clock signal to the semiconductor memory. In the alternative, the write sequence is not transmitted at all.

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Claims

1. A method for operating a serial non-volatile semiconductor memory, the method which comprises: applying a serial write sequence to an input terminal for safely writing data into the semiconductor memory, the write sequence being formed at least with a sequence of command bits, a sequence of address bits and a sequence of data bytes; during a transmission of the bits of the write sequence, applying a clock signal at a clock input; supplying a supply voltage at a supply voltage terminal; and on occasion of a low supply voltage, subsequently transmitting at least one of the write sequence or the clock sequence incorrectly during the transmission of the write sequence and of the clock signal to the semiconductor memory.

2. The method according to claim 1, which comprises, subsequently to transmitting a last data byte of the write sequence, transmitting a sequence of clock signal pulses having a number of at least 1 and at most 7.

3. A method for operating a serial non-volatile semiconductor memory, the method which comprises: applying a serial write sequence to an input terminal for safely writing data into the semiconductor memory, the write sequence being formed at least with a sequence of command bits, a sequence of address bits and a sequence of data bytes; during a transmission of the bits of the write sequence, applying a clock signal at a clock input; supplying a supply voltage at a supply voltage terminal; and if a low voltage is present, not transmitting a write sequence to the semiconductor memory.

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Claim Tree

  • 1
    1. A method for operating a serial non-volatile semiconductor memory, the method which comprises:
    • applying a serial write sequence to an input terminal for safely writing data into the semiconductor memory, the write sequence being formed at least with a sequence of command bits, a sequence of address bits and a sequence of data bytes
    • during a transmission of the bits of the write sequence, applying a clock signal at a clock input
    • supplying a supply voltage at a supply voltage terminal
    • and on occasion of a low supply voltage, subsequently transmitting at least one of the write sequence or the clock sequence incorrectly during the transmission of the write sequence and of the clock signal to the semiconductor memory.
    • 2. The method according to claim 1, which comprises,
      • subsequently to transmitting a last data byte of the write sequence, transmitting a sequence of clock signal pulses having a number of at least 1 and at most 7.
  • 3
    3. A method for operating a serial non-volatile semiconductor memory, the method which comprises:
    • applying a serial write sequence to an input terminal for safely writing data into the semiconductor memory, the write sequence being formed at least with a sequence of command bits, a sequence of address bits and a sequence of data bytes
    • during a transmission of the bits of the write sequence, applying a clock signal at a clock input
    • supplying a supply voltage at a supply voltage terminal
    • and if a low voltage is present, not transmitting a write sequence to the semiconductor memory.
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Description

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority, under 35 U.S.C. § 119, of German patent application DE 10 2016 212 956.2, filed Jul. 15, 2016; the prior application is herewith incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

Field of the Invention

Non-volatile semiconductor memories which, in particular, are designed as EEPROMs or flash EEPROMs are used when data are to remain stored independently of the presence of a supply voltage. In the case of these semiconductor memory types, charge carriers are applied for this purpose to an insulated gate electrode which is at a floating potential (floating gate).

This requires a distinctly higher voltage as the so-called programming voltage than is usually applied from the outside as the supply voltage to the semiconductor chip on which the memory is implemented. The semiconductor memory chip, therefore, has a charge pump which generates the programming voltage from the supply voltage.

If the supply voltage is not high enough, the required programming voltage can frequently no longer be generated, which results in faulty write processes in the semiconductor memory.

In this context, serial EEPROMs and serial flash EEPROMs are semiconductor memories which have a serial data input.

Data corruption due to voltage dips when writing into non-volatile memories is a serious problem in the use of serial EEPROMs and serial flash EEPROMs in motor vehicles. In particular, write accesses frequently occur in the starting and trailing phase of a motor vehicle and it is especially here that the supply voltage situation is critical.

This affects serial SPI (serial peripheral interface), I2C (Inter IC) and microwire EEPROMS or flash EEPROMS with writing times in the millisecond timing pattern. In particular, the situation is also additionally aggravated by new EEPROM features such as error correction.

Data corruption can lead to increased error entries, increased reset rates, increased field failure rates up to expensive recall actions, particularly when sensitive data domains such as security keys are affected.

For writing data into a serial non-volatile semiconductor memory, a microprocessor in most cases transmits, apart from a chip selection signal and a clock signal, a write sequence to the corresponding inputs of the memory chip.

FIG. 1 shows such a signal sequence with the example of an SPI interface via which the corresponding signals are transmitted to the semiconductor chip. In the case of I2C and microwire EEPROMs or flash EEPROMs, this is considered as appropriate, however.

The signal sequence of FIG. 1 shows in the first line a Chip Select Signal S or S\, respectively, by means of which the relevant semiconductor chip is determined as addressee of the information on the data line. In the second line, the clock signal C is shown which supplies clock pulses for the duration of the data transmission on the data line. In the third line, the data signal D itself is shown in the form of a write cycle which in the example shown of an SPI write cycle consists of a command section (instruction) in the form of a sequence of command bits, an address section (16-bit address) in the form of a sequence of address bits and a sequence of data bytes. In this context, an arbitrary number of data bytes can be transmitted but, for each data byte, 8 clock pulses must be transmitted in each case on the clock line C so that the data signal is recognized as being correct.

After the transmission of the sequence and decoding in the State Machine of the EEPROM, a sequence of high-voltage pulses is switched to addressed lines and selected columns of the memory matrix within the semiconductor chip. This takes a number of milliseconds and leads to the deletion and subsequent programming of the addressed memory cells.

A voltage dip during this high-voltage sequence lasting some milliseconds (typically >3 ms) can lead to the corruption of the addressed data or of the addressed page in the memory matrix of the EEPROM.

The problem is additionally aggravated by new EEPROM designs with ECC (integrated error correction). The ECC word length here is typically 4 bytes and thus greater than the write granularity of 1 byte. As a result, data corruption effects can occur in the case of write interruption due to a voltage dip which extends beyond the addressed range. In addition, the write sequence is more complex and longer overall due to the ECC algorithm and thus also more endangered with respect to data corruption under low voltage.

SUMMARY OF THE INVENTION

It is accordingly an object of the invention to provide a method for operating a non-volatile serial semiconductor memory which overcomes the above-mentioned and other disadvantages of the heretofore-known devices and methods of this general type and which provides, specifically, for a method for operating an EEPROM in which a data corruption is prevented when a low voltage is present.

With the foregoing and other objects in view there is provided, in accordance with the invention, a method for operating a serial non-volatile semiconductor memory, the method which comprises:

applying a serial write sequence to an input terminal for safely writing data into the semiconductor memory, the write sequence being formed at least with a sequence of command bits, a sequence of address bits and a sequence of data bytes;

during a transmission of the bits of the write sequence, applying a clock signal at a clock input;

supplying a supply voltage at a sufficient voltage level at a supply voltage terminal; and

on occasion of a low supply voltage, subsequently transmitting at least one of the write sequence or the clock sequence incorrectly during the transmission of the write sequence and of the clock signal to the semiconductor memory.

In other words, in a method for operating a serial non-volatile semiconductor memory in which, for safely writing data into the semiconductor memory, a serial write sequence is applied to an input terminal, which sequence is formed at least with a sequence of command bits, a sequence of address bits and a sequence of data bytes, wherein, during the transmission of the bits of the write sequence, a clock signal is present at a clock input and a sufficiently high supply voltage is required at a supply voltage terminal, in the case of the occurrence of too low a supply voltage, the write sequence and/or the clock signal is subsequently transmitted incorrectly during the transmission of the write sequence and of the clock signal to the semiconductor memory.

The terms “sufficient voltage” or “sufficient supply voltage” as used herein means that a voltage level is present at the supply terminal that enables the device to safely write the entire sequence. The terms “low voltage” or “low supply voltage” as used herein means that the voltage level is insufficient and that, on continued writing, data corruption would/might occur.

When there is information that the supply voltage is too low, that is to say a low voltage is present, it can thus be achieved by manipulation of the write command that the State Machine of the EEPROM decodes the write command as invalid and aborts. This can happen in various ways.

In an advantageous development of the invention, this manipulation occurs by adding 1 to 7 additional SPI clock pulses before the deactivation of the Chip Select Signal.

This ensures that a write sequence which is currently transmitted is aborted at the earliest possible time after the activation of a low-voltage signal.

A low-voltage signal for the supply voltage is present in current control devices for motor vehicles typically in the form of an interrupt for initiating a housekeeping phase in the microcontroller.

By means of such a manipulation according to the invention of the signals or of a signal of the write process, a write process already initiated can ultimately be prevented in a simple but effective manner although the set of commands of EEPROMs does not have an explicit abort command.

With the above and other objects in view there is also provided, in accordance with the invention, a method for operating a serial non-volatile semiconductor memory, the method which comprises:

applying a serial write sequence to an input terminal for safely writing data into the semiconductor memory, the write sequence being formed at least with a sequence of command bits, a sequence of address bits and a sequence of data bytes;

during a transmission of the bits of the write sequence, applying a clock signal at a clock input;

supplying a supply voltage at a supply voltage terminal; and

if a low voltage is present, not transmitting a write sequence to the semiconductor memory.

In other words, if no write process has yet been initiated, a data corruption can be prevented in another embodiment of the invention in that, in the case of too low a supply voltage being present, there is no transmission of a write sequence to the semiconductor memory.

The signal which indicates a low voltage is thus used for preventing the beginning of a write process.

Other features which are considered as characteristic for the invention are set forth in the appended claims.

Although the invention is illustrated and described herein as embodied in a method for operating a serial non-volatile semiconductor memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.

The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 shows the course of write signals with an EEPROM having an SPI interface according to the prior art; and

FIG. 2 shows the course of a Chip Select Signal and the course according to the invention of a clock signal.

DETAILED DESCRIPTION OF THE INVENTION

Referring now once more to the figures of the drawing in detail and particularly to FIG. 2 thereof, the signal shape shown in the lower part of the figure shows clock pulses of a clock signal by means of which the bits of the command, address and data signals are clocked into an EEPROM. During a valid Chip Select Signal as shown by the signal shape shown in the upper part of the figure, clock signals for the data bytes have to comprise eight clock pulses or a multiple thereof, however, in order to be recognized as valid by the State Machine of the EEPROM.

In the example shown, finally, two clock pulses are transmitted again, whereupon the State Machine discards the entire write sequence as invalid and does not initiate any programming pulses.

By means of this manipulation of the clock signal, programming of the data bytes can thus be prevented effectively even with a write sequence which has already started, when a low voltage is present.

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Patent Valuation

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15.0/100 Score

Market Attractiveness

It shows from an IP point of view how many competitors are active and innovations are made in the different technical fields of the company. On a company level, the market attractiveness is often also an indicator of how diversified a company is. Here we look into the commercial relevance of the market.

42.0/100 Score

Market Coverage

It shows the sizes of the market that is covered with the IP and in how many countries the IP guarantees protection. It reflects a market size that is potentially addressable with the invented technology/formulation with a legal protection which also includes a freedom to operate. Here we look into the size of the impacted market.

69.4/100 Score

Technology Quality

It shows the degree of innovation that can be derived from a company’s IP. Here we look into ease of detection, ability to design around and significance of the patented feature to the product/service.

72.0/100 Score

Assignee Score

It takes the R&D behavior of the company itself into account that results in IP. During the invention phase, larger companies are considered to assign a higher R&D budget on a certain technology field, these companies have a better influence on their market, on what is marketable and what might lead to a standard.

14.0/100 Score

Legal Score

It shows the legal strength of IP in terms of its degree of protecting effect. Here we look into claim scope, claim breadth, claim quality, stability and priority.

Citation

Patents Cited in This Cited by
Title Current Assignee Application Date Publication Date
Device and method for repeatedly forming a preselected arrangement of conveyed articles GOLDCO INDUSTRIES, INC. A CORP. OF COLORADO 22 July 1992 21 December 1993
Semiconductor integrated circuit device, manufacturing method thereof, and driving method for the same SEIKO INSTRUMENTS, INC. 22 March 1995 11 August 1998
Fuse data storage system using core memory ATMEL CORPORATION 02 August 2004 02 February 2006
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