Great research starts with great data.

Learn More
More >
Patent Analysis of

Prevention of charging damage in full-depletion devices

Updated Time 12 June 2019

Patent Registration Data

Publication Number

US10002800

Application Number

US15/154525

Application Date

13 May 2016

Publication Date

19 June 2018

Current Assignee

INTERNATIONAL BUSINESS MACHINES CORPORATION

Original Assignee (Applicant)

INTERNATIONAL BUSINESS MACHINES CORPORATION

International Classification

H01L21/66,H01L23/60,H01L27/02,H01L21/84,H01L23/66

Cooperative Classification

H01L23/60,H01L22/20,H01L27/0207,H01L23/66,H01L21/84

Inventor

HOOK, TERENCE B.

Patent Images

This patent contains figures and images illustrating the invention and its embodiment.

US10002800 Prevention charging damage 1 US10002800 Prevention charging damage 2 US10002800 Prevention charging damage 3
See all images <>

Abstract

Methods and systems method for checking a semiconductor device for compliance with a rule include determining one or more device type categories to which a fully depleted semiconductor on insulator (FDSOI) device in a chip layout belongs based on which, if any, of a gate, a source/drain region, and a well of the FDSOI device are connected to each other or to a substrate. It is determined whether the FDSOI device complies with a first design rule that considers antenna area connected to the gate and the source/drain region of the FDSOI device. It is determined whether the FDSOI device complies with a second design rule that considers antenna area connected to the well and the source/drain region of the FDSOI device. The chip layout is modified, if the FDSOI devices fails to comply with the first and second design rules, to bring the non-compliant FDSOI device into compliance.

Read more

Claims

1. A method for checking a semiconductor device for compliance with a rule, comprising: determining one or more device type categories to which a fully depleted semiconductor on insulator (FDSOI) device in a chip layout belongs based on which of a gate, a source/drain region, and a well of the FDSOI device are connected to each other or to a substrate; determining whether the FDSOI device complies with a first design rule that considers antenna area connected to the gate and the source/drain region of the FDSOI device; determining whether the FDSOI device complies with a second design rule that considers antenna area connected to the well and the source/drain region of the FDSOI device; and modifying the chip layout, if the FDSOI devices fails to comply with the first and second design rules, to bring the non-compliant FDSOI device into compliance.

2. The method of claim 1, further comprising repeating said steps of checking the FDSOI device for compliance with the first design rule and the second design rule and modifying the chip layout until every FDSOI device in the chip layout complies with the first and second design rules.

3. The method of claim 1, further comprising fabricating a chip based on the chip layout after determining every FDSOI device in the chip layout complies with the first and second design rules.

4. The method of claim 1, wherein the FDSOI device is determined to be in a first category if neither the gate nor the source/drain region is electrically connected to the well or the substrate.

5. The method of claim 4, wherein the first design rule compares a combined antenna area electrically connected to the gate and the source/drain region to an area of the gate times a safe charging current factor for a gate dielectric.

6. The method of claim 4, wherein the second design rule compares a combined antenna area electrically connected to the well and to the source/drain region to an area of the gate times a safe charging current factor for a buried dielectric.

7. The method of claim 1, wherein the FDSOI device is determined to be in a second category if the gate is electrically connected to the well or the substrate.

8. The method of claim 7, wherein the first design rule compares an antenna area electrically connected to the source/drain region to an area of the gate times a safe charging current factor for a gate dielectric divided by a factor of ten.

9. The method of claim 1, wherein the FDSOI device is determined to be in a third category if the source/drain region is electrically connected to the well or the substrate.

10. The method of claim 9, wherein the first design rule compares an antenna area electrically connected to the gate to an area of the gate times a safe charging current factor for a gate dielectric divided by a factor of ten.

11. The method of claim 1, wherein the FDSOI device is determined to be in a fourth category if the well is electrically connected to a substrate.

12. The method of claim 11, wherein the second design rule compares an antenna area electrically connected to the source/drain region to an area of the source/drain region times a safe charging current factor for a buried dielectric divided by a factor of ten.

13. The method of claim 1, wherein the FDSOI device is determined to be in a fifth category if the source/drain region is electrically connected to the well or the substrate.

14. The method of claim 13, wherein the second design rule compares an antenna area electrically connected to the well to an area of the source/drain region times a safe charging current factor for a buried dielectric divided by a factor of ten.

15. A method for checking a semiconductor device for compliance with a rule, comprising: determining one or more device type categories to which a fully depleted semiconductor on insulator (FDSOI) device in a chip layout belongs based on which of a gate, a source/drain region, and a well of the FDSOI device are connected to each other or to a substrate; determining whether the FDSOI device complies with a first design rule that considers antenna area connected to the gate and the source/drain region of the FDSOI device, wherein the first design rule compares an antenna area electrically connected to the FDSOI device to an area of the gate times a safe charging current factor for a gate dielectric; determining whether the FDSOI device complies with a second design rule that considers antenna area connected to the well and the source/drain region of the FDSOI device, wherein the second design rule compares an antenna area electrically connected to the FDSOI device to an area of the gate times a safe charging current factor for a buried dielectric; modifying the chip layout, if the FDSOI devices fails to comply with the first and second design rules, to bring the non-compliant FDSOI device into compliance; and repeating the determination of whether the FDSOI complies with the first design rule and the second design rule and the modification of the chip layout until every FDSOI device in the chip layout complies with the first and second design rules.

Read more

Claim Tree

  • 1
    1. A method for checking a semiconductor device for compliance with a rule, comprising:
    • determining one or more device type categories to which a fully depleted semiconductor on insulator (FDSOI) device in a chip layout belongs based on which of a gate, a source/drain region, and a well of the FDSOI device are connected to each other or to a substrate
    • determining whether the FDSOI device complies with a first design rule that considers antenna area connected to the gate and the source/drain region of the FDSOI device
    • determining whether the FDSOI device complies with a second design rule that considers antenna area connected to the well and the source/drain region of the FDSOI device
    • and modifying the chip layout, if the FDSOI devices fails to comply with the first and second design rules, to bring the non-compliant FDSOI device into compliance.
    • 2. The method of claim 1, further comprising
      • repeating said steps of checking the FDSOI device for compliance with the first design rule and the second design rule and modifying the chip layout until every FDSOI device in the chip layout complies with the first and second design rules.
    • 3. The method of claim 1, further comprising
      • fabricating a chip based on the chip layout after determining every FDSOI device in the chip layout complies with the first and second design rules.
    • 4. The method of claim 1, wherein
      • the FDSOI device is determined to be in a first category if neither the gate nor the source/drain region is electrically connected to the well or the substrate.
    • 7. The method of claim 1, wherein
      • the FDSOI device is determined to be in a second category if the gate is electrically connected to the well or the substrate.
    • 9. The method of claim 1, wherein
      • the FDSOI device is determined to be in a third category if the source/drain region is electrically connected to the well or the substrate.
    • 11. The method of claim 1, wherein
      • the FDSOI device is determined to be in a fourth category if the well is electrically connected to a substrate.
    • 13. The method of claim 1, wherein
      • the FDSOI device is determined to be in a fifth category if the source/drain region is electrically connected to the well or the substrate.
  • 15
    15. A method for checking a semiconductor device for compliance with a rule, comprising:
    • determining one or more device type categories to which a fully depleted semiconductor on insulator (FDSOI) device in a chip layout belongs based on which of a gate, a source/drain region, and a well of the FDSOI device are connected to each other or to a substrate
    • determining whether the FDSOI device complies with a first design rule that considers antenna area connected to the gate and the source/drain region of the FDSOI device, wherein the first design rule compares an antenna area electrically connected to the FDSOI device to an area of the gate times a safe charging current factor for a gate dielectric
    • determining whether the FDSOI device complies with a second design rule that considers antenna area connected to the well and the source/drain region of the FDSOI device, wherein the second design rule compares an antenna area electrically connected to the FDSOI device to an area of the gate times a safe charging current factor for a buried dielectric
    • modifying the chip layout, if the FDSOI devices fails to comply with the first and second design rules, to bring the non-compliant FDSOI device into compliance
    • and repeating the determination of whether the FDSOI complies with the first design rule and the second design rule and the modification of the chip layout until every FDSOI device in the chip layout complies with the first and second design rules.
See all independent claims <>

Description

BACKGROUND

Technical Field

The present invention generally relates to semiconductor device design and, more particularly, to designing semiconductor devices to prevent charging damage during fabrication.

Description of the Related Art

Plasma induced gate oxide damage is caused during the fabrication of an integrated circuit. Various fabrication processes, in particular those that involve plasmas, can cause a charge buildup on circuit components. This charge buildup results in a voltage being applied to the circuit components that is in excess of the tolerances of those devices. In one specific example, the buildup of charge can cause a breakdown in the gate dielectric of a transistor, thereby damaging the transistor.

Charge builds up in particular on conductors. As the area of conductors increases, for example from component interconnects, the collected charge increases and the higher the likelihood of a breakdown. Conversely, the greater the gate area, for example from multiple devices connected to the interconnect, the more the charge buildup will be spread out and the lower the likelihood of a breakdown.

To address this problem, circuit layouts are checked for compliance with design rules that establish safe margins during fabrication. These rules are referred to as “antenna rules,” and a violation of such rules is an “antenna violation.” However, in fully depleted semiconductor-on-insulator (SOI) technologies, the channel region and buried dielectric of a device are made particularly thin. While this provides certain advantages in tuning the electrical characteristics of the device (e.g., by applying a voltage to a well underneath the buried dielectric), the use of fully depleted SOI structures creates the risk of plasma induced damage to the buried dielectric as well.

SUMMARY

A method for checking a semiconductor device for compliance with a rule includes determining one or more device type categories to which a fully depleted semiconductor on insulator (FDSOI) device in a chip layout belongs based on which, if any, of a gate, a source/drain region, and a well of the FDSOI device are connected to each other or to a substrate. It is determined whether the FDSOI device complies with a first design rule that considers antenna area connected to the gate and the source/drain region of the FDSOI device. It is determined whether the FDSOI device complies with a second design rule that considers antenna area connected to the well and the source/drain region of the FDSOI device. The chip layout is modified, if the FDSOI devices fails to comply with the first and second design rules, to bring the non-compliant FDSOI device into compliance.

A method for checking a semiconductor device for compliance with a rule includes determining one or more device type categories to which a fully depleted semiconductor on insulator (FDSOI) device in a chip layout belongs based on which, if any, of a gate, a source/drain region, and a well of the FDSOI device are connected to each other or to a substrate. It is determined whether the FDSOI device complies with a first design rule that considers antenna area connected to the gate and the source/drain region of the FDSOI device. The first design rule compares an antenna area electrically connected to the FDSOI device to an area of the gate times a safe charging current factor for a gate dielectric. It is determined whether the FDSOI device complies with a second design rule that considers antenna area connected to the well and the source/drain region of the FDSOI device. The second design rule compares an antenna area electrically connected to the FDSOI device to an area of the gate times a safe charging current factor for a buried dielectric. The chip layout is modified, if the FDSOI devices fails to comply with the first and second design rules, to bring the non-compliant FDSOI device into compliance. The determination of whether the FDSOI complies with the first design rule and the second design rule and the modification of the chip layout are repeated until every FDSOI device in the chip layout complies with the first and second design rules.

A system for checking a semiconductor device for compliance with a rule includes a compliance module comprising a processor configured to determine one or more device type categories to which a fully depleted semiconductor on insulator (FDSOI) device in a chip layout belongs based on which, if any, of a gate, a source/drain region, and a well of the FDSOI device are connected to each other or to a substrate; to determine whether the FDSOI device complies with a first design rule that considers antenna area connected to the gate and the source/drain region of the FDSOI device; and to determine whether the FDSOI device complies with a second design rule that considers antenna area connected to the well and the source/drain region of the FDSOI device. A layout module is configured to modify the chip layout, if the FDSOI devices fails to comply with the first and second design rules, to bring the non-compliant FDSOI device into compliance.

These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The disclosure will provide details in the following description of preferred embodiments with reference to the following figures wherein:

FIG. 1 is a diagram of a fully depleted semiconductor on insulator (FDSOI) device in accordance with the present principles;

FIG. 2 is a block/flow diagram of a method of checking a gate-system and a well-system of an FDSOI device for compliance with antenna rules in accordance with the present principles;

FIG. 3 is a block diagram of a system for checking a gate-system and a well-system of an FDSOI device for compliance with antenna rules in accordance with the present principles; and

FIG. 4 is a block diagram of a processing system in accordance with the present principles.

DETAILED DESCRIPTION

Embodiments of the present invention provide antenna rule compliance checking for semiconductor devices that use fully depleted semiconductor-on-insulator (FDSOI) technologies. In addition to checking antenna rules between the gate and the channel region, to prevent damage to a gate dielectric, the present embodiments check antenna rules between the channel region and an underlying well to prevent damage to a buried dielectric.

The term FDSOI as used herein refers to a semiconductor device that has a narrow semiconductor region forming the channel between a gate dielectric and a buried dielectric. In one exemplary embodiment, the narrow semiconductor region may have a thickness of about 7 nm. As a result, the field exerted by the gate of a transistor can fully deplete the channel region of charge carriers (i.e., electrons in an n-type region and “holes” in a p-type region).

Referring now to FIG. 1, an exemplary FDSOI device 100 is shown. A thin semiconductor layer 106 is on a buried insulator layer 102. In one specific embodiment, the buried insulator layer 102 may be an oxide such as silicon dioxide, and the semiconductor layer 106 may be a silicon-containing material. The thin semiconductor layer 106 may have an exemplary thickness of about 7 nm, while the buried insulator layer 102 may have an exemplary thickness of about 25 nm. Illustrative examples of silicon-containing materials suitable for the semiconductor substrate 106 include, but are not limited to, silicon, silicon germanium, silicon germanium carbide, silicon carbide, polysilicon, epitaxial silicon, amorphous silicon, and multi-layers thereof. Although silicon is the predominantly used semiconductor material in wafer fabrication, alternative semiconductor materials can be employed, such as, but not limited to, germanium, gallium arsenide, gallium nitride, cadmium telluride and zinc sellenide.

Underneath the buried insulator layer 102, or formed therein, is one or more wells 104. In one exemplary embodiment, the well 104 may be an n-doped semiconductor region. In an alternative embodiment, the well 104 may be a triple well that includes a p-doped region within an n-doped region, surrounded by an intrinsic semiconductor substrate. As used herein, “p-type” refers to the addition of impurities to an intrinsic semiconductor that creates deficiencies of valence electrons. In a silicon-containing substrate, examples of p-type dopants, i.e., impurities, include but are not limited to: boron, aluminum, gallium and indium. As used herein, “n-type” refers to the addition of impurities that contributes free electrons to an intrinsic semiconductor In a silicon containing substrate examples of n-type dopants, i.e., impurities, include but are not limited to antimony, arsenic and phosphorous.

The thin semiconductor layer 106 forms the channel region of the device 100. Source and drain regions 108 may be formed directly on the thin semiconductor layer 106 and may be appropriately doped. The source and drain regions 108 may be formed from the same material as the thin semiconductor layer 106 and later doped by implantation or, alternatively, may be epitaxially grown and doped in situ. A gate 110 is formed over the channel region of the thin semiconductor layer 106, with spacers 112 to electrically insulate the gate 110 from the source and drain regions 108. A gate dielectric layer 114 insulates the channel region of the thin semiconductor layer 106 from the gate 110.

It should be understood that the FDSOI device 100 may be considered alone or in tandem with a large set of other FDSOI devices and other types of device on a single chip. Multiple FDSOI devices 100 may be connected to a single net on the design layout of the chip and so may be connected to one another via, e.g., one another's gates 110, source/drain regions 108, and wells 104. Such a chip may be fabricated according to any appropriate semiconductor device fabrication process at any appropriate scale.

It is to be understood that the present invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials and process features and steps may be varied within the scope of the present invention.

It will also be understood that when an element such as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

The present embodiments may include a design for an integrated circuit chip, which may be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer may transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.

Methods as described herein may be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

During fabrication, some processes tend to cause the accumulation of stray charge on conducting circuit components. For example, contacts and interconnects can act like antennas that accumulate the charge. When the accumulated charge grows too large to be dissipated safely, an insulating layer (such as the gate dielectric 114 or the buried dielectric layer 102) can break down, damaging the device.

To account for this, design rules are used to compare the amount of antenna area to an amount of dissipating area (e.g., gate area). However, the presence of well 104 complicates matters, as there are multiple avenues for breakdown and, furthermore, the well and the gate interact with one another to potentially increase the likelihood of breakdown in certain conditions. As a result, the FDSOI device 100 can be interpreted as two separate systems: a gate-system that characterizes the danger of charging damage to the gate dielectric114 between the gate 110 and the thin semiconductor layer 106, and a well-system that characterizes the danger of charging damage to the buried dielectric 102 between the thin semiconductor layer 106 and the well 104.

In particular, the gate 110, the source/drain regions 108 (and thus also the thin semiconductor layer 106), and the well 104 may each have respective antennas (i.e., networks of conductive material) connected to them. The device 100 can be modeled as two separate transistor structures for antenna rule compliance—with a first rule checking for compliance between the gate and the source/drain potentials and a second rule checking for compliance between the well and the source/drain potentials.

When assessing the gate-system for compliance, the worst-case scenario is if the well 104 is effectively grounded to the substrate. In some embodiments the well 104 may accumulate a charge of its own, but such a charge would serve to diminish the danger of the charge buildup on the gate 110. Because checking for antenna rule compliance is intended to ensure safe processes, the worst-case scenario is assumed. In this case, there are three possibilities: both the gate 110 and the source/drain regions 108 may float relative to the well 104, the gate 110 may be tied to the well 104, or the source/drain regions 108 may be tied to the well 104 (e.g., through one or more interconnects or devices). If both nodes are floating, the likelihood of damage is significantly smaller than if one node is effectively grounded, as balanced charge buildups will produce a smaller potential difference than if one node is kept at a ground potential.

When assessing the well-system for compliance, the gate 110 is ignored. If the well 104 has a floating potential (e.g., in the case of an n-well or triple well), then the antenna size of both the well 104 and the source/drain regions 108 should be limited. If the well 104 is grounded to the substrate, then the antenna on the source/drain regions 108 are limited. As with the gate-system, if both nodes are floating, the buried insulator layer 102 is less likely to be damaged, because the potential difference between the nodes will be smaller than if one node is grounded.

It should be noted that, if the source/drain regions 108 are electrically connected to the well 104 (i.e., if they are on the same net) then there is no need to test for rule compliance for the well-system, as there is no likelihood of damage to the dielectric between them. Similarly, if the gate 110 and the source/drain regions 108 are electrically connected to one another, compliance checking for the gate-system may be skipped as well.

When checking for antenna rule compliance, the device 100 is determined to fall into one or more of the categories described above and an appropriate set of antenna rules is applied. In a first example, where neither the gate 110 nor the source/drain regions 108 are electrically connected to the well 104 or the substrate, then a first exemplary antenna rule is to ensure that

11/Vg+11/Vsd<αAg,

where Vg is the antenna area connected to gate 110, Vsd is the antenna area connected to the source/drain regions 108, Ag is the area of gate 110, and α is a technology-specific factor related to the ability of the gate dielectric 114 to harmlessly support charging current.

In a second example, where neither the source/drain 108 nor the well 104 are electrically connected to the substrate, then a second exemplary antenna rule is to ensure that

11/Vwell+11/Vsd<βAg,

where Vwell is the antenna area connected to the well 104 and β is a technology-specific factor related to the ability of the buried dielectric 102 to harmlessly support charging current.

In a third example, if the gate 110 is electrically connected to the well 104 or the substrate, then a third exemplary antenna rule is to ensure that

Vsd<αAg10.

Because the gate 110 is connected to the well 104 or the substrate and, in the worst case scenario, is assumed therefore to be grounded, the tolerance to charge buildup is much lower (in this specific example by a factor of ten).

In a fourth example, if the source/drain regions 106 are electrically connected to the well 104 or the substrate, then a fourth exemplary antenna rule is to ensure that

Vg<αAg10.

As with the scenario described above, the fact that one node is connected to the well 104 or the substrate (and must therefore be assumed to be at a ground potential), the tolerance for charge buildup is decreased.

In a fifth example, if the well 104 is electrically connected to the substrate, then a fifth exemplary antenna rule is to ensure that

Vsd<βAg10.

In this case, the antenna rule is checking for compliance between the well 104 and the source/drain region 108, ignoring the gate 110.

In a sixth example, if the source/drain regions 108 are electrically connected to the substrate, the a sixth exemplary antenna rule is to ensure that

Vwell<βAg10.

Referring now to FIG. 2, a method of preventing charging damage is shown. Block 202 identifies the FDSOI devices 100 on a design layout that have an underlying well 104. Block 204 then determines which category of device each FDSOI device 100 belongs to, based on whether there are connections between the gate 110, the source/drain regions 108, and the well 104, and whether the well 104 is electrically to the substrate or ground.

Block 206 determines an antenna area that is attached to the gate 110, the source/drain regions 108, and the well 104 of each FDSOI device 100. The antenna area may include metal interconnects and contacts and may also include other conductive structures. Block 208 then applies an antenna rule for the gate-system of each FDSOI device 100, determining whether there is a likelihood of damage at the gate dielectric 114 due to charge buildup at the gate 110 or the source/drain regions 108. As noted above, the antenna rule to be applied by block 208 depends on which category of device the FDSOI device 100 is determined to be. Block 210 similarly applies an antenna rule for the well-system of each FDSOI device 100, determining whether there is a likelihood of damage at the buried dielectric 102 due to charge buildup at the well 104 or the source/drain regions 108. Again, the specific antenna rule to be applied depends on which category of device the FDSOI device 100 belongs to.

Block 212 determines whether each FDSOI device 100 complies with its respective antenna rules. If not, block 214 modifies the layout design. Block 214 may be performed by a human being using a computer-assisted design tool or, alternatively, modifications to the design layout may be made automatically to, e.g., decrease the amount of antenna area for a particular node or to increase the safe discharge area. Processing returns to block 206 and antenna checks are repeated until every FDSOI device 100 complies. Once all FDSOI devices 100 have been checked and all compliance violations have been resolved, block 216 fabricates the chip.

The present invention may be a system, a method, and/or a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention.

The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.

Computer readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.

Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions.

These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.

Reference in the specification to “one embodiment” or “an embodiment” of the present principles, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present principles. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment.

It is to be appreciated that the use of any of the following “/”, “and/or”, and “at least one of”, for example, in the cases of “A/B”, “A and/or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed.

Referring now to FIG. 3, a system 300 for ensuring compliance of an FDSOI device with one or more rules is shown. The system 300 includes a hardware processor 302 and a memory 304. In addition, the system 300 may include one or more functional modules that are implemented as software, stored in memory 304 and executed by processor 302. Alternatively, the functional modules may be implemented as one or more discrete hardware components using, e.g., application specific integrated chips or field programmable gate arrays.

For example, compliance module 306 analyzes a design layout 308 that is stored in memory 304 and determines whether the design layout complies with one or more antenna rules. To accomplish this, the compliance module determines the area of nets in the design layout 308 connected to respective nodes in each FDSOI device 100 and checks each FDSOI device 100 against at least two antenna compliance rules—one for the gate-system and one for the well-system in FDSOI device 100.

If at least one FDSOI device 100 in the design layout 308 fails to comply with the antenna rules, layout editing module 310 is used to make modifications to the design layout 308 to bring the FDSOI devices 100 into compliance. This may be performed automatically or with guidance from a human designer. Once the compliance module 306 confirms that all FDSOI devices 100 comply with the antenna rules, block 312 controls fabrication of the chip.

Referring now to FIG. 4, an exemplary processing system 400 is shown which may represent the system 300 for ensuring compliance of an FDSOI device with one or more rules. The processing system 400 includes at least one processor (CPU) 404 operatively coupled to other components via a system bus 402. A cache 406, a Read Only Memory (ROM) 408, a Random Access Memory (RAM) 410, an input/output (I/O) adapter 420, a sound adapter 430, a network adapter 440, a user interface adapter 450, and a display adapter 460, are operatively coupled to the system bus 402.

A first storage device 422 and a second storage device 424 are operatively coupled to system bus 402 by the I/O adapter 420. The storage devices 422 and 424 can be any of a disk storage device (e.g., a magnetic or optical disk storage device), a solid state magnetic device, and so forth. The storage devices 422 and 424 can be the same type of storage device or different types of storage devices.

A speaker 432 is operatively coupled to system bus 402 by the sound adapter 430. A transceiver 442 is operatively coupled to system bus 402 by network adapter 440. A display device 462 is operatively coupled to system bus 402 by display adapter 460.

A first user input device 452, a second user input device 454, and a third user input device 456 are operatively coupled to system bus 402 by user interface adapter 450. The user input devices 452, 454, and 456 can be any of a keyboard, a mouse, a keypad, an image capture device, a motion sensing device, a microphone, a device incorporating the functionality of at least two of the preceding devices, and so forth. Of course, other types of input devices can also be used, while maintaining the spirit of the present principles. The user input devices 452, 454, and 456 can be the same type of user input device or different types of user input devices. The user input devices 452, 454, and 456 are used to input and output information to and from system 400.

Of course, the processing system 400 may also include other elements (not shown), as readily contemplated by one of skill in the art, as well as omit certain elements. For example, various other input devices and/or output devices can be included in processing system 400, depending upon the particular implementation of the same, as readily understood by one of ordinary skill in the art. For example, various types of wireless and/or wired input and/or output devices can be used. Moreover, additional processors, controllers, memories, and so forth, in various configurations can also be utilized as readily appreciated by one of ordinary skill in the art. These and other variations of the processing system 400 are readily contemplated by one of ordinary skill in the art given the teachings of the present principles provided herein.

Having described preferred embodiments of a system and method (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.

Read more
PatSnap Solutions

Great research starts with great data.

Use the most comprehensive innovation intelligence platform to maximise ROI on research.

Learn More

Patent Valuation

$

Reveal the value <>

31.0/100 Score

Market Attractiveness

It shows from an IP point of view how many competitors are active and innovations are made in the different technical fields of the company. On a company level, the market attractiveness is often also an indicator of how diversified a company is. Here we look into the commercial relevance of the market.

65.0/100 Score

Market Coverage

It shows the sizes of the market that is covered with the IP and in how many countries the IP guarantees protection. It reflects a market size that is potentially addressable with the invented technology/formulation with a legal protection which also includes a freedom to operate. Here we look into the size of the impacted market.

72.75/100 Score

Technology Quality

It shows the degree of innovation that can be derived from a company’s IP. Here we look into ease of detection, ability to design around and significance of the patented feature to the product/service.

81.0/100 Score

Assignee Score

It takes the R&D behavior of the company itself into account that results in IP. During the invention phase, larger companies are considered to assign a higher R&D budget on a certain technology field, these companies have a better influence on their market, on what is marketable and what might lead to a standard.

17.0/100 Score

Legal Score

It shows the legal strength of IP in terms of its degree of protecting effect. Here we look into claim scope, claim breadth, claim quality, stability and priority.

Citation

Patents Cited in This Cited by
Title Current Assignee Application Date Publication Date
Silicon-on-insulator CMOS integrated circuit with multiple threshold voltages and a method for designing the same STMICROELECTRONICS (CROLLES 2) 01 August 2012 09 July 2013
Method of providing protection against charging damage in hybrid orientation transistors GLOBALFOUNDRIES INC. 19 December 2007 01 February 2011
Integrated circuit structures for preventing charging damage GLOBALFOUNDRIES INC. 09 January 2006 30 December 2008
Determining allowance antenna area as function of total gate insulator area for SOI technology GLOBALFOUNDRIES INC. 13 December 2007 04 May 2010
Method for generating a topography of an FDSOI integrated circuit STMICROELECTRONICS SA 13 December 2013 28 July 2015
See full citation <>

More Patents & Intellectual Property

PatSnap Solutions

PatSnap solutions are used by R&D teams, legal and IP professionals, those in business intelligence and strategic planning roles and by research staff at academic institutions globally.

PatSnap Solutions
Search & Analyze
The widest range of IP search tools makes getting the right answers and asking the right questions easier than ever. One click analysis extracts meaningful information on competitors and technology trends from IP data.
Business Intelligence
Gain powerful insights into future technology changes, market shifts and competitor strategies.
Workflow
Manage IP-related processes across multiple teams and departments with integrated collaboration and workflow tools.
Contact Sales
Clsoe
US10002800 Prevention charging damage 1 US10002800 Prevention charging damage 2 US10002800 Prevention charging damage 3