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Patent Analysis of

Apparatuses and methods to enhance passivation and ILD reliability

Updated Time 12 June 2019

Patent Registration Data

Publication Number

US10002814

Application Number

US14/195422

Application Date

03 March 2014

Publication Date

19 June 2018

Current Assignee

INTEL CORPORATION

Original Assignee (Applicant)

HARRIES, RICHARD J.,RANGARAJ, SUDARASHAN V.,SANKMAN, ROBERT L.

International Classification

H01L23/31,H01L23/00

Cooperative Classification

H01L23/3128,H01L24/03,H01L24/05,H01L24/11,H01L24/13

Inventor

HARRIES, RICHARD J.,RANGARAJ, SUDARASHAN V.,SANKMAN, ROBERT L.

Patent Images

This patent contains figures and images illustrating the invention and its embodiment.

US10002814 Apparatuses enhance 1 US10002814 Apparatuses enhance 2 US10002814 Apparatuses enhance 3
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Abstract

Some embodiments of the present invention include apparatuses and methods relating to processing and packaging microelectronic devices that reduce stresses on and limit or eliminate crack propagation in the devices.

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Claims

1. An apparatus comprising: a substrate including a bond pad; a first passivation layer on the substrate, wherein the first passivation layer exposes at least a portion of the bond pad; a barrier metal on the bond pad; a bump attached to the barrier metal such that an undercut is formed between the bump and the first passivation layer; a first underfill layer on the first passivation layer substantially filling a region adjacent to the bump, the first underfill layer completely covering the first passivation layer, wherein the first underfill layer exposes a portion of the bump, wherein the first underfill layer fills the undercut and the first underfill is non-conductive, and wherein the underfill layer has a height less than a height of the solder bump; a second substrate directly soldered to the bump to form a soldered bump connection; and a second underfill surrounding the soldered bump connection, wherein the second underfill is non-conductive.

2. The apparatus of claim 1, wherein the first underfill layer comprises a spark passivation layer.

3. The apparatus of claim 1, wherein the height of the bump is substantially level with the height of the first underfill layer.

4. The apparatus of claim 1, wherein the bump includes copper.

5. An apparatus comprising: a surface including a bond pad; a first passivation layer on the surface, wherein the first passivation layer exposes at least a portion of the bond pad; a barrier metal on the bond pad; a bump attached to the barrier metal such that an undercut is formed between the bump and the first passivation layer; a first underfill layer on the first passivation layer and adjacent to the bump, the first underfill layer completely covering the first passivation layer, wherein the first underfill layer exposes a portion of the bump, wherein the first underfill layer fills the undercut and the first underfill is non-conductive, and wherein the underfill layer has a height less than a height of the solder bump; a second surface directly soldered to the bump to form a soldered bump connection; and a second underfill surrounding the soldered bump connection, wherein the second underfill is non-conductive.

6. The apparatus of claim 5, wherein the surface is on a package substrate.

7. The apparatus of claim 5, wherein the surface is on a microelectronic device.

8. The apparatus of claim 5, wherein the second underfill is epoxy.

9. The apparatus of claim 5, wherein the second underfill is a capillary underfill epoxy.

10. An apparatus comprising: a microelectronic device surface including a bond pad; a first passivation layer on the surface, wherein the first passivation layer exposes at least a portion of the bond pad; a barrier metal on the bond pad; a solder bump attached to the barrier metal such that an undercut is formed between the solder bump and the first passivation layer;a first underfill layer on the first passivation layer and adjacent to the solder bump, the first underfill layer completely covering the first passivation layer, wherein: the first underfill layer exposes a portion of the solder bump, the first underfill layer fills the undercut, the first underfill is non-conductive, and the first underfill layer has a height less than a height of the solder bump; a substrate, directly soldered to the solder bump to form a soldered connection; and a second underfill surrounding the soldered connection, wherein the second underfill is nonconductive.

11. The apparatus of claim 10, wherein the second underfill is a capillary underfill epoxy.

12. The apparatus of claim 10, wherein the first underfill layer comprises epoxy.

13. The apparatus of claim 10, wherein the first underfill layer comprises a spark passivation layer.

14. The apparatus of claim 10, wherein the bump includes copper.

15. The apparatus of claim 10, wherein the first underfill layer has a thickness in the range of 1 to 15 microns.

16. The apparatus of claim 10, wherein the substrate is soldered to the solder bump using a lead-free solder.

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Claim Tree

  • 1
    1. An apparatus comprising:
    • a substrate including a bond pad
    • a first passivation layer on the substrate, wherein the first passivation layer exposes at least a portion of the bond pad
    • a barrier metal on the bond pad
    • a bump attached to the barrier metal such that an undercut is formed between the bump and the first passivation layer
    • a first underfill layer on the first passivation layer substantially filling a region adjacent to the bump, the first underfill layer completely covering the first passivation layer, wherein the first underfill layer exposes a portion of the bump, wherein the first underfill layer fills the undercut and the first underfill is non-conductive, and wherein the underfill layer has a height less than a height of the solder bump
    • a second substrate directly soldered to the bump to form a soldered bump connection
    • and a second underfill surrounding the soldered bump connection, wherein the second underfill is non-conductive.
    • 2. The apparatus of claim 1, wherein
      • the first underfill layer comprises
    • 3. The apparatus of claim 1, wherein
      • the height of the bump is substantially level with the height of the first underfill layer.
    • 4. The apparatus of claim 1, wherein
      • the bump includes copper.
  • 5
    5. An apparatus comprising:
    • a surface including a bond pad
    • a first passivation layer on the surface, wherein the first passivation layer exposes at least a portion of the bond pad
    • a barrier metal on the bond pad
    • a bump attached to the barrier metal such that an undercut is formed between the bump and the first passivation layer
    • a first underfill layer on the first passivation layer and adjacent to the bump, the first underfill layer completely covering the first passivation layer, wherein the first underfill layer exposes a portion of the bump, wherein the first underfill layer fills the undercut and the first underfill is non-conductive, and wherein the underfill layer has a height less than a height of the solder bump
    • a second surface directly soldered to the bump to form a soldered bump connection
    • and a second underfill surrounding the soldered bump connection, wherein the second underfill is non-conductive.
    • 6. The apparatus of claim 5, wherein
      • the surface is on a package substrate.
    • 7. The apparatus of claim 5, wherein
      • the surface is on a microelectronic device.
    • 8. The apparatus of claim 5, wherein
      • the second underfill is epoxy.
    • 9. The apparatus of claim 5, wherein
      • the second underfill is a capillary underfill epoxy.
  • 10
    10. An apparatus comprising:
    • a microelectronic device surface including a bond pad
    • a first passivation layer on the surface, wherein the first passivation layer exposes at least a portion of the bond pad
    • a barrier metal on the bond pad
    • a solder bump attached to the barrier metal such that an undercut is formed between the solder bump and the first passivation layer
    • a first underfill layer on the first passivation layer and adjacent to the solder bump, the first underfill layer completely covering the first passivation layer, wherein: the first underfill layer exposes a portion of the solder bump, the first underfill layer fills the undercut, the first underfill is non-conductive, and the first underfill layer has a height less than a height of the solder bump
    • a substrate, directly soldered to the solder bump to form a soldered connection
    • and a second underfill surrounding the soldered connection, wherein the second underfill is nonconductive.
    • 11. The apparatus of claim 10, wherein
      • the second underfill is a capillary underfill epoxy.
    • 12. The apparatus of claim 10, wherein
      • the first underfill layer comprises
    • 13. The apparatus of claim 10, wherein
      • the first underfill layer comprises
    • 14. The apparatus of claim 10, wherein
      • the bump includes copper.
    • 15. The apparatus of claim 10, wherein
      • the first underfill layer has a thickness in the range of 1 to 15 microns.
    • 16. The apparatus of claim 10, wherein
      • the substrate is soldered to the solder bump using a lead-free solder.
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Description

TECHNICAL FIELD

Embodiments of the invention relate to semiconductor processing and packaging technology. In particular, embodiments of the invention relate to enhancing passivation and interlayer dielectric reliability.

BACKGROUND

In the production of microelectronic products, a microelectronic chip or die is typically packaged before it is sold. The package may provide electrical connection to the chip's internal circuitry, protection from the external environment, and heat dissipation. In one package system, a chip may be flip-chip connected to a substrate. In a flip-chip package, electrical leads on the die are distributed on its active surface and the active surface is electrically connected to corresponding leads on a substrate.

FIGS. 1A-1D illustrate a prior art method for producing and packaging a microelectronic chip or die. FIG. 1A illustrates a die 100 including a substrate 105, a device region 110, an interconnect region 115, a bond pad 120, a passivation layer 125, a barrier metal 130, and a bump 140. Interconnect region 115 includes a plurality of metal interconnect layers that interconnect the devices of device region 110 and provide electrical routing to external circuitry. The metal interconnect layers include metal traces separated and insulated by an interlayer dielectric (ILD) material. Adjacent metal interconnect layers are typically connected by vias which are also separated and insulated by an ILD.

FIG. 1A also illustrates an undercut 135. Undercut 135 may result from a barrier metal layer etch in the presence of bump 140 which etches a layer of barrier metal material from passivation layer 125 and leaves barrier metal 130. Undercut 135 provides a location for the formation of undesired cracks in passivation layer 125 and/or interconnect region 115. For example, undercut 135 may cause a first crack in passivation layer 125 which subsequently causes an additional crack or cracks in the ILD of interconnect region 115. The subsequent cracks may be connected to the initial crack or they may be disconnected from, but related to, the initial crack. In particular, low dielectric constant (low-k) ILD materials are typically susceptible to cracks. The cracks in passivation layer 125 and/or interconnect region 115 may cause poor performance or failure of die 100.

Further, even in the absence of an undercut, bump 140 and the corners of bump 140 near passivation layer 125 are typically causes of undesired cracking and stress in passivation layer 125 and the ILD of interconnect region 115.

In FIGS. 1B and 1C, die 100 is flip-chip bonded to a substrate 180 which includes bumps 190. In bonding die 100 and substrate 180, stresses are typically imparted on die 100 due to coefficient of thermal expansion mismatches between die 100 and substrate 180, and other causes. These stresses may cause additional opportunity for cracking in passivation layer 125 and/or interconnect region 115. Further, after die attach and during “sit” time prior to further processing, cracks may continue to propagate in passivation layer 125 and/or interconnect region 115. In FIG. 1D, an underfill 195 is formed between die 100 and substrate 180.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings, in which the like references indicate similar elements and in which:

FIGS. 1A-1D are cross-sectional views of a prior art method including flip-chip attaching a die to a substrate.

FIG. 2A is a cross-sectional view of partially formed wafer or die including a device region, an interconnect region, a bond pad, a barrier metal, a bump, and a passivation layer.

FIG. 2B is a view similar to FIG. 2A with a layer over the bump and the passivation layer.

FIG. 2C is a view similar to FIG. 2B with a portion of the layer removed to form a sidewall structure.

FIG. 2D is a cross sectional view of a substrate including bumps and sidewall structures being flip-chip attached to a substrate including contacts.

FIG. 2E is a view similar to FIG. 2D with the substrates attached and an underfill between them.

FIG. 3A is a cross-sectional view of partially formed wafer or die including a device region, an interconnect region, a bond pad, and passivation layer.

FIG. 3B is a view similar to FIG. 3A with a portion of the passivation layer removed to expose the bond pad.

FIG. 3C is a view similar to FIG. 3B with a barrier metal formed over the bond pad.

FIG. 3D is a view similar to FIG. 3C with a layer formed over the barrier metal and the passivation layer.

FIG. 3E is a view similar to FIG. 3D with a portion of the layer removed to expose the barrier metal.

FIG. 3F is a view similar to FIG. 3E with a bump formed over the barrier metal.

FIG. 3G is a cross sectional view of a substrate including bumps and a layer among the bumps being flip-chip attached to a substrate including contacts.

FIG. 3H is a view similar to FIG. 3G with the substrates attached and an underfill between them.

FIG. 4A is a cross-sectional view of partially formed wafer or die including a device region, an interconnect region, a bond pad, a barrier metal, a plurality of bumps, and a passivation layer, and a fixture over the bumps.

FIG. 4B is a view similar to FIG. 4A with a material between the passivation layer and the fixture and around the bumps.

FIG. 4C is a view similar to FIG. 4B with the fixture removed.

FIG. 4D is a cross sectional view of a substrate including bumps and a material around the bumps being flip-chip attached to a substrate including contacts.

FIG. 4E is a view similar to FIG. 4D with the substrates attached and an underfill between them.

DETAILED DESCRIPTION

In various embodiments, apparatuses and methods relating to microelectronics processing and packaging are described with reference to figures wherein the same reference numbers are used to describe similar elements. However, various embodiments may be practiced without one or more of the specific details, or with other methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of various embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the invention. Nevertheless, the invention may be practiced without specific details. Furthermore, it is understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

In processing and packaging microelectronic devices, it may be desirable to limit or eliminate cracking in the passivation layer of the device or the interlayer dielectric (ILD) of the interconnect region of the device. Further, it may be desirable to reduce the amount of stress on the passivation layer or the ILD while attaching the device to a substrate. Limiting or eliminating cracking and reducing the stresses on the passivation layer or ILD may reduce the probability of failures in the device, particularly when low-k ILD materials are used. Further, reducing stresses may enable the use of lead-free materials to attach the device to packaging substrates, as is further discussed below. Briefly, the present invention may provide structures and methods that reduce stresses on and limit or eliminate cracking in the passivation layer or the ILD of a microelectronic device.

FIGS. 2A-2E illustrate methods and apparatuses that may reduce stresses on and limit or eliminate cracking in the passivation layer or the ILD of a microelectronic device.

FIG. 2A illustrates a portion of a microelectronic device 200. In various embodiments, microelectronic device 200 may be a wafer or a die. Microelectronic device 200 may include a substrate 205, a device region 210, an interconnect region 215, a bond pad 220, a passivation layer 225, a barrier metal 230, and a bump 240. In some embodiments, microelectronic device 200 may also include an undercut 235. In an embodiment, microelectronic device 200 may include a plurality of bond pads, barrier metals, and bumps analogous to those shown in FIG. 2A.

Substrate 205 may include any suitable material or materials such as silicon, germanium, gallium arsenide, indium phosphide, silicon on insulator, or the like. Device region 210 may include any suitable devices. In an embodiment, device region 210 may include transistors. In other embodiments, device region 210 may include resistors or conductors. Interconnect region 215 may include a stack of metallization layers including metal interconnects separated and insulated by an ILD material or materials. In an embodiment, the ILD may include a low-k ILD, having a dielectric constant, k, of less than about 4. The metallization layers of interconnect region 215 may be electrically interconnected to adjacent metallization layers by vias. The vias may be separated and insulated by an ILD material or materials. In an embodiment, the ILD may include a low-k ILD. In various embodiments, interconnect region 215 may include about 5 to 9 metallization layers and corresponding via layers, although any number of metallization layers may be used.

Bond pad 220 may be any suitable material and size. In an embodiment, bond pad 220 may be a portion of a metallization layer of interconnect region 215. In an embodiment, bond pad 220 may include copper. Passivation layer 225 may include any suitable material. In an embodiment, passivation layer 225 may include a spark passivation material. In another embodiment, passivation layer 225 may include a polyimide material. In an embodiment, passivation layer 225 may surround bond pad 220 and expose bond pad 220 for barrier metal 230. In another embodiment (not shown), bond pad 220 may be surrounded by an adjacent and substantially coplanar ILD material, and passivation layer 225 may be over the ILD material and expose bond pad 220 for barrier metal 230.

Barrier metal 230 may include any conductive material or stack of conductive materials. Bump 240 may also include any conductive material or materials. In an embodiment, bump 240 may include copper. Undercut 235 may be of any size or shape, and may be a source for increased stress and undesirable crack formation and propagation in passivation layer 225 and interconnect region 215. In an embodiment, undercut 235 may not be present.

As illustrated in FIG. 2B, a layer 245 may be formed over passivation layer 225 and bump 240. Layer 245 may be any suitable material or materials. In an embodiment, layer 245 may be a conformal layer. In an embodiment, layer 245 may include silicon nitride. In an embodiment, layer 245 may be a conformal layer formed by chemical vapor deposition (CVD). In another embodiment, layer 245 may be a conformal layer having a thickness in the range of about 1 to 15 microns. In an embodiment, layer 245 may be a conformal layer having a thickness in the range of about 4 to 10 microns. In another embodiment, layer 245 may be a conformal layer having a thickness in the range of about 5 to 15 microns.

As illustrated in FIG. 2C, portions of layer 245 may be removed to form structure 250. Structure 250 may be formed by any suitable technique. In an embodiment, structure 250 may be formed by an anisotropic etch of layer 245. In another embodiment, structure 250 may be formed by an anisotropic ion beam etch of layer 245. In an embodiment, layer 245 may be entirely removed from the top surface of bump 240. In an embodiment, the portion of layer 245 that does not form structure 250 may be entirely removed. However, in some embodiments, a portion or part of layer 245 that does not form structure 250, such as a thin remnant of layer 245 or residuals of layer 245, may remain on passivation layer 225. Further, in some embodiments, there may be a plurality of bumps and sidewall structures analogous to those shown in FIG. 2C. Between adjacent sidewall structures, there may be a gap that exposes the portion of passivation layer 225 between the adjacent sidewall structures.

In an embodiment, structure 250 may be around the sides of bump 240 and may therefore be referred to as a sidewall structure. In an embodiment, structure 250 may surround bump 240. In an embodiment, structure 250 may have about the same height as bump 240. In other embodiments, structure 250 may have a height that is less than the height of bump 240. Structure 250 may have any suitable width. In an embodiment, structure 250 may have a width in the range of about 1 to 15 microns. In another embodiment, structure 250 may have a width in the range of about 4 to 10 microns. In an embodiment, structure 250 may have a width in the range of about 5 to 15 microns.

Structure 250 may limit or eliminate the formation and propagation of cracks in passivation layer 225 or the ILD of interconnect region 215. Also, structure 250 may lower the stress on passivation layer 225 and the ILD of interconnect region 215. In an embodiment, structure 250 may limit or eliminate cracks and lower the stresses on passivation layer 225 and the ILD of interconnect region 215 by encapsulating undercut 235. In another embodiment, structure 250 may limit or eliminate cracks and lower the stresses on passivation layer 225 and the ILD of interconnect region 215 by providing load sharing with bump 240. In an embodiment, structure 250 may lower the stress on passivation layer 225 and the ILD of interconnect region 215 during subsequent processing, such as die attach.

As illustrated in FIGS. 2D and 2E, device 200 may be attached to a substrate 280 including contacts 290; and an underfill 295 may be formed between device 200 and substrate 280. In FIGS. 2D and 2E, some details of FIG. 2C are not shown for the sake of clarity.

In an embodiment, the formation of structure 250 may be at or near the end of wafer processing and the attachment of device 200 and substrate 280 may be performed after dicing substrate 205. In an embodiment, attaching device 200 and substrate 280 may include a flip-chip attachment. In an embodiment, attaching device 200 and substrate 280 may include a reflow process. In an embodiment, underfill 295 may include a capillary underfill. In another embodiment, underfill 295 may include a no-flow underfill.

Substrate 280 may be any suitable packaging substrate, such as a printed circuit board (PCB), interposer, motherboard, card, or the like. In some embodiments, contacts 290 may extend away from the surface of substrate 280 and contacts 290 may be considered bumps. In an embodiment, contacts 290 may be bumps that include a lead-based solder. In other embodiments, contacts 290 may be bumps that include a lead-free solder. In particular, the use of the methods and apparatus described may enable the use of lead-free solders, which are typically less malleable than lead-based solders. In an embodiment, contacts 290 may be bumps that include a lead-free solder comprising tin, silver, or indium.

FIGS. 3A-3H illustrate methods and apparatuses that may reduce stresses on and limit or eliminate cracking in the passivation layer or the ILD of a microelectronic device.

FIG. 3A illustrates a portion of a microelectronic device 300. In various embodiments, microelectronic device 300 may be a wafer or a die. Microelectronic device 300 may include substrate 205, device region 210, interconnect region 215, bond pad 220, and passivation layer 305.

Passivation layer 305 may include any suitable material. In an embodiment, passivation layer 305 may include a spark passivation material. In another embodiment, passivation layer 305 may include a polyimide material. In an embodiment, passivation layer 305 may surround and cover bond pad 220. In another embodiment (not shown), bond pad 220 may be surrounded by an adjacent and substantially coplanar ILD material, and passivation layer 305 may be over the ILD material and bond pad 220.

As illustrated in FIG. 3B, an opening 310 may be formed to expose bond pad 220. In an embodiment, a portion of bond pad 220 may be exposed. In an embodiment, the entire top surface of bond pad 220 may be exposed. Opening 310 may be formed by any available technique. In an embodiment, opening 310 may be formed by lithography and etch steps.

As illustrated in FIG. 3C, a barrier metal 315 may be formed. In an embodiment, barrier metal 315 may be formed over bond pad 220 and a portion of passivation layer 305. In another embodiment, barrier metal 315 may be formed only over bond pad 220. Barrier metal 315 may include any suitable material or stack of materials, and may be formed by any suitable technique. In an embodiment, barrier metal 315 may be formed by deposition, lithography and etch techniques.

As illustrated in FIG. 3D, a layer 320 may be formed over barrier metal 315 and passivation layer 305. Layer 320 may be any suitable material and may be formed by any suitable technique. In an embodiment, layer 320 may include a passivation material. In an embodiment, layer 320 may include a spark passivation material. In another embodiment, layer 320 may include a polyimide material. In an embodiment, layer 320 may include a photoresist. In an embodiment, layer 320 may be formed by a spin on technique.

As illustrated in FIG. 3E, an opening 325 may be formed to expose barrier metal 315. In an embodiment, a portion of barrier metal 315 may be exposed. In another embodiment, the entire top surface of barrier metal 315 may be exposed. Opening 320 may be formed by any available technique. In an embodiment, opening 320 may be formed by lithography and etch techniques.

As illustrated in FIG. 3F, a bump 330 may be formed over barrier metal 315. Bump 330 may include any suitable material and may be formed by any suitable technique. In an embodiment, bump 330 may include copper. In an embodiment, bump 330 may be formed by electroplating. In an embodiment, bump 330 may have a height that extends above the height of layer 320. In another embodiment, bump 330 may have a height that is about coplanar with the height of layer 320.

Layer 320 may limit or eliminate the formation and propagation of cracks in passivation layer 305 and the ILD of interconnect region 215. Also, layer 320 may lower the stress on passivation layer 305 and the ILD of interconnect region 215. In an embodiment, layer 320 may limit or eliminate cracks and lower the stresses on passivation layer 305 and the ILD of interconnect region 215 by providing load sharing with bump 330. In an embodiment, layer 320 may lower the stress on passivation layer 305 and the ILD of interconnect region 215 during subsequent processing, such as die attach.

As illustrated in FIGS. 3G and 3H, device 300 may be bonded to substrate 280 including contacts 290; and underfill 295 may be formed between substrate 205 and substrate 280. In FIGS. 3G and 3H, some details of FIG. 3F are not shown for the sake of clarity.

In an embodiment, the formation of layer 320 may be at or near the end of wafer processing and attachment of device 300 and substrate 280 may be performed after dicing substrate 205. In an embodiment, attaching device 300 and substrate 280 may include a flip-chip attachment. In an embodiment, attaching device 300 and substrate 280 may include a reflow process. In an embodiment, underfill 295 may include a capillary underfill. In another embodiment, underfill 295 may include a no-flow underfill.

As discussed with reference to FIGS. 2D and 2E, contacts 290 may be bumps that include a lead-free solder such as a solder comprising tin, silver, or indium. In particular, the use of the methods and apparatus described may enable the use of lead-free solders, which are typically less malleable than lead-based solders.

FIGS. 4A-4E illustrate methods and apparatuses that may reduce stresses on and limit or eliminate cracking in the passivation layer or the ILD of a microelectronic device.

FIG. 4A illustrates a portion of a microelectronic device 400 and a fixture 405. In various embodiments, microelectronic device 400 may be a wafer or a die. Microelectronic device 400 may include substrate 205, device region 210, interconnect region 215, bond pad 220, and passivation layer 225. In some embodiments, microelectronic device 400 may also include an undercut 235. Microelectronic device 400 and fixture 405 may be put together and held together by any suitable technique.

As illustrated in FIG. 4B, a material 410 may be formed between fixture 405 and passivation layer 225, and around bumps 240. Material 410 may be any suitable material and may be formed by any suitable technique. In an embodiment, material 410 may include an underfill material. In another embodiment, material 410 may include an epoxy. In an embodiment, material 410 may be injected from the side of fixture 405 and microelectronic device 400. In an embodiment, fixture 405 may prevent material 410 from covering bumps 240.

As illustrated in FIG. 4C, fixture 405 may be removed to leave material 410 over passivation layer 225 and around bumps 240. In an embodiment, material 410 may leave a portion of bumps 240 exposed. In an embodiment, a cure step may be performed to harden material 410.

Material 410 may limit or eliminate the formation and propagation of cracks in passivation layer 225 and the ILD of interconnect region 215. Also, material 410 may lower the stress on passivation layer 225 and the ILD of interconnect region 215. In an embodiment, material 410 may limit or eliminate cracks and lower the stresses on passivation layer 225 and the ILD of interconnect region 215 by encapsulating undercut 235. In another embodiment, material 410 may limit or eliminate cracks and lower the stresses on passivation layer 225 and the ILD of interconnect region 215 by providing load sharing with bump 240. In an embodiment, material 410 may lower the stress on passivation layer 225 and the ILD of interconnect region 215 during subsequent processing, such as die attach.

As illustrated in FIGS. 4D and 4E, device 400 may be bonded to substrate 280 including contacts 290, and underfill 295 may be formed between device 400 and substrate 280. In FIGS. 4D and 4E, some details of FIG. 4C are not shown for the sake of clarity.

In an embodiment, the formation of material 410 may be at or near the end of wafer processing and attachment of device 400 and substrate 280 may be after dicing of substrate 205. In an embodiment, attaching device 400 and substrate 280 may include a flip-chip attachment. In an embodiment, attaching device 400 and substrate 280 may include a reflow process. In an embodiment, underfill 295 may include a capillary underfill. In another embodiment, underfill 295 may include a no-flow underfill.

As discussed with reference to FIGS. 2D and 2E, contacts 290 may be bumps that include a lead-free solder such as a solder comprising tin, silver, or indium. In particular, the use of the methods and apparatus described may enable the use of lead-free solders, which are typically less malleable than lead-based solders.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of ordinary skill in the art upon reviewing the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

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31.0/100 Score

Market Attractiveness

It shows from an IP point of view how many competitors are active and innovations are made in the different technical fields of the company. On a company level, the market attractiveness is often also an indicator of how diversified a company is. Here we look into the commercial relevance of the market.

93.0/100 Score

Market Coverage

It shows the sizes of the market that is covered with the IP and in how many countries the IP guarantees protection. It reflects a market size that is potentially addressable with the invented technology/formulation with a legal protection which also includes a freedom to operate. Here we look into the size of the impacted market.

68.64/100 Score

Technology Quality

It shows the degree of innovation that can be derived from a company’s IP. Here we look into ease of detection, ability to design around and significance of the patented feature to the product/service.

93.0/100 Score

Assignee Score

It takes the R&D behavior of the company itself into account that results in IP. During the invention phase, larger companies are considered to assign a higher R&D budget on a certain technology field, these companies have a better influence on their market, on what is marketable and what might lead to a standard.

20.0/100 Score

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It shows the legal strength of IP in terms of its degree of protecting effect. Here we look into claim scope, claim breadth, claim quality, stability and priority.

Citation

Patents Cited in This Cited by
Title Current Assignee Application Date Publication Date
Method for manufacturing a flip chip semiconductor device CITIZEN WATCH CO., LTD. 09 July 1999 09 May 2000
Semiconductor device package and method of making the same TEXAS INSTRUMENTS INCORPORATED 01 March 2004 14 November 2006
Apparatuses and methods to enhance passivation and ILD reliability INTEL CORPORATION 11 June 2012 27 September 2012
Stress-compensation layers in contact arrays, and processes of making same INTEL CORPORATION 31 March 2004 28 February 2006
Thin flip - chip method MICRON TECHNOLOGY, INC. 06 December 2000 06 June 2002
See full citation <>

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