Great research starts with great data.

Learn More
More >
Patent Analysis of

Superconductor device interconnect

Updated Time 12 June 2019

Patent Registration Data

Publication Number

US10003005

Application Number

US15/244827

Application Date

23 August 2016

Publication Date

19 June 2018

Current Assignee

NORTHROP GRUMMAN SYSTEMS CORPORATION

Original Assignee (Applicant)

KIRBY, CHRISTOPHER F.,RENNIE, MICHAEL,GRANINGER, AURELIUS L.

International Classification

H01L39/24,H01L39/02

Cooperative Classification

H01L39/2493,H01L39/025,H01L39/223

Inventor

KIRBY, CHRISTOPHER F.,RENNIE, MICHAEL,GRANINGER, AURELIUS L.

Patent Images

This patent contains figures and images illustrating the invention and its embodiment.

US10003005 Superconductor interconnect 1 US10003005 Superconductor interconnect 2 US10003005 Superconductor interconnect 3
See all images <>

Abstract

A method is provided of forming a superconductor device interconnect structure. The method includes forming a first high temperature dielectric layer overlying a substrate, forming a base electrode in the first high temperature dielectric layer with the base electrode having a top surface aligned with the top surface of the first high temperature dielectric layer, and depositing a second high temperature dielectric layer over the first high temperature dielectric layer and the base electrode. The method further comprises forming a first contact through the second dielectric layer to a first end of the base electrode, forming a Josephson junction (JJ) overlying and in contact with the first contact, and forming a second contact through the second dielectric layer to a second end of the base electrode.

Read more

Claims

1. A method of forming a superconductor device interconnect structure, the method comprising: forming a first high temperature dielectric layer overlying a substrate; forming a base electrode in the first high temperature dielectric layer, the base electrode having a top surface aligned with the top surface of the first high temperature dielectric layer; depositing a second high temperature dielectric layer over the first high temperature dielectric layer and the base electrode; forming a first contact that extends from a top surface of the second high temperature dielectric layer to a first end of the base electrode; forming a Josephson junction (JJ) overlying and in contact with a top surface of the first contact; and forming a second contact that extends from a top surface the second high temperature dielectric layer to a second end of the base electrode.

2. The method of claim 1, wherein the JJ is an aluminum/aluminum oxide/aluminum JJ.

3. The method of claim 2, wherein the base electrode is formed from niobium.

4. The method of claim 1, wherein the first contact has a diameter that is equal to or smaller than a diameter of the JJ, such that the JJ has a width defined by the width of the first contact.

5. The method of claim 1, wherein the dielectric material employed in the first high temperature dielectric layer and the second high temperature dielectric layer is a material that can form the first and second high temperature dielectric layers at a temperature of greater than 180° Celsius.

6. The method of claim 1, further comprising forming a first conductive line overlying the first contact and a second conductive line overlying the second contact, wherein the first and second conductive lines are disposed over the top surface of the second high temperature dielectric layer.

7. The method of claim 6, further comprising: forming a low temperature dielectric layer over the second high temperature dielectric layer, and the JJ; etching a via in the low temperature dielectric layer and the second high temperature dielectric layer for forming the second contact; etching trenches in the low temperature dielectric layer for forming the first conductive line and the second conductive line; filling the via and the trenches with a superconducting material to form the second contact that extends to a second end of the base electrode and to form the first and second conductive lines; polishing the superconducting material down to the surface of the low temperature dielectric layer; and etching away the low temperature dielectric layer.

8. The method of claim 1, wherein the formation of the JJ comprises: polishing the top surface of the first contact; depositing a first aluminum layer over the first contact and the second high temperature dielectric layer; oxidizing the first aluminum layer to form an aluminum oxide layer on a top surface of the aluminum layer; forming a second aluminum layer over the aluminum oxide layer; depositing and patterning a photoresist material layer over the second aluminum layer; etching the second aluminum layer to encapsulate the aluminum oxide layer with the second aluminum layer to form a JJ and remove the remaining portions of the second aluminum layer; and stripping the photoresist material layer.

9. The method of claim 1, wherein the forming the base electrode is formed by a single damascene process.

10. The method of claim 1, further comprising forming one or more layers between the substrate and the first high temperature dielectric layer.

11. A method of forming a superconductor device interconnect structure, the method comprising: forming a first high temperature dielectric layer overlying a substrate; forming a base electrode in the first high temperature dielectric layer, the base electrode having a top surface aligned with the top surface of the first high temperature dielectric layer; depositing a second high temperature dielectric layer over a Josephson junction (JJ), and the first high temperature dielectric layer; forming a first contact from a top surface of the second high temperature dielectric layer to a first end of the base electrode; polishing the top surface of the first contact; depositing a first aluminum layer over the first contact and the second high temperature dielectric layer; oxidizing the first aluminum layer to form an aluminum oxide layer on the top surface of the first aluminum layer; forming a second aluminum layer over the aluminum oxide layer; etching the second aluminum layer to encapsulate the aluminum oxide layer with the second aluminum layer to form a JJ and remove the remaining portions of the second aluminum layer; and forming a second contact from a top surface of the second high temperature dielectric layer to a second end of the base electrode, a first conductive line overlying the first contact and a second conductive line overlying the second contact, wherein the first and second conductive lines overly a top surface of the second high temperature dielectric layer.

12. The method of claim 11, where the forming a second contact, a first conductive line overlying the first contact and a second conductive line overlying the second contact comprises: forming a low temperature dielectric layer over the second high temperature dielectric layer, and the JJ; etching a via in the low temperature dielectric layer and the second high temperature dielectric layer for forming the second contact; etching trenches in the low temperature dielectric layer for forming the first conductive line and the second conductive line; filling the via and the trenches with a superconducting material to form the second contact and the first conductive line the second conductive line; polishing the superconducting material down to the surface of the low temperature dielectric layer; and etching away the low temperature dielectric layer.

13. The method of claim 11, wherein the dielectric material employed in the first high temperature dielectric layer and the second high temperature dielectric layer is a material that can form the first and second high temperature dielectric layers at a temperature above 180° Celsius.

14. The method of claim 11, wherein the second contact and the first and second conductive lines are formed from niobium.

15. The method of claim 11, wherein the base electrode is formed from niobium.

Read more

Claim Tree

  • 1
    1. A method of forming a superconductor device interconnect structure, the method comprising:
    • forming a first high temperature dielectric layer overlying a substrate
    • forming a base electrode in the first high temperature dielectric layer, the base electrode having a top surface aligned with the top surface of the first high temperature dielectric layer
    • depositing a second high temperature dielectric layer over the first high temperature dielectric layer and the base electrode
    • forming a first contact that extends from a top surface of the second high temperature dielectric layer to a first end of the base electrode
    • forming a Josephson junction (JJ) overlying and in contact with a top surface of the first contact
    • and forming a second contact that extends from a top surface the second high temperature dielectric layer to a second end of the base electrode.
    • 2. The method of claim 1, wherein
      • the JJ is an aluminum/aluminum oxide/aluminum JJ.
    • 4. The method of claim 1, wherein
      • the first contact has a diameter that is equal to or smaller than a diameter of the JJ, such that the JJ has a width defined by the width of the first contact.
    • 5. The method of claim 1, wherein
      • the dielectric material employed in the first high temperature dielectric layer and the second high temperature dielectric layer is a material that can form the first and second high temperature dielectric layers at a temperature of greater than 180° Celsius.
    • 6. The method of claim 1, further comprising
      • forming a first conductive line overlying the first contact and a second conductive line overlying the second contact, wherein the first and second conductive lines are disposed over the top surface of the second high temperature dielectric layer.
    • 8. The method of claim 1, wherein
      • the formation of the JJ comprises:
    • 9. The method of claim 1, wherein
      • the forming the base electrode is formed by a single damascene process.
    • 10. The method of claim 1, further comprising
      • forming one or more layers between the substrate and the first high temperature dielectric layer.
  • 11
    11. A method of forming a superconductor device interconnect structure, the method comprising:
    • forming a first high temperature dielectric layer overlying a substrate
    • forming a base electrode in the first high temperature dielectric layer, the base electrode having a top surface aligned with the top surface of the first high temperature dielectric layer
    • depositing a second high temperature dielectric layer over a Josephson junction (JJ), and the first high temperature dielectric layer
    • forming a first contact from a top surface of the second high temperature dielectric layer to a first end of the base electrode
    • polishing the top surface of the first contact
    • depositing a first aluminum layer over the first contact and the second high temperature dielectric layer
    • oxidizing the first aluminum layer to form an aluminum oxide layer on the top surface of the first aluminum layer
    • forming a second aluminum layer over the aluminum oxide layer
    • etching the second aluminum layer to encapsulate the aluminum oxide layer with the second aluminum layer to form a JJ and remove the remaining portions of the second aluminum layer
    • and forming a second contact from a top surface of the second high temperature dielectric layer to a second end of the base electrode, a first conductive line overlying the first contact and a second conductive line overlying the second contact, wherein the first and second conductive lines overly a top surface of the second high temperature dielectric layer.
    • 12. The method of claim 11, where the forming a second contact, a first conductive line overlying the first contact and a second conductive line overlying the second contact comprises:
      • forming a low temperature dielectric layer over the second high temperature dielectric layer, and the JJ
      • etching a via in the low temperature dielectric layer and the second high temperature dielectric layer for forming the second contact
      • etching trenches in the low temperature dielectric layer for forming the first conductive line and the second conductive line
      • filling the via and the trenches with a superconducting material to form the second contact and the first conductive line the second conductive line
      • polishing the superconducting material down to the surface of the low temperature dielectric layer
      • and etching away the low temperature dielectric layer.
    • 13. The method of claim 11, wherein
      • the dielectric material employed in the first high temperature dielectric layer and the second high temperature dielectric layer is a material that can form the first and second high temperature dielectric layers at a temperature above 180° Celsius.
    • 14. The method of claim 11, wherein
      • the second contact and the first and second conductive lines are formed from niobium.
    • 15. The method of claim 11, wherein
      • the base electrode is formed from niobium.
See all independent claims <>

Description

TECHNICAL FIELD

The present invention relates generally to superconductors, and more particularly to a superconductor device interconnect.

BACKGROUND

Superconducting circuits are one of the leading technologies proposed for quantum computing and cryptography applications that are expected to provide significant enhancements to national security applications where communication signal integrity or computing power are needed. They are operated at temperatures<100 kelvin. Efforts on fabrication of superconducting devices have mostly been confined to university or government research labs, with little published on the mass producing of superconducting devices. Therefore, many of the methods used to fabricate superconducting devices in these laboratories utilize processes or equipment incapable of rapid, consistent fabrication. Furthermore, the need for low temperature processing currently presents one of the more significant barriers to mass production of superconducting devices.

One of the common devices employed in superconducting circuits is a Josephson junction (JJ), which can be embedded in a dielectric interconnect structure. Typically, Josephson junctions (JJs) interconnect structures are formed employing low temperature materials (e.g., formed at less than or equal to 180° C.) since the utilization of higher temperature materials can result in damage to the structure of the JJ, and thus cause deterioration of the normal operation of the JJ. The utilization of low temperature materials in the superconducting device interconnects results in more losses than the utilization of high temperature materials. Furthermore, the use of legacy processing techniques to form a JJ result in large topography problems and therefore problems with yield and reliability of the JJ. Both of these reasons lead to a minimum size of JJ of the order of 1 um diameter which limits the density and functionality of an integrated chip.

An attempt has been made to employ low loss high temperature dielectrics (e.g., formed at temperatures greater than 180° C.) in forming circuits with JJs. One example method uses a non-planarized deposition of sputtered quartz to form the high temperature dielectric. However, this process is not scalable to the desired 0.25 um technologies, and the lack of planarization limits these devices to 4 levels of interconnect.

SUMMARY

In one example, a method is providing of forming a superconductor device interconnect structure. The method comprises forming a first high temperature dielectric layer overlying a substrate, forming a base electrode in the first high temperature dielectric layer with the base electrode having a top surface aligned with the top surface of the first high temperature dielectric layer, and depositing a second high temperature dielectric layer over the first high temperature dielectric layer and the base electrode. The method further comprises forming a first contact from a top surface of the second high temperature dielectric layer to a first end of the base electrode, forming a Josephson junction (JJ) overlying and in contact with a top surface of the first contact, and forming a second contact from a top surface of the second dielectric layer to a second end of the base electrode.

In another example, a method of forming a superconductor device interconnect structure is provided. The method comprises forming a first high temperature dielectric layer overlying a substrate, forming a base electrode in the first high temperature dielectric layer with the base electrode having a top surface aligned with the top surface of the first high temperature dielectric layer, depositing a second high temperature dielectric layer over the JJ, and the first high temperature dielectric layer, and forming a first contact from a top surface of the second dielectric layer to a first end of the base electrode. The method further comprises polishing the top surface of the first contact, depositing a first aluminum layer over the first contact and the second dielectric layer, oxidizing the first aluminum layer to form an aluminum oxide layer on the top surface of the first aluminum layer, and forming a second aluminum layer over the aluminum oxide layer. The method further comprises etching the second aluminum layer to encapsulate the aluminum oxide layer with the second aluminum layer to form a JJ and remove the remaining portions of the second aluminum layer, and forming a second contact from a top surface of the second high temperature dielectric layer to a second end of the base electrode, a first conductive line overlying the first contact and a second conductive line overlying the second contact, wherein the first and second conductive lines overly a top surface of the second dielectric layer.

In yet another example, a superconductor device interconnect structure is provided. The structure comprises a first high temperature dielectric layer overlying a substrate, a base electrode disposed in the first high temperature dielectric layer with the base electrode having a top surface aligned with the top surface of the first high temperature dielectric layer, a second high temperature dielectric layer disposed over the first high temperature dielectric layer and the base electrode, and a first contact that extends from a top surface of the second high temperature dielectric layer to a first end of the base electrode. The structure further comprises a JJ overlying the first contact, a second contact that extends from a top surface of the second high temperature dielectric layer to a second end of the base electrode, a first conductive line overlying the first contact, and a second conductive line overlying the second contact.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates cross-sectional view of a superconducting device interconnect structure.

FIG. 2 illustrates a schematic cross-sectional view of an example of a superconductor structure in its early stages of fabrication.

FIG. 3 illustrates a schematic cross-sectional view of the structure of FIG. 2 after a photoresist material layer has been deposited and patterned, and while undergoing an etch process.

FIG. 4 illustrates a schematic cross-sectional view of the structure of FIG. 3 after the etch process and after the photoresist material layer has been stripped.

FIG. 5 illustrates a schematic cross-sectional view of the structure of FIG. 4 after a contact material fill.

FIG. 6 illustrates a schematic cross-sectional view of the structure of FIG. 5 after undergoing a chemical mechanical polish.

FIG. 7 illustrates a schematic cross-sectional view of the structure of FIG. 6 after deposition of a second high temperature dielectric, a photoresist material layer deposition and patterning, and while undergoing an etch process to form a first via.

FIG. 8 illustrates a schematic cross-sectional view of the structure of FIG. 7 after the etch process and after the photoresist material layer has been stripped.

FIG. 9 illustrates a schematic cross-sectional view of the structure of FIG. 8 after a contact material fill to form a first contact and after a chemical mechanical polish.

FIG. 10 illustrates a schematic cross-sectional view of the structure of FIG. 9 after undergoing an oxidation to form an layer on a top surface of the first contact and after undergoing a deoposition process to form a cap layer.

FIG. 11 illustrates a schematic cross-sectional view of the structure of FIG. 10 after a photoresist material layer has been deposited and patterned, and while undergoing an etch process.

FIG. 12 illustrates a schematic cross-sectional view of the structure of FIG. 11 after the etch process and after the photoresist material layer has been stripped.

FIG. 13 illustrates a schematic cross-sectional view of the structure of FIG. 12 after deposition of a low temperature dielectric, a photoresist material layer deposition and patterning, and while undergoing an etch process to form a second via.

FIG. 14 illustrates a schematic cross-sectional view of the structure of FIG. 13 after the etch process and after the photoresist material layer has been stripped.

FIG. 15 illustrates a schematic cross-sectional view of the structure of FIG. 14 after a photoresist material layer has been deposited and patterned, and while undergoing an etch process to form trenches.

FIG. 16 illustrates a schematic cross-sectional view of the structure of FIG. 15 after the etch process and after the photoresist material layer has been stripped.

FIG. 17 illustrates a schematic cross-sectional view of the structure of FIG. 16 after a contact material fill.

FIG. 18 illustrates a schematic cross-sectional view of the structure of FIG. 17 after undergoing a chemical mechanical polish, and while undergoing an etch process to remove the low temperature dielectric layer.

FIG. 19 illustrates a schematic cross-sectional view of the structure of FIG. 18 after undergoing an etch process to remove the low temperature dielectric layer.

DETAILED DESCRIPTION

The present invention is directed to a high temperature low loss dielectric superconductor device (e.g., Josephson junction (JJ)) interconnect structure and a method for forming the same. In one example, an aluminum (AL) based superconducting JJ (e.g., Al/aluminum-oxide(AlOx)/Al) is incorporated into a dual damascene process for scaling into a high density multilevel interconnect submicron technology. The interconnect metal used for this integration can be, for example, niobium (Nb). The active JJ is required to be surrounded by high temperature dielectrics to obtain performance targets at RF frequencies. The method incorporates a scalable JJ process into a planarized superconducting interconnect scheme with a high temperature dielectric.

A high temperature dielectric is formed of a dielectric material that is formed at temperatures greater than 180° C. Temperatures at greater than 180° C. can cause damage to the structure of the JJ, while a low temperature dielectric is formed at temperatures that are less than 180° C. which do not typically cause damage to the structure of the JJ. High temperature dielectrics provide superconducting devices that have less signal loss than devices embedded in low temperature dielectrics and allow for devices within the dielectric to operate with improved performance relative to devices embedded in low temperature dielectric.

The invention also resolves the problem of making high density JJs of 0.5 um and below into a multilevel process flow to enable high levels of interconnects. This present formation of JJs utilizes a scaled process technology, and specifically utilizes the chemical mechanical polish (CMP) of Al followed by oxidation of the aluminum to form the thin tunnel barrier. There is no documented evidence of a JJ formed on a polished surface to date when fabricating high density functional Al/AlOx/Al JJ devices (0.35 um and larger) and circuits with niobium based interconnect of 0.25 um dimensions. The aluminum based JJ has significantly different performance characteristics compared to the common niobium based JJs.

FIG. 1 illustrates cross-sectional view of a superconducting device JJ interconnect structure 10. The superconducting device structure 10 includes an active layer 14 overlying a substrate 12. The substrate 12 can be formed of silicon, glass or other substrate material. The active layer 14 can be a ground layer or a device layer. A first high temperature dielectric layer 16 overlies the active layer 14, and a second high temperature dielectric layer 20 overlies the first high temperature dielectric layer 16. Both the first and the second high temperature dielectric layers are formed of a dielectric material that can be employed in high temperatures (e.g., greater than or equal to 180 degrees Celsius) typically utilized in the formation of semiconductors.

A base electrode 18 is embedded in the first high temperature dielectric layer 16. A JJ 30 is overlays the second high temperature dielectric layer 20. The JJ 30 is formed from an aluminum layer with an oxidized top surface and capped with an aluminum layer that encapsulates the oxidized top surface. A first conductive contact 22 formed from, for example aluminum, extends from the JJ 26 to a first end of the base electrode 18 through the second high temperature dielectric layer 20. Importantly, the first conductive contact 22 defines the width of the JJ 30. In this manner, the JJ can be made with a width as small as the ability of the technology used to make the first conductive contact 22, which is much smaller for the high temperature dielectric material as opposed to a low temperature dielectric material.

A second conductive contact 24 formed from, for example, niobium, extends from the top surface of the second high temperature dielectric layer 20 to a second end of the base electrode 18. A first side of the JJ 30 is connected to a first conductive line 26, which is considered the top electrode of the JJ 30. A second conductive line 28 is considered the counter electrode and is coupled to the base electrode 18 by the second conductive contact 24. The base electrode 18 is coupled to the second side of the JJ 30 and the counter electrode. The conductive lines 26 and 28 are formed of a superconducting material, such as niobium.

Turning now to FIGS. 2-10, fabrication is discussed in connection with formation of interconnects in the superconducting device of FIG. 1. It is to be appreciated that the present example is discussed with respect to a process flow that starts with the formation of either a single or dual damascene layer of superconducting metal in an insulating dielectric. If the JJ is formed first then it would be a single damascene as depicted below or dual damascene if inserted within a multi-level interconnect. The present example will be illustrated with respect to a single damascene trench etched into a dielectric thin film to form a bottom electrode followed by a dual damascene process to form a top electrode.

FIG. 2 illustrates a superconductor structure 50 in its early stages of fabrication. The superconductor structure 50 includes an active layer 54, such as a ground layer or device layer, that overlays an underlying substrate 52. The underlying substrate 52 can be, for example, a silicon or glass wafer that provides mechanical support for the active layer 54 and subsequent overlying layers. A first high temperature dielectric layer 56 is formed over the active layer 54. Any suitable technique for forming the first high temperature dielectric layer 56 may be employed such as Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), High Density Chemical Plasma Vapor Deposition (HDPCVD), sputtering or spin on techniques to a thickness suitable for providing an interconnect layer. Alternatively, the first high temperature dielectric layer 56 can be formed directly on the substrate 50.

Next, as illustrated in FIG. 3, a photoresist material layer 58 is applied to cover the structure and is then patterned and developed to expose a trench opening 60 in the photoresist material layer 58 in accordance with a trench pattern. The photoresist material layer 58 can have a thickness that varies in correspondence with the wavelength of radiation used to pattern the photoresist material layer 58. The photoresist material layer 58 may be formed over the first high temperature dielectric layer 56 via spin-coating or spin casting deposition techniques, selectively irradiated (e.g., via deep ultraviolet (DUV) irradiation) and developed to form the trench opening 60.

FIG. 3 also illustrates performing of an etch 110 (e.g., anisotropic reactive ion etching (RIE)) on the first high temperature dielectric layer 56 to form an extended trench openings 62 (FIG. 4) in the first high temperature dielectric layer 56 based on the trench pattern in the photoresist material layer 58. The etch step 110 can be a dry etch and employ an etchant which selectively etches the underlying first high temperature dielectric layer 56 at a faster rate than the underlying active layer 54 and the overlying photoresist material layer 58. For example, the first high temperature dielectric layer 56 may be anisotropically etched with a plasma gas(es), herein carbon tetrafloride (CF4) containing fluorine ions, in a commercially available etcher, such as a parallel plate RIE apparatus or, alternatively, an electron cyclotron resonance (ECR) plasma reactor to replicate the mask pattern of the photoresist material layer 58 to thereby create the extended trench opening 62. The photoresist material layer 58 is thereafter stripped (e.g., ashing in an O2 plasma) so as to result in the structure shown in FIG. 4.

Next, the structure undergoes a contact material fill to deposit a superconducting material 64, such as niobium or tantalum (Ta) or some other superconducting material, into the trench 62 to form the resultant structure of FIG. 5. The contact material fill can be deposited employing a standard contact material deposition. Following deposition of the contact material fill, the superconducting material 64 is polished via chemical mechanical polishing (CMP) down to the surface level of the first high temperature dielectric layer 56 to form the base electrode 66 and provide the resultant structure of FIG. 6.

Next, as represented in FIG. 7, a second high temperature dielectric layer 68 is formed over the structure of FIG. 6. The second high temperature dielectric layer 68 can be formed in the same manner and techniques as the first high temperature dielectric layer 56. As shown in FIG. 7, a photoresist material layer 70 is applied to cover the structure and is then patterned (e.g., DUV imaged) and developed to expose an open region 72 in the photoresist material layer 70 in accordance with a via pattern. FIG. 7 also illustrates performing of an etch 120 on the second high temperature dielectric layer 68 to form an extended via opening 74 (FIG. 8) in the second high temperature dielectric layer 68 based on the via pattern in the photoresist material layer 70. The first extended open region 72 or via extends to the base electrode 66. The photoresist material layer 70 is thereafter stripped (e.g., ashing in an O2 plasma) so as to result in the structure shown in FIG. 8.

Next, a sputter pre-clean is performed to remove any oxidation on the contact material of the base electrode of FIG. 8. Furthermore, the structure of FIG. 8 undergoes a sputter deposition of, for example, aluminum to fill the first extended open region 72 or via that extends to the base electrode 66 to form a conductive contact 76. The top surface of the first conductive contact 76 is then polished using CMP to form a smooth surface for forming of the JJ on top of the first conductive contact 76 to provide the resultant structure of FIG. 9. The roughness of the polished surface is very important to ensure good JJ characteristics. Additionally, the width of the JJ is defined based on the width of the first extended open region 72 or via, and ultimately the width of the conductive contact 76.

Next, the top surface of the first conductive contact 76 is oxidized to form an oxidized top surface 79 and capped with an aluminum layer 80 to form a JJ 84 (FIG. 12). The thin oxidized aluminum 79 forms the tunnel barrier and the aluminum layers 76 and 80 on both sides sets the gap voltage of the JJ 84. As illustrated in FIG. 11, a photoresist material layer 82 is applied to cover a portion of the structure that defines the JJ and is then patterned and developed to remove the cap layer 80 everywhere except where the JJ is going to be formed. The photoresist material layer 82 overlaps the thin oxidized aluminum at both ends.

FIG. 11 illustrates performing of an etch 130 (e.g., anisotropic reactive ion etching (RIE)) on the cap layer 80 to form the JJ 84 (FIG. 12) to define the final JJ size. The remaining cap layer after the etch 130 encapsulates the thin oxidized aluminum 79. The etch step 130 can be a dry etch that employs an etchant which selectively etches the trilayer stack layer at a faster rate than the first conductive contact 76, the second high temperature dielectric layer 68 and the overlying photoresist material layer 82. A chlorine based plasma etch is utilized as the etchant since it will etch superconducting materials, such as niobium, tantalum and aluminum. The aluminum oxide 79 is so thin that etching does not stop due to the presence of argon in the etching chemistry. The plasma etch is desired to not over-etch significantly into the underlying base electrode 66, which is benefited by the good planarity of the underlying structure to thereby create the JJ 84. The photoresist material layer 82 is thereafter stripped (e.g., ashing in an O2 plasma) so as to result in the structure shown in FIG. 12.

Next, as represented in FIG. 13, a low temperature based dielectric layer 86 (e.g., Tetraethyl Orthosilicate (TEOS)) is formed over the structure of FIG. 12 to encapsulate the JJ 84, and enable a plasma etch selectivity of a subsequent etch to the underlying second high temperature dielectric layer 68. The low temperature based dielectric is now used to protect the JJ 84 from subsequent processing due to temperatures and etching processes. A photoresist material layer 88 is applied to cover the structure and is then patterned (e.g., DUV imaged) and developed to expose an open regions 90 in the photoresist material layer 88 in accordance with a via pattern. FIG. 13 also illustrates performing of an etch 140 on the low temperature based dielectric layer 86 to form extended via opening 92 (FIG. 14) in the low temperature based dielectric layer 86 and the second high temperature dielectric layer 68 based on the via pattern in the photoresist material layer 88. The extended via opening 92 extends to a second end of the base electrode 66. The photoresist material layer 88 is thereafter stripped (e.g., ashing in an O2 plasma) to provide the resultant structure of FIG. 14.

Next, as represented in FIG. 15, a photoresist material layer 94 is applied to cover the structure and is then patterned and developed to expose open trench regions 96 in the photoresist material layer 94 in accordance with a trench pattern. FIG. 15 also illustrates performing of an etch 150 (e.g., anisotropic reactive ion etching (RIE)) on the low temperature based dielectric layer 86 to form extended openings 96 (FIG. 16) in the low temperature based dielectric layer 86 based on the trench pattern in the photoresist material layer 94. The etch 150 is a selective etch that is selective to stop on the second high temperature dielectric layer 68. The photoresist material layer 94 is thereafter stripped (e.g., ashing in an O2 plasma) so as to result in the structure shown in FIG. 16.

Next, the structure undergoes a contact material fill to deposit superconducting material 100, such as niobium, into the via 92 and trenches 98 to form contact 100 and conductive lines 102 employing a standard contact material deposition to provide the resultant structure in FIG. 17. Following deposition of the contact material fill, the contact material is polished via chemical mechanical polishing (CMP) down to the surface level of the TEOS based dielectric layer 86 to provide the resultant structure in FIG. 18. Finally an oxide plasma etch 160 is performed on the structure of FIG. 18 to remove the low temperature based dielectric layer 86 to ensure no high loss dielectric is near the JJ 84.

A resultant final structure shown in FIG. 19 is provided that includes contacts that extend to the base electrode 66 and the JJ 84 coupled to respective conductive lines 102 to provide a structure similar to the structure illustrated in FIG. 1. The conductive lines 102 form a counter electrode coupled to the base electrode 66 which is coupled to a first end of the JJ 84 with a top electrode coupled to a second end of the JJ 84.

What have been described above are examples of the invention. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the invention, but one of ordinary skill in the art will recognize that many further combinations and permutations of the invention are possible. Accordingly, the invention is intended to embrace all such alterations, modifications, and variations that fall within the scope of this application, including the appended claims.

Read more
PatSnap Solutions

Great research starts with great data.

Use the most comprehensive innovation intelligence platform to maximise ROI on research.

Learn More

Patent Valuation

$

Reveal the value <>

31.0/100 Score

Market Attractiveness

It shows from an IP point of view how many competitors are active and innovations are made in the different technical fields of the company. On a company level, the market attractiveness is often also an indicator of how diversified a company is. Here we look into the commercial relevance of the market.

37.0/100 Score

Market Coverage

It shows the sizes of the market that is covered with the IP and in how many countries the IP guarantees protection. It reflects a market size that is potentially addressable with the invented technology/formulation with a legal protection which also includes a freedom to operate. Here we look into the size of the impacted market.

72.61/100 Score

Technology Quality

It shows the degree of innovation that can be derived from a company’s IP. Here we look into ease of detection, ability to design around and significance of the patented feature to the product/service.

47.0/100 Score

Assignee Score

It takes the R&D behavior of the company itself into account that results in IP. During the invention phase, larger companies are considered to assign a higher R&D budget on a certain technology field, these companies have a better influence on their market, on what is marketable and what might lead to a standard.

14.59/100 Score

Legal Score

It shows the legal strength of IP in terms of its degree of protecting effect. Here we look into claim scope, claim breadth, claim quality, stability and priority.

Citation

Patents Cited in This Cited by
Title Current Assignee Application Date Publication Date
Planarization of Josephson integrated circuit INTERNATIONAL BUSINESS MACHINES CORPORATION 04 April 1991 08 October 1991
Non-oxide based dielectrics for superconductor devices NORTHROP GRUMMAN SYSTEMS CORPORATION 08 December 2015 08 June 2017
Multi-qubit coupling structure SAMSUNG ELECTRONICS CO., LTD. 25 November 2015 26 May 2016
Superconductor device interconnect structure NORTHROP GRUMMAN SYSTEMS CORPORATION 16 August 2016 03 October 2017
See full citation <>

More like this

Title Current Assignee Application Date Publication Date
Oxide superconductor and method for producing same KABUSHIKI KAISHA TOSHIBA 27 July 2016 31 August 2017
Fabrication of interlayer dielectrics with high quality interfaces for quantum computing devices GOOGLE INC.,MEGRANT, ANTHONY EDWARD 30 December 2015 06 July 2017
Capacitor for a semiconductor device and method of forming the same SAMSUNG ELECTRONICS CO., LTD. 14 October 2008 12 February 2009
Composite distributed dielectric structure INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE 17 June 2005 25 March 2008
A manufacturing method for a nanostructured device using a shadow mask UNIVERSITY OF COPENHAGEN 07 March 2017 14 September 2017
Oxide superconductor and method for producing same INTERNATIONAL SUPERCONDUCTIVITY TECHNOLOGY CENTER 03 March 2000 13 September 2000
Manufacture of josephson element of oxide superconductor NIPPON TELEGRAPH & TELEPHONE 25 July 1980 13 February 1982
Improved josephson junction using molecular beam epitaxy AMBATURE, INC. 08 July 2017 18 January 2018
Suspended josephson junctions INTEL CORPORATION 13 June 2016 21 December 2017
Superconductor device for operating in an external magnetic field SIEMENS AKTIENGESELLSCHAFT 22 March 2017 28 September 2017
Oxide superconductor HITACHI, LTD. 11 November 1988 11 April 1990
Superconducting qubits with caps on superconductors INTEL CORPORATION 13 June 2016 21 December 2017
Memory cell having a magnetic josephson junction device with doped magnetic alloy layer MICROSOFT TECHNOLOGY LICENSING, LLC 20 July 2017 01 February 2018
Superconducting integrated circuit MASSACHUSETTS INSTITUTE OF TECHNOLOGY 21 July 2016 26 January 2017
Non-oxide based dielectrics for superconductor devices NORTHROP GRUMMAN SYSTEMS CORPORATION 14 October 2016 15 June 2017
Bottom recess process for an outer blocking dielectric layer inside a memory opening SANDISK TECHNOLOGIES, INC. 22 September 2015 28 April 2016
Elastic wave device MURATA MANUFACTURING CO., LTD. 16 February 2017 02 November 2017
Optoelectronic device with dielectric layer and method of manufacture ALTA DEVICES, INC. 21 September 2016 09 March 2017
See all similar patents <>

More Patents & Intellectual Property

PatSnap Solutions

PatSnap solutions are used by R&D teams, legal and IP professionals, those in business intelligence and strategic planning roles and by research staff at academic institutions globally.

PatSnap Solutions
Search & Analyze
The widest range of IP search tools makes getting the right answers and asking the right questions easier than ever. One click analysis extracts meaningful information on competitors and technology trends from IP data.
Business Intelligence
Gain powerful insights into future technology changes, market shifts and competitor strategies.
Workflow
Manage IP-related processes across multiple teams and departments with integrated collaboration and workflow tools.
Contact Sales
Clsoe
US10003005 Superconductor interconnect 1 US10003005 Superconductor interconnect 2 US10003005 Superconductor interconnect 3