Great research starts with great data.

Learn More
More >
Patent Analysis of

Fast FIR filtering technique for multirate filters

Updated Time 12 June 2019

Patent Registration Data

Publication Number

US10003324

Application Number

US14/799950

Application Date

15 July 2015

Publication Date

19 June 2018

Current Assignee

VECIMA NETWORKS INC.

Original Assignee (Applicant)

VECIMA NETWORKS INC.

International Classification

H03H17/06,H03H17/02

Cooperative Classification

H03H17/0621,H03H17/0275,H03H2017/0247

Inventor

BERSCHEID, BRIAN,MAYILAVELANE, AROUTCHELVAME

Patent Images

This patent contains figures and images illustrating the invention and its embodiment.

US10003324 Fast FIR filtering technique 1 US10003324 Fast FIR filtering technique 2 US10003324 Fast FIR filtering technique 3
See all images <>

Abstract

Data samples are filtered by using a digital filter where the length of an impulse response of the digital filter is finite, an impulse response of the digital filter is symmetric and the operation of the digital filter is multi-rate. The method uses a polyphase decomposition to break down the input data stream into N parallel substreams and the multi-rate digital filter is separated by a polyphase decomposition into multiple lower-rate sub-filters where each of the sub-filters is separated into a set of simpler sub-sub-filters which operate upon the same set of input samples and which have impulse responses which are jointly centro-symmetric, a set of pre-filtering arithmetic structures, and a set of post-filtering arithmetic structures and performing each such pair of sub-sub-filtering operations using a single shared filter structure, a set of pre-filtering combining adders, and a set of post-filtering separating adders.

Read more

Claims

1. A method for filtering data samples comprising: using a digital filter to act upon a input data stream in order to transform it into an output data stream, wherein: the length of an impulse response of the digital filter is finite; an impulse response of the digital filter is symmetric; the operation of the digital filter is multi-rate; using a polyphase decomposition to break down the input data stream into N parallel substreams; the multi-rate digital filter being separated by a polyphase decomposition into multiple lower-rate sub-filters; each of the sub-filters being separated one or more times into a set of simpler sub-sub-filters, a set of pre-filtering arithmetic structures, and a set of post-filtering arithmetic structures, according to a fast FIR filtering decomposition algorithm; the set of sub-sub-filters comprising one or more pairs of sub-sub-filters which operate upon the same set of input samples and which have impulse responses which are jointly centro-symmetric; and performing each such pair of sub-sub-filtering operations using a single shared filter structure, a set of pre-filtering combining adders, and a set of post-filtering separating adders.

2. The method according to claim 1, wherein the multi-rate digital filter is a digital interpolator and wherein a single pre-filtering arithmetic structure is used to generate the set of input data samples required by multiple sets of sub-sub-filters.

3. The method according to claim 2, wherein the order of the pre-filtering and post-filtering arithmetic structures is interchanged through a circuit transposition operation.

4. The method according to claim 1, wherein the filter is a digital decimator and a single post-filtering arithmetic structure is used to process the output samples from Multiple sets of sub-sub-filters.

5. The method according to claim 4, wherein the order of the pre-filtering and post-filtering arithmetic structures is interchanged through a circuit transposition operation.

6. The method according to claim 1, wherein the fast FIR decomposition algorithm is a 2×2 decomposition as described in equation 6.

7. The method according to claim 1, wherein the fast FIR decomposition algorithm is a 3×3 decomposition as described in equation 8.

8. A method for filtering data samples comprising: using a digital filter to act upon a input data stream in order to transform it into an output data stream, wherein: the length of an impulse response of the digital filter is finite; an impulse response of the digital filter is symmetric; the operation of the digital filter is multi-rate; using a polyphase decomposition to break down the input data stream into N parallel substreams; the multi-rate digital filter being separated by a polyphase decomposition into multiple lower-rate sub-filters; each of the sub-filters being separated one or more times into a set of simpler sub-sub-filters, a set of pre-filtering arithmetic structures, and a set of post-filtering arithmetic structures, according to a fast FIR filtering decomposition algorithm; wherein the multi-rate digital filter is a digital interpolator and wherein a single pre-filtering arithmetic structure is used to generate the set of input data samples required by multiple sets of sub-sub-filters.

9. The method according to claim 8, wherein the order of the pre-filtering and post-filtering arithmetic structures is interchanged through a circuit transposition operation.

10. The method according to claim 8, wherein the fast FIR decomposition algorithm is a 2×2 decomposition as described in equation 6.

11. The method according to claim 8, wherein the fast FIR decomposition algorithm is a 3×3 decomposition as described in equation 8.

12. A method for filtering data samples comprising: using a digital filter to act upon a input data stream in order to transform it into an output data stream, wherein: the length of an impulse response of the digital filter is finite; an impulse response of the digital filter is symmetric; the operation of the digital filter is multi-rate; using a polyphase decomposition to break down the input data stream into N parallel substreams; the multi-rate digital filter being separated by a polyphase decomposition into multiple lower-rate sub-filters; each of the sub-filters being separated one or more times into a set of simpler sub-sub-filters, a set of pre-filtering arithmetic structures, and a set of post-filtering arithmetic structures, according to a fast FIR filtering decomposition algorithm; wherein the filter is a digital decimator and a single post-filtering arithmetic structure is used to process the output samples from multiple sets of sub-sub-filters.

13. The method according to claim 12, wherein the order of the pre-filtering and post-filtering arithmetic structures is interchanged through a circuit transposition operation.

14. The method according to claim 12, wherein the fast FIR decomposition algorithm is a 2×2 decomposition as described in equation 6.

15. The method according to claim 12, wherein the fast FIR decomposition algorithm is a 3×3 decomposition as described in equation 8.

Read more

Claim Tree

  • 1
    1. A method for filtering data samples comprising:
    • using a digital filter to act upon a input data stream in order to transform it into an output data stream, wherein: the length of an impulse response of the digital filter is finite
    • an impulse response of the digital filter is symmetric
    • the operation of the digital filter is multi-rate
    • using a polyphase decomposition to break down the input data stream into N parallel substreams
    • the multi-rate digital filter being separated by a polyphase decomposition into multiple lower-rate sub-filters
    • each of the sub-filters being separated one or more times into a set of simpler sub-sub-filters, a set of pre-filtering arithmetic structures, and a set of post-filtering arithmetic structures, according to a fast FIR filtering decomposition algorithm
    • the set of sub-sub-filters comprising one or more pairs of sub-sub-filters which operate upon the same set of input samples and which have impulse responses which are jointly centro-symmetric
    • and performing each such pair of sub-sub-filtering operations using a single shared filter structure, a set of pre-filtering combining adders, and a set of post-filtering separating adders.
    • 2. The method according to claim 1, wherein
      • the multi-rate digital filter is a digital interpolator and wherein
    • 4. The method according to claim 1, wherein
      • the filter is a digital decimator and a single post-filtering arithmetic structure is used to process the output samples from Multiple sets of sub-sub-filters.
    • 6. The method according to claim 1, wherein
      • the fast FIR decomposition algorithm is a 2×2 decomposition as described in equation 6.
    • 7. The method according to claim 1, wherein
      • the fast FIR decomposition algorithm is a 3×3 decomposition as described in equation 8.
  • 8
    8. A method for filtering data samples comprising:
    • using a digital filter to act upon a input data stream in order to transform it into an output data stream, wherein: the length of an impulse response of the digital filter is finite
    • an impulse response of the digital filter is symmetric
    • the operation of the digital filter is multi-rate
    • using a polyphase decomposition to break down the input data stream into N parallel substreams
    • the multi-rate digital filter being separated by a polyphase decomposition into multiple lower-rate sub-filters
    • each of the sub-filters being separated one or more times into a set of simpler sub-sub-filters, a set of pre-filtering arithmetic structures, and a set of post-filtering arithmetic structures, according to a fast FIR filtering decomposition algorithm
    • wherein the multi-rate digital filter is a digital interpolator and wherein a single pre-filtering arithmetic structure is used to generate the set of input data samples required by multiple sets of sub-sub-filters.
    • 9. The method according to claim 8, wherein
      • the order of the pre-filtering and post-filtering arithmetic structures is interchanged through a circuit transposition operation.
    • 10. The method according to claim 8, wherein
      • the fast FIR decomposition algorithm is a 2×2 decomposition as described in equation 6.
    • 11. The method according to claim 8, wherein
      • the fast FIR decomposition algorithm is a 3×3 decomposition as described in equation 8.
  • 12
    12. A method for filtering data samples comprising:
    • using a digital filter to act upon a input data stream in order to transform it into an output data stream, wherein: the length of an impulse response of the digital filter is finite
    • an impulse response of the digital filter is symmetric
    • the operation of the digital filter is multi-rate
    • using a polyphase decomposition to break down the input data stream into N parallel substreams
    • the multi-rate digital filter being separated by a polyphase decomposition into multiple lower-rate sub-filters
    • each of the sub-filters being separated one or more times into a set of simpler sub-sub-filters, a set of pre-filtering arithmetic structures, and a set of post-filtering arithmetic structures, according to a fast FIR filtering decomposition algorithm
    • wherein the filter is a digital decimator and a single post-filtering arithmetic structure is used to process the output samples from multiple sets of sub-sub-filters.
    • 13. The method according to claim 12, wherein
      • the order of the pre-filtering and post-filtering arithmetic structures is interchanged through a circuit transposition operation.
    • 14. The method according to claim 12, wherein
      • the fast FIR decomposition algorithm is a 2×2 decomposition as described in equation 6.
    • 15. The method according to claim 12, wherein
      • the fast FIR decomposition algorithm is a 3×3 decomposition as described in equation 8.
See all independent claims <>

Description

This invention relates to a method for filtering data samples using a digital filter to act upon an input data stream in order to transform it into an output data stream, where the length of an impulse response of the digital filter is finite, the impulse response of the digital filter is symmetric and the operation of the digital filter is multi-rate.

BACKGROUND OF THE INVENTION

The following references are related to this field and may provide information relevant to the subject matter herein so that the disclosures of each of the following documents are incorporated herein by reference:

  • [1] A. Oppenheim and R. Schafer, Discrete-Time Signal Processing. Pearson Education, 2011.
  • [2] F. Van de Sande, N. Lugil, F. Demarsin, Z. Hendrix, A. Andries, P. Brandt, W. Anklam, J. Patterson, B. Miller, M. Rytting, M. Whaley, B. Jewett, J. Liu, J. Wegman, and K. Poulton, “A 7.2 gsa/s, 14 bit or 12 gsa/s, 12 bit signal generator on a chip in a 165 ghz ft bicmos process,”Solid-State Circuits, IEEE Journal of, vol. 47, no. 4, pp. 1003-1012, 2012.
  • [3] M.-J. Choe, Kwang-Hyun-Baek, and M. Teshome, “A 1.6-gs/s 12-bit return-to-zero gaas rf dac for multiple nyquist operation,”Solid-State Circuits, IEEE Journal of, vol. 40, no. 12, pp. 2456-2468, 2005.
  • [4] J. Xiao, B. Chen, T. Y. Kim, N.-Y. Wang, X. Chen, T.-H. Chih, K. Raviprakash, H.-F. Chen, R. Gomez, and J. Chang, “A 13-bit 9 gs/s rf dac-based broadband transmitter in 28 nm cmos,” in VLSI Circuits (VLSIC), 2013 Symposium on, 2013, pp. C262-C263.
  • [5] B. Mohr, N. Zimmermann, B. Thiel, J. Mueller, Y. Wang, Y. Zhang, F. Lemke, R. Leys, S. Schenk, U. Bruening, R. Negra, and S. Heinen, “An rfdac based reconfigurable multi-standard transmitter in 65 nm cmos,” in Radio Frequency Integrated Circuits Symposium (RFIC), 2012 IEEE, 2012, pp. 109-112.
  • [6] K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation. Wiley, 1999.
  • [7] Z.-J. Mou and P. Duhamel, “Short-length fir filters and their use in fast nonrecursive filtering,”Signal Processing, IEEE Transactions on, vol. 39, no. 6, pp. 1322-1332, 1991.
  • [8] C. Cheng and K. Parhi, “Hardware efficient fast parallel fir filter structures based on iterated short convolution,”Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 51, no. 8, pp. 1492-1500, 2004.
  • [9] Y.-C. Tsao and K. Choi, “Area-efficient parallel fir digital filter structures for symmetric convolutions based on fast fir algorithm,”Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 20, no. 2, pp. 366-371, 2012.
  • [10] Z.-J. Mou and P. Duhamel, “A unified approach to the fast fir filtering algorithms,” in Acoustics, Speech, and Signal Processing, 1988. ICASSP-88, 1988 International Conference on, 1988, pp. 1914-1917 vol. 3.
  • [11] I.-S. Lin and S. Mitra, “Fast fir filtering algorithms based on overlapped block structure,” in Circuits and Systems, 1993, ISCAS '93, 1993 IEEE International Symposium on, 1993, pp. 363-366 vol. 1.
  • [12] C. Cheng and K. Parhi, “Low-cost parallel fir filter structures with 2-stage parallelism,”Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 54, no. 2, pp. 280-290, 2007.
  • [13] Y.-C. Tsao and K. Choi, “Area-efficient vlsi implementation for parallel linear-phase fir digital filters of odd length based on fast fir algorithm,”Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 59, no. 6, pp. 371-375, 2012.
  • [14] R. Crochiere and L. Rabiner, Multirate digital signal processing. Prentice Hall, 1983.
  • [15] Z.-J. Mou, “Symmetry exploitation in digital interpolators/decimators,”Signal Processing, IEEE Transactions on, vol. 44, no. 10, pp. 2611-2615, 1996.

Finite impulse response (FIR) filters are commonly used in digital communication systems to perform a number of operations, including channel shaping or matched filtering, channel up/downconversion, channel synchronization, RF pre-distortion, and adaptive equalization. As a result, there has been a significant amount of research into methods of implementing FIR filters in FPGAs, ASICs and DSP processors (henceforth “FPGAs”). Over the years, a number of efficient techniques and structures have been identified and are now widely known to the industrial and academic communities [1].

Due to recent advances in RF integrated circuit technology, a current trend in the industry is to use wideband digital-to-analog and analog-to-digital converters to digitize or output large (up to multiple GHz) blocks of RF spectrum [2]-[5]. While this is very convenient from a system perspective, the higher sampling rates necessitated by these wideband signals place a significant computational burden upon the FPGA which processes the digital signal. In many applications, the required sampling rate of the digital signal exceeds the maximum clock frequency of the FPGA, which means that many traditional FIR filter structures are not directly applicable.

The straightforward method of handling this scenario is to construct a so-called parallel FIR filter, in which the high frequency input data is represented as L parallel streams, where L is the ratio of the sampling frequency to the FPGA clock frequency. The original prototype filter is decomposed into a set of L2 subfilters which are applied to the incoming parallel data. The outputs of these subfilters are then combined in order to generate L parallel output data streams [6]. The downside of the parallel FIR approach is its cost, which increases linearly with L. As the required sampling frequency increases, the number of parallel data streams becomes large, which can render even modest filtering operations computationally expensive. Consequently, there has been renewed interest in structures for the implementation of high-speed FIR filters in recent years [6]-[13].

One such structure is known as the Fast FIR Algorithm (FFA), described in detail in [6], [7], and [10]. The FFA decomposes the parallel filtering operation in a manner which allows some of the subfilters to be replaced with pre- and post-adders. This reduces the number of multiplications required to perform the filtering operation at the cost of extra additions—an advantageous tradeoff because the hardware cost of adders is typically much less than that of multipliers.

One downside of the standard FFA algorithm is that it is not well-suited to the case where the filter coefficients are symmetrical. Under normal circumstances, the number of multiplications required for a symmetrical filter may be cut in half by adding the common terms before multiplying. However, when the FFA is applied to a symmetrical filter, most of the FFA's subfilters are not symmetrical, thereby negating much of the benefit of the FFA. To address this deficiency, Tsao and Choi (T&C) proposed a modified FFA which is better-suited to symmetrical filters [9]. By changing the method used to construct the subfilters, T&C were able to generate a structure in which a higher proportion of the subfilters have symmetrical coefficients, resulting in a lower computational cost for symmetrical filters than the traditional FFA.

However, the T&C FFA was designed to handle only single rate FIR filters. The algorithm cannnot be directly applied to multirate filters, such as the high-rate interpolators and decimators which are needed to convert to and from the RF sampling frequency in modern systems. As a result, this critical filtering stage is typically relatively expensive in modern systems. In this paper, a technique for reducing the computational complexity of multirate filters through the use of the T&C FFA is presented. This technique is applicable to all multirate filters, but is particularly useful for high speed interpolators and decimators.

The output of a single-rate N-tap FIR filter with filter coefficients hi for an infinite length input sequence xn is expressed as

yn=i=0N-1hixn-i,n=0,1,2,(1)

Unlike the single-rate filter of equation 1, an L-parallel FIR filter receives L input samples every clock cycle. Such an L-parallel filter can be expressed using a polyphase decomposition as given below

i=0L-1Yi(zL)z-i=j=0L-1Xj(zL)z-jk=0L-1Hk(zL)z-kwhereXj=p=0z-pxLp+j,Hk=p=0NL-1z-phLp+kandYi=p=0z-py(Lp+i)(2)

for i, j, k=0, 1, 2, . . . , L−1. For example, the standard 2-by-2 FFA described in [6] receives two input samples each clock cycle, as shown in FIG. 1a. This filter may be expressed mathematically as

Y=Y0+z-1Y1=(H0+z-1H1)(X0+z-1X1)={H0X0+z-2H1X1}+z-1{H0X1+H1X0}={H0X0+z-2H1X1}+z-1{(H0+H1)(X0+X1)-H0X0-H1X1}(3)

The filter of equation (3) can be represented in matrix form as given below.

y2=qs,2×gs,2×hs,2×ps,2×x2  (4)

where

ps,2T=[110011],qs,2=[10D-11-1],

D=z−1, gs,2=I3, which is the 3×3 identity matrix, hs,2=ps,2×[H0 H1]T, y2=[Y0 Y1]T, and x2=[X0 X1]T. Note that in this paper, the superscriptT denotes transposition of a matrix and the subscript s indicates that the matrix in question refers to a standard FFA.

From equation (4), it is apparent that an implementation of the 2-by-2 standard FFA requires 3 subfilters (from subfilter matrix hs,2), one pre-adder (from pre-add matrix ps,2), and three post-adders (from post-add matrix qs,2). Assuming a symmetrical original prototype filter, only one of the FFA subfilters (H0+H1) is symmetrical.

In [9], T&C presented an alternate 2-by-2 FFA which is specifically defined for the case of a symmetrical prototype filter. The 2-by-2 T&C FFA, which is shown in FIG. 1b, is mathematically expressed as

Y={1/2[(H0+H1)(X0+X1)+(H0-H1)(X0-X1)]-H1X1+z-2H1X1}+z-1{1/2[(H0+H1)(X0+X1)-(H0-H1)(X0-X1)]}(5)

Equation 5 may be expressed in matrix form as

y2=qc,2×gc,2×hc,2×pc,2×x2  (6)

where

pc,2T=[1101-11],qc,2=[11(-1+D)1-10],

gc,2=diag[½½ 1], and hc,2=pc,2×[H0 H1]T. In this paper, diagonal matrices such as gc,2 are represented using the notation diag[rowval], where rowval is the set of values on the main diagonal. The subscript c is used to indicate that a matrix belongs to a T&C FFA.

Equation 6 indicates that an implementation of the 2-by-2 T&C FFA requires 3 subfilters, two pre-adders, and four post-adders, which is an increase of two adders compared to the standard FFA. However, two of the FFA subfilters, (H0+H1) and (H0−H1), are symmetrical.

Similarly, the matrix forms of the 3-by-3 standard and T&C FFAs are given in equations (7) and (8), respectively.

y3=qs,3×gs,3×hs,3×ps,3×x3  (7)

where

ps,3T=[100101010111001011],qs,3=[1-D-D0D0-1-1D100020-1-11],

gs,3=I6, hs,3=ps,3×[H0H1H2]T, y3=[Y0 Y1 Y2]T, and x3=[X0 X1 X2]T.

y3=qc,3×gc,3×hc,3×pc,3×x3  (8)

where

pc,3T=[1101111-1110000011-1],qc,3=[1-D1+D-1-DD-2D01-D-1-DD0DD00101-1],

gc,3=diag[½½ 1½½], and hc,3=pc,3×[H0 H1 H2]T.

The above equations indicate that an implementation of the 3-by-3 standard FFA requires six subfilters, three pre-adders, and seven post-adders. In contrast, the 3-by-3 T&C FFA requires six subfilters, five pre-adders, and twelve post-adders. As with the 2-by-2 FFAs already discussed, the advantage of the 3-by-3 T&C FFA is that it yields a greater number of symmetrical subfilters: four, as opposed to two in the case of the standard 3-by-3 FFA.

It is possible to construct a composite L-by-L FFA by cascading multiple stages of 2-by-2 and/or 3-by-3 FFAs. In this scenario, L=Πi=0W−1li, where li=2 or 3 represents the FFA order of the i'th stage of the decomposition and W represents the total number of stages in the decomposition. To illustrate, consider decompsing an N-tap FIR filter to generate a 6-by-6 FFA. The first cascading stage applies a 2-by-2 FFA (l0=2) on the FIR filter which results in three subfilters of length N/2. The second cascading stage applies a 3-by-3 FFA (l1=3) to decompose each subfilter from the first stage into six subfilters, each of length N/6. Thus, the 6-by-6 FFA has a total of 18 subfilters, each of length N/6.

In general, an L-by-L standard FFA may be expressed mathematically as:

Yp=QsHsPsXp  (9)

where Xp and Yp are permuted versions of Y=[Y0 Y1 . . . YL-1]T and X=[X0 X1 . . . XL-1]T. The permutation process is described in detail in [6]. Ps, Hs, and Qs, are general pre-add, subfilter, and post-add matrices, which are described by equations (10-12).

Ps=ps,l0ps,l1ps,lW-2ps,lW-1(10)Hs=diag(PsH)andH=[H0H1HL-1]T(11)Qs=i=0W-1Bs,W-1-i,(12)

where Bs,i, which represents the post-add matrix at cascade stage i, is equal to

IlF0IlF1IFli-1Qs,i,Fi,

the number of subfilters generated by an li-by-li FFA, is 3 for li=2 and 6 for li=3. Qs,i is an expanded version of qs,li, where each element in the original matrix is replaced by an m-by-m matrix, m=L/(Πn=0iln). The rules for this replacement are as follows: each 1 is replaced by Im, each 0 is replaced by 0m, and each z−1 is replaced by the m-unfolded version of z−1. This type of transformation will be seen repeatedly in this paper, and will be referred to as an m-by-m delay unfolding transformation.

The L-by-L T&C FFA applies the same cascading process but uses both standard and T&C basic FFA structures. The reason both the standard and T&C basic FFA structures are used is that applying the T&C FFA on non-symmetrical filters does not produce symmetrical subfilters. Thus, there is no benefit to the additional cost of the T&C FFA when decomposing any subfilters that are not symmetrical. To minimize the overall system cost, it is prudent to use the T&C decomposition on only the symmetrical subfilters and the standard FFA decomposition on the non-symmetrical subfilters.

The literature [9] discusses the process of constructing an L-by-L T&C FFA, but does not provide an explicit mathematical model for the resulting filter. In this document, one such model is presented for the proposed FFA-based multirate architecture. This model can be easily generalized for the single rate T&C FFA.

SUMMARY OF THE INVENTION

According to a first aspect of the invention there is provided a method for filtering data samples comprising:

using a digital filter to act upon a input data stream in order to transform it into an output data stream, wherein:

the length of an impulse response of the digital filter is finite;

an impulse response of the digital filter is symmetric;

the operation of the digital filter is multi-rate;

using a polyphase decomposition to break down the input data stream into N parallel substreams;

the multi-rate digital filter being separated by a polyphase decomposition into multiple lower-rate sub-filters;

each of the sub-filters being separated one or more times into a set of simpler sub-sub-filters, a set of pre-filtering arithmetic structures, and a set of post-filtering arithmetic structures, according to a fast FIR filtering decomposition algorithm;

the set of sub-sub-filters comprising one or more pairs of sub-sub-filters which operate upon the same set of input samples and which have impulse responses which are jointly centro-symmetric;

and performing each such pair of sub-sub-filtering operations using a single shared filter structure, a set of pre-filtering combining adders, and a set of post-filtering separating adders.

Preferably the multi-rate digital filter is a digital interpolator and wherein a single pre-filtering arithmetic structure is used to generate the set of input data samples required by multiple sets of sub-sub-filters. That is multiple redundant pre-filtering arithmetic structures are simplified into a single pre-filtering arithmetic structure.

Preferably the order of the pre-filtering and post-filtering arithmetic structures is interchanged through a circuit transposition operation.

Preferably the filter is a digital decimator and a single post-filtering arithmetic structure is used to process the output samples from multiple sets of sub-sub-filters.

Preferably the order of the pre-filtering and post-filtering arithmetic structures is interchanged through a circuit transposition operation.

Preferably the fast FIR decomposition algorithm is a 2×2 decomposition as described in equation 6.

Preferably the fast FIR decomposition algorithm is a 3×3 decomposition as described in equation 8.

According to a second aspect of the invention there is provided a method for filtering data samples comprising:

using a digital filter to act upon a input data stream in order to transform it into an output data stream, wherein:

the length of an impulse response of the digital filter is finite;

an impulse response of the digital filter is symmetric;

the operation of the digital filter is multi-rate;

using a polyphase decomposition to break down the input data stream into N parallel substreams;

the multi-rate digital filter being separated by a polyphase decomposition into multiple lower-rate sub-filters;

each of the sub-filters being separated one or more times into a set of simpler sub-sub-filters, a set of pre-filtering arithmetic structures, and a set of post-filtering arithmetic structures, according to a fast FIR filtering decomposition algorithm;

wherein the multi-rate digital filter is a digital interpolator and wherein a single pre-filtering arithmetic structure is used to generate the set of input data samples required by multiple sets of sub-sub-filters.

According to a third aspect of the invention there is provided a method for filtering data samples comprising:

using a digital filter to act upon a input data stream in order to transform it into an output data stream, wherein:

the length of an impulse response of the digital filter is finite;

an impulse response of the digital filter is symmetric;

the operation of the digital filter is multi-rate;

using a polyphase decomposition to break down the input data stream into N parallel substreams;

the multi-rate digital filter being separated by a polyphase decomposition into multiple lower-rate sub-filters;

each of the sub-filters being separated one or more times into a set of simpler sub-sub-filters, a set of pre-filtering arithmetic structures, and a set of post-filtering arithmetic structures, according to a fast FIR filtering decomposition algorithm;

wherein the filter is a digital decimator and a single post-filtering arithmetic structure is used to process the output samples from multiple sets of sub-sub-filters.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is an illustration of a standard or prior art 2×2 filter having a FFA structure.

FIG. 1B is an illustration of a standard or prior art 2×2 filter having a T&C FFA structure.

FIG. 2A is an illustration of a standard or prior art polyphase upsample by 2 filter.

FIG. 2B is an illustration of a 2×2 FFA upsample by 2 filter which clearly shows the coefficents of the individual sub-subfilters.

FIG. 2C is an illustration of a 2×2 FFA upsample by 3 filter.

FIG. 3A is an illustration of a standard or prior art 2×2 filter having a T&C FFA structure.

FIG. 3B is an illustration of a 2×2 filter having a transposed T&C FFA structure.

FIG. 4A is an illustration of a standard or prior art polyphase upsample by 2 filter.

FIG. 4B is an illustration of a 6×6 FFA upsample by 2 filter.

FIG. 4C is an illustration of a 6×6 FFA downsample by 2 filter.

FIG. 5 is an illustration of a 12×12 filter having a T&C FFA structure.

FIG. 6 is an illustration comparing the multiplier usage of the proposed structure to that of the standard or prior art parallel structure for a variety of parallelism factors.

FIG. 7 is a Table 1 which indicates the number of pre-adders and post-adders required for various transposed and non-transposed FFA structures.

FIG. 8 is a Table 2 which compares the computational complexity of the proposed structure and the standard or prior art parallel structure for a number of example filters.

DETAILED DESCRIPTION

Sample rate converters are a special class of multirate FIR filters. Two main types of sample rate converters exist: interpolators and decimators. Since a decimator can easily be obtained by transposing the signal flow graph of an interpolator [14], the discussion which follows concentrates on interpolators.

The polyphase decompostion of a single-input 1-to-M interpolator [15] is expressed in the z-domain as shown below.

Y(z)=H(z)X(zM)=i=0M-1z-iHi(zM)X(zM)=i=0M-1z-iYi(zM),(13)

where

Hi(zM)=j=0K-1hi+jNz-jM

for N=KM. If the interpolator receives more than one input sample on every clock cycle, a specialized filter structure is required for the implementation. This paper proposes an FFA-based architecture that reduces the multiplier and adder requirements for symmetrical FIR sample rate converters. In the case of an L-parallel 1-to-M FFA based interpolator, the structure is developed as follows:

Step 1: Apply the polyphase decomposition technique described by equation (13) to the FIR interpolator. This decomposition results in M polyphase subfilters.

Step 2: Apply an L-by-L FFA decomposition to each polyphase subfilter, thereby breaking it down into multiple FFA subfilters (also referred to herein as sub-sub-filters).

Step 3: Since each polyphase subfilter receives the same L-parallel input data, only one copy of the FFA pre-add section is required, as shown in FIG. 2c. M−1 redundant copies of the pre-add structure may be removed. Note that M copies of the post-add structure are required, one for each polyphase subfilter.

The first optimization, which may be used to reduce the total number of multipliers required to implement the filter, will be introduced through an example.

Consider the construction of a 2-parallel version of a 1-to-2 interpolator using the procedure described above. In this example, the symmetrical interpolation filter is 16 taps long, with the coefficients defined as h0, h1, . . . , h7, h7, h6, . . . , h0. Performing a polyphase decomposition will result in two polyphase subfilters, H0 and H1, which will contain the odd and even coefficients of the original prototype filter, respectively. Since two input samples are received every clock cycle, the 2-by-2 T&C FFA is applied to decompose each polyphase subfilter Hi, into three 4-tap FFA subfilters (Hi,j), where i represents the polyphase subfilter numbering and j represents the FFA subfilter numbering.

FIG. 2b shows the coefficients of the 4-tap FFA subfilters, which are represented as hi,j,0, . . . , hi,j,3. It can be seen from the figure that none of the FFA subfilters is symmetrical. However, FFA subfilters H0,0 and H1,0 contain the same set of coefficents but in the opposite order (h0,0,0=h0,0,3, . . . , h0,0,3=h1,0,0). Furthermore, these two subfilters take the exact same input (shown as Xa in the figure). In [15], Mou showed that it is possible to exploit this centrosymmetry as follows in order to implement the two filters using four multipliers and eight adders, instead of the eight multipliers and six adders required by the straightforward implementation.

[Y0,0(n)Y1,0(n)]=[H0,0H1,0]Xa=[h0,0,0h0,0,1h0,0,2h0,0,3h1,0,0h1,0,1h1,0,2h1,0,3][xa,n+xa,n-3xa,n-1+xa,n-2xa,n-1-xa,n-2xa,n-xa,n-3]=A[c0c10000d0d1][I2J2J2-I2][xa,nxa,n-1xa,n-2xa,n-3](15)=A[c0c10000d0d1]DXa(16)(14)

where

A=[111-1],

ci=(H0,0[i]+H1,0[i])/2, di=(H0,0[i]−H1,0[i])/2 and I2 and J2 represent the 2-by-2 identity and counter identity matrices, respectively. Notice that the original filtering operations have been broken down into a set of pre-filtering combining adders (represented by matrix D), a simpler filtering operation, and a set of post-filtering separating adders (represented by matrix A.

Similarly, the coefficients used by FFA subfilter H1,1 are the reversed and negated versions of those used by H0,1. This subfilter pair may also be computed using equation (15) with the following minor substitution:

A=[11-11].

Note that the subfilters H0,2 and H1,2 are not symmetrical, so they must be implemented using one multiplier per coefficient.

Next, consider the case of a 2-parallel 1-to-3 FFA-based interpolator, as shown in FIG. 2c. If the FFA subfilter coefficients are explicitly decomposed as was done in FIG. 2b for the 1-to-2 case, it will be apparent that some centrosymmetric FFA subfilter pairs exist between the polyphase subfilters H0 and H2. Additionally, some of the FFA subfilters arising from interpolator subfilter H1 are individually symmetrical, and may therefore be implemented in the typical way to reduce the multiplier usage by half.

In general, for any L-by-L FFA based symmetrical interpolator or decimator, centro-symmetric FFA subfilter pairs exist between the T&C FFAs of the polyphase subfilters Hi and HM+1−i, where i=1, 2, . . . , └M/2┘−1. If M is odd, the polyphase subfilter H(M−1)/2+1 will generate some symmetrical FFA subfilters. By exploiting both forms of symmetry, it is possible to reduce the multiplier cost of multirate FFA implementations. Note that a derivation of the multiplier costs of various composite FFAs is provided hereinafter.

It is well-known [14] that if the signal flow graph of a single-rate linear system is transposed, the functionality of the system is unchanged. This process can be applied to any FFA decomposition in order to generate an alternate structure. For example, consider FIGS. 3a and 3b, which show the 2×2 T&C FFA in the normal and transposed formats. Although these two systems are functionally identical, they clearly use different pre and post adder structures. It is apparent from FIG. 3 that the typical 2×2 T&C FFA requires 2 pre adders and 4 post adders, whereas the transposed structure requires 3 pre adders and 3 post adders.

In general, the effect of transposition on an FFA is to transfer some of the adders from the post adder structure into the pre adder structure. Table 1 summarizes the pre and post adder requirements for a variety of FFA structures. Note that the FFA subfilters are unaffected by transposition.

It is apparent from Table 1 that transposition does not change the logic resources required to implement a single rate FFA, as the increase in pre adder resources is exactly balanced by a decrease in post adder resources. However, this is not the case for multirate FFAs. To illustrate this fact, consider the case of a 1-to-2 interpolator with 6 parallel inputs, shown in FIG. 4. After each of the polyphase subfilters from FIG. 4a is converted into a 6×6 FFA, the interpolator requires 2 copies of the 6×6 post adder structure, but only one copy of the 6×6 pre adder structure, as indicated in FIG. 4b. The 6×6 pre and post adders themselves require three copies of the 2×2 T&C structure, two copies of the 3×3 T&C structure, and one copy of the standard 3×3 structure. Referring to Table 1 for the individual costs, the total number of pre and post adders required if non-transposed structures are used is 105. If the transposed structures are used instead for the individual FFAs, only 93 pre and post adders are needed, representing a cost reduction of 12 adders.

In general, 1-to-M interpolators require M copies of the post adder structure and only 1 copy of the pre adder structure. As a result, the most economical implementation for an interpolator is achieved through the transposed architecture, which transfers some of the complexity from the post adder structure to the pre adder structure. Conversely, the non-transposed architectures result in more economical implementations for decimators, due to the fact that M-to-1 decimators require M copies of the pre adder structure and only 1 copy of the post adder structure, as indicated in FIG. 4c. The number of adders saved by using the optimal transpostion increases as the rate change factor M and the parallelism L increase.

When transposition is performed, the updated pre and post adder matrices may be found through the following procedure:

1) Set post adder matrix to transpose of original pre adder matrix

2) Set pre adder matrix to transpose of original post adder matrix

3) Reverse order of rows in post adder matrix

4) Reverse order of columns in pre adder matrix

An L-parallel 1-to-M FFA interpolator may be represented mathematically as follows:

Yp=[Yp,0Yp,1Yp,M-1]=[QcQcQc]diag[Hc,0Hc,1Hc,M-1]PcXp(17)

where M is the upsmapling factor, Qc is the post-adder matrix of an L-by-L FFA, Yp,i is a permuted version of the output of an L-by-L FFA performed on the ith polyphase subfilter, Hc,i is an L-by-L FFA subfilter matrix derived from the ith polyphase subfilter, Pc is the pre-adder matrix of an L-by-L FFA and Xp is the permuted version of the input of the L-by-L FFA or FFA interpolator.

The derivation of each of these quantities is described in detail in the following sections.

1) Derive Pre-Add Matrix:

As shown in equation 10, the pre-adder matrix of a composite L-by-L standard FFA is constructed by forming the tensor product of the pre-adder matrices of each of the elementary (2-by-2 or 3-by-3) FFAs. However, the expression for the pre-adder matrix of an L-by-L T&C FFA is more complex.

To illustrate, consider a 6-by-6 FFA implemented by cascading 2-by-2 and 3-by-3 FFAs. The pre-adder matrix for a 6-by-6 was developed hereinbefore, and is shown in equation 19. In the case of a symmetrical filter, the 6-by-6 T&C FFA is developed as follows.

The first cascading stage of 6-by-6 T&C FFA involves a 2-by-2 T&C FFA, which breaks down the original filter into two symmetrical and one non-symmetrical FFA subfilters. The second stage of the decomposition involves using a 3-by-3 FFA to further decompose each of the subfilters from the first stage. When decomposing the symmetrical subfilters, the T&C FFA is used. However, since one of the subfilters is not symmetrical, it will not yield any symmetrical subfilters when decomposed. Therefore, it is preferable to use the less expensive standard FFA when decomposing the non-symmetrical filter.

In order to derive an expression for the 6-by-6 T&C FFA, it is useful to note that the first two rows of the pre-adder matrix pc,2 generate inputs for the symmetrical subfilters, whereas the third row generates an input for the non-symmetrical subfilter. Since these two sets of subfilters are to be decomposed in different ways, a technique for mathematically separating the rows of pc,2 is needed. This paper introduces two new matrices for this purpose: Sc,2=diag[1 1 0] extracts the rows which correspond to symmetrical subfilters, and Ss,2=diag[0 0 1] extracts the rows which correspond to non-symmetrical subfilters. Similarly, two other matrices Sc,3=diag[0 0 1 1 1 1] and Ss,3=[1 1 0 0 0 0] are introduced to extract the rows from pc,3 related to symmetrical and non-symmetrical 3-by-3 T&C FFA subfilters, respectively. The 6-by-6 T&C pre-adder matrix is generated by applying the T&C 3-by-3 FFA to the symmetrical portion of pc,2 and the standard 3-by-3 FFA to the non-symmetrical portion of pc,2, as shown in equation 18.

Pc,6=[Ss,2×pc,2]pc,3+[Sn,2×pc,2]ps,3  (18)

Ps,6=pc,2ps,3  (19)

Extending the example one step further, a 12-by-12 FFA may be viewed as a cascade of 2-by-2 and 6-by-6 FFAs as shown in FIG. 5. As in the previous example, after performing the initial 2-by-2 decomposition, one of the subfilters is non-symmetrical, and is therefore best suited to a standard FFA decomposition. Thus, as shown in equation 20, the derivation of a 12-by-12 T&C FFA requires both the 6-by-6 standard and T&C FFAs. A graphical representation of the filter structure is provided in FIG. 5.

Pc,12=[Ss,2×pc,2]Pc,6+[Sn,2×pc,2]Ps,6  (20)

In general, the derivation of the pre-adder matrix for a composite T&C FFA involves an iterative process that starts from the final cascading stage, W−1. The first step of the iterative process defines the T&C pre-adder matrix Pc,lW−1 and standard pre-adder matrix Ps,lW−1 as shown in equation 21.

Pc,lW−1=pc,lW−1 and Ps,lW−1=ps,lW−1  (21)

For the subsequent iterations, j=W−2, W−3, . . . , 0, the pre-adder matrices of both b-by-b T&C and standard FFAs, where b=Πi=jW−1li are computed as shown in equations 22 and 23, respectively.

Pc,b=[Sc,lj×pc,lj]Pc,b′+[(Sn,lj×pc,lj]Ps,b′,  (22)

Ps,b=Ps,ljps,lj+1 . . . ps,lW−2ps,lW−1  (23)

where b′=b/lj. The final pre-adder matrix, Pc, is equal to Pc,L.

2) Derive Subfilter Matrix:

The subfilter matrix Hc,m, for m=0, 1, . . . , M−1, which represents the FFA subfilters of mth polyphase subfilter H, is given as

Hc,m=Gc×Pc×Hm,  (24)

where Gc is the gain of the FFA.

The gain matrix Gc is derived through the same iterative process used to derive the pre-adder matrix, explained in −1. The first iterative step, j=W−1, starts with gain matrices of both T&C and standard FFAs from the final cascading stage, as given below.

Gc,lW−1=gc,lW−1 and Gs,lW−1=gs,lW−1  (25)

For the subsequent iterations, j=W−2, W−3, . . . , 0 the gain matrices of both b-by-b standard and T&C sections are determined using equations 26 and 27.

Gs,b=gs,ljgs,lj+1 . . . gs,lW−2gs,lW−1  (26)

Gc,b=[Sc,lj×gc,lj]Gc,b′+[(Sn,lj×gc,lj]Gs,b′,  (27)

The final gain matrix, Gc, is equal to Gc,L.

3) Derive Post-Add Matrix:

The procedure for computing the post-adder for a composite standard FFA was previously provided in equation 12. Applying this procedure to a 6-by-6 standard FFA yields the result shown in equation 28 below.

Qs,6=Bs,1(6)×Bs,0(6), where  (28)

Bs,0(6)=I3qs,3  (29)

Bs,1(6)=Qs,2(6),  (30)

where Qs,26 is generated by performing a 3-by-3 delay unfolding transformation on matrix qs,2. Note that in this section, the superscript (x) is used to indicate that the matrix in question belongs to an x-by-x FFA, and does not imply any mathematical operations. Thus, the matrix Bs,0(6) is identical to the matrix Bs,0. This superscript notation is used only to clarify the examples discussed in this section, and is not used for generalized L-by-L FFA derivation which follows.

The derivation of 6-by-6 T&C post-add matrix is more complex because both the T&C and standard post-add matrices are involved. As shown in FIG. 4b, the overall post-adder structure for this filter may be broken up into two stages. The first stage of post-adders connects directly to the 18 FFA subfilters and corresponds to the final (3-by-3) stage of the cascaded FFA decomposition. The first two sets of 6 subfilters were generated by applying the 3-by-3 T&C FFA to two symmetrical subfilters from the first cascading stage, so the corresponding post-adders use the T&C structure. The final set of 6 subfilters was generated by applying the 3-by-3 standard FFA to the non-symmetrical subfilter from the first cascading stage, so its post adder uses the standard FFA structure. The output of the first stage of the post-add section is represented mathematically as shown in Equation 32. In the second post-adder stage, which is represented by equation 33, the output of the 3-by-3 post-adder structures are connected to three 2-by-2 T&C post-adder structures.

Qc,6=Bc,1(6)×Bc,0(6), where  (31)

Bc,0(6)=(Sc,2qc,3)+(Ss,2qs,3)  (32)

Bc,1(6)=Qc,2(6),  (33)

where Qc,2(6) is generated by performing a 3-by-3 delay unfolding transformation on qc,2.

The 12-by-12 post-add matrices of standard and T&C FFAs are given in equations 34 and 38 respectively.

Qs,12=Bs,2(12)×Bs,1(12)×Bs,0(12), where  (34)

Bs,0(12)=I3(I3qs,3)=I3Bs,0(6)  (35)

Bs,1(12)=I3Qs,2(6)  (36)

Bs,2=Qs,2(12)  (37)

where Qs,2(12) is generated by performing a 6-by-6 delay unfolding transformation on qs,2.

Qc,12=Bc,2(12)×Bc,1(12)×Bc,0(12), where  (38)

Bc,0(12)=(Sc,2Bc,0(6))+(Ss,2Bs,0(6))  (39)

Bc,1(12)=(Sc,2Qc,2(6))+(Ss,2Qs,2(6))  (40)

Bc,2(12)=Qc,2(12)  (41)

where Qc,2(12) is generated by performing a 6-by-6 delay unfolding transformation on qc,2.

The derivation of generalized L-by-L T&C post-add matrix Qc is expressed as

Qc=i=0W-1Bc,W-1-i,(42)

where Bc,W−1−i is derived below. From the above examples, it is clear that the derivation of Bc,W−1−i involves an iterative process.

The first iterative step (j=0) defines two matrices Bc,i,j=Qc,li and Bs,i,j=Qs,li, where Qc,li and Qs,li are generated by performing L/(Πn=0iln)-by-L/(Πn=0iln) delay unfolding transfor-mations on matrices qc,li and (qs,li), respectively.

The subsequent iterative steps (j=1, . . . , i) are defined as follows.

Bc,i,j=(Sc,li−jBc,i,j−1)+(Sn,li−jBs,i,j−1),  (43)

In eqn (43), Bs,i,j−I is obtained as given below.

Bs,i,j=IFiBs,i,j−1,  (44)

where Fi=3 for li−j=2 and Fi=6 for li−j=3. The matrix Bc,W−1−i is equal to Bc,i,i

The resource usage of the proposed technique may be analyzed in three main sections: the subfilters, the polyphase combiner adders (in the case of a decimator), and the FFA pre/post adders. Considering the subfilters first, when a multirate filter is implemented using the proposed scheme, the total number of subfilters may be determined as follows:

F=Mi=1WFi(45)

where Fi, the number of subfilters generated by the i'th FFA, is 3 for a 2×2 FFA and 6 for a 3×3 FFA. Each of the subfilters has N/LM coefficents. Of these subfilters, a fraction equal to (⅔)W are either individually symmetric or jointly centrosymmetric, with the remainder being asymmetric. As previously discussed, it is possible to exploit either type of symmetry in order to reduce the required multiplier resources by half. Thus, the total number of multipliers required to implement the filter is:

P=(23)WN2Li=1WFi+(1-(23)W)NLi=1WFi(46)

The number of adders typically required to implement an FIR subfilter is one less than the number of filter coefficients. In order to exploit the symmetry in the jointly centrosymmetric subfilters, one additional adder is required per subfilter. Thus, the total number of adders required for the subfilters is:

Asf=(NLM-1+(23)W)Mi=1WFi(47)

In the case of a decimator, the most efficient implementation is generated by placing the adders associated with the polyphase combiner right after the subfilters and before the FFA post adders, as shown in FIG. 4c. In this case, the required number of polyphase combiner adders is:

Apph=(M-1M)(Mi=1WFi)=(M-1)i=1WFi(48)

When constructing a single-rate composite FFA larger than 2×2 or 3×3, multiple copies of the standard 2×2 or 3×3 pre and post adder structures are required. The exact number of copies depends on the sequence of FFA decompositions used to construct the composite filter. At each stage of the decomposition, Ci, the number of copies required, may be determined based on the number of inputs to the pre adder stage as follows:

Ci=LLi(k=1i-1FkLk)(49)

As previously discussed, the T&C FFA structure is used when decomposing filters that are symmetric or jointly centrosymmetric, while the standard FFA decomposition is used for asymmetric filters. Thus, the fraction of the pre and post adder copies which use the T&C structure in the i'th stage of the FFA decomposition is ⅔i−1. The standard FFA structure is used for the remaining copies.

For multirate FFA structures, the total pre and post adder cost depends on whether the filter is an interpolator or a decimator. M copies of the pre adder structure are required for decimators, while M copies of the post adder structure are required for interpolators. Thus, the required numbers of pre and post adders for the proposed interpolator and decimator structures are given by equations 50 and 51, respectively:

Affa_int=i=1rCi[(2/3)i-1(AC_prei+MAC_posti)+(1-(2/3)i-1)(ASprei+MAS_posti)](50)Affa_dec=i=1rCi[(2/3)i-1(MAC_prei+AC_posti)+(1-(2/3)i-1)(MASprei+AS_posti)](51)

where AS_prei, AS_posti, AC_prei, and AC_posti refer to the number of adders in the standard/T&C pre/post adder structure used for the FFA decomposition at stage i. These values are listed in Table 1.

The typical way to implement a multirate filter at sampling rates higher than the system clock rate is to extend the parallel filtering approach described in [6]. Such an approach would involve breaking down each of the M polyphase filter branches into L2 subfilters. Since each pair of subfilters is jointly centrosymmetric in this case, the total number of multipliers required is

NL2.

The total number of adders required is NL−LM for interpolators and NL−L for decimators.

Table 2 compares the required computational resources of the parallel and proposed techniques for a variety of multirate filters. Note that in the “Saved Adders” column, the number without parentheses represents the total difference between the proposed approach and the parallel approach, whereas the number in parentheses represents the saving achieved by using the optimized transposed architecture.

It is clear from equation 46 and Table 2 that the number of multipliers saved by the proposed approach does not depend on the rate change factor M. Rather, the multiplier savings are determined solely by the parallelism factor L. As the parallelism increases, the multiplier savings relative to the parallel case also increases, as highlighted in FIG. 6. Thus, higher levels of parallelism are desirable from a resource utilization perspective, although there is a tradeoff in terms of increased design complexity.

It should be noted that the proposed approach is not limited to cases where the signal's sampling frequency exceeds the system clock frequency. In situations where the converse is true, this technique may be applied in order to trade logic resource consumption or chip area for a reduction in dynamic power consumption. The application of the proposed technique will reduce the operating rate of the multipliers, thereby requiring more discrete multipliers in order to perform the operation. However, the total number of multiplications performed by the system per unit of time will be reduced according to the relationship shown in FIG. 6, resulting in a corresponding reduction in the dynamic power consumed by the module.

The arrangements herein provide a technique for applying Fast-FIR filtering to upsampling and downsampling filters, resulting in a reduction in the computational complexity and hardware implementation costs of such filters. The technique allows for the exploitation of symmetry in the prototype filter coefficients, which allows for a further reduction in the number of multipliers required to construct the filters.

The structure and computational complexity of the derived multirate Fast FIR filters may be modified by transposing the signal flow graphs of the individual Fast-FIR decompositions, allowing some duplicate pre- and post-adder sections to be combined. In the case of an upsampler, the transposed version of the filter results in a more economical hardware implementation. Conversely, the non-transposed filter structure is more economical for downsamplers.

Furthermore, the arrangements herein provide a series of generalized equations describing the operation of the symmetrical FIR exploitation scheme originally presented by T&C and utilized in the present technique. Such equations were not previously available in the public literature. These equations simplify the application of the T&C FIR technique for arbitrary numbers of parallel inputs.

Read more
PatSnap Solutions

Great research starts with great data.

Use the most comprehensive innovation intelligence platform to maximise ROI on research.

Learn More

Patent Valuation

$

Reveal the value <>

17.0/100 Score

Market Attractiveness

It shows from an IP point of view how many competitors are active and innovations are made in the different technical fields of the company. On a company level, the market attractiveness is often also an indicator of how diversified a company is. Here we look into the commercial relevance of the market.

27.0/100 Score

Market Coverage

It shows the sizes of the market that is covered with the IP and in how many countries the IP guarantees protection. It reflects a market size that is potentially addressable with the invented technology/formulation with a legal protection which also includes a freedom to operate. Here we look into the size of the impacted market.

70.21/100 Score

Technology Quality

It shows the degree of innovation that can be derived from a company’s IP. Here we look into ease of detection, ability to design around and significance of the patented feature to the product/service.

51.0/100 Score

Assignee Score

It takes the R&D behavior of the company itself into account that results in IP. During the invention phase, larger companies are considered to assign a higher R&D budget on a certain technology field, these companies have a better influence on their market, on what is marketable and what might lead to a standard.

15.0/100 Score

Legal Score

It shows the legal strength of IP in terms of its degree of protecting effect. Here we look into claim scope, claim breadth, claim quality, stability and priority.

Citation

Patents Cited in This Cited by
Title Current Assignee Application Date Publication Date
Method and Apparatus For Hybrid Digital Filtering TOROSYAN, ARTHUR 03 December 2014 26 March 2015
See full citation <>

More Patents & Intellectual Property

PatSnap Solutions

PatSnap solutions are used by R&D teams, legal and IP professionals, those in business intelligence and strategic planning roles and by research staff at academic institutions globally.

PatSnap Solutions
Search & Analyze
The widest range of IP search tools makes getting the right answers and asking the right questions easier than ever. One click analysis extracts meaningful information on competitors and technology trends from IP data.
Business Intelligence
Gain powerful insights into future technology changes, market shifts and competitor strategies.
Workflow
Manage IP-related processes across multiple teams and departments with integrated collaboration and workflow tools.
Contact Sales
Clsoe
US10003324 Fast FIR filtering technique 1 US10003324 Fast FIR filtering technique 2 US10003324 Fast FIR filtering technique 3