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Patent Analysis of

High-precision analog-to-digital converter and DNL-based performance improvement method

Updated Time 12 June 2019

Patent Registration Data

Publication Number

US10003352

Application Number

US15/559055

Application Date

08 June 2015

Publication Date

19 June 2018

Current Assignee

CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE

Original Assignee (Applicant)

CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE

International Classification

H03M1/12,H03M1/46,H03M1/80,H03M1/06,H03M1/42

Cooperative Classification

H03M1/468,H03M1/0678,H03M1/1061,H03M1/1245,H03M1/42

Inventor

LI, TING,HU, GANGYI,JIANG, HEQUAN,LI, RUZHANG,HUANG, ZHENGBO,ZHANG, YONG,CHEN, GUANGBING,WANG, YUXIN,FU, DONGBING

Patent Images

This patent contains figures and images illustrating the invention and its embodiment.

US10003352 High-precision analog-to-digital converter DNL-based 1 US10003352 High-precision analog-to-digital converter DNL-based 2 US10003352 High-precision analog-to-digital converter DNL-based 3
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Abstract

The present invention provides a high-precision analog-to-digital converter, includes a redundant weight capacitor array, a comparator, a code reestablishment circuit, a weight storage circuit and a control logic circuit. The redundant weight capacitor array collects input voltages and generates output voltages in a sampling stage. The comparator compares the output voltages of the redundant weight capacitor array. The code reestablishment circuit calculates an output code of the successive approximation type analog-to-digital converter according to the comparator output result and a capacitor weight in the weight storage circuit. The weight storage circuit stores the capacitor weight. The control logic circuit controls the sampling and conversion stages of the redundant weight capacitor array. The present invention also provides a DNL-based performance improvement method adapted to the analog-to-digital converter.

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Claims

1. A high-precision analog-to-digital converter, comprising a redundant weight capacitor array, a comparator, a code reestablishment circuit, a weight storage circuit and a control logic circuit; wherein the redundant weight capacitor array receives external input voltages Vin+ and Vin−, generates output voltages Vout+ and Vout− under the control of the control logic circuit, supplies the output voltages Vout+ and Vout− to the comparator for comparison, and controls each bit of capacitor to participate in a voltage addition and subtraction operation in sequence under the control of the control logic circuit according to a comparison result of the comparator to regenerate output voltages Vout+ and Vout− which are supplied to the comparator for comparison, repeating as such until a last bit of capacitor completes the voltage addition and subtraction operation, and the redundant weight capacitor array is combined with the weight storage circuit to implement digital correction of a capacitor mismatch error, thereby preventing code missing for the analog-to-digital converter; the comparator compares the output voltages Vout+ and Vout− of the redundant weight capacitor array, outputs 1 if Vout+ is more than Vout−, or else, outputs 0; the code reestablishment circuit calculates an output code of the successive approximation type analog-to-digital converter according to an output result of the comparator and an actual capacitor weight extracted according to DNL in the weight storage circuit; the weight storage circuit stores the actual capacitor weight extracted according to DNL; and the control logic circuit controls the redundant weight capacitor array to collect the input voltages in a sampling stage and controls a corresponding weight capacitor of the redundant weight capacitor array to implement the voltage addition and subtraction operation according to the output result of the comparator in a conversion stage.

2. The high-precision analog-to-digital converter according to claim 1, wherein the redundant weight capacitor array comprises n bits of effective capacitors and at least r bits of redundant capacitors, and the number of capacitors included in each bit of the effective capacitor and redundant capacitor is an integral multiple of 2, wherein an nth bit of effective capacitor is Cn, an (n−1)th bit of effective capacitor is Cn-1, . . . , a first bit of effective capacitor is C1, Cn is a highest weight effective capacitor with the weight of Wn, C1 is the lowest weight effective capacitor with the weight of W1; and an rth bit of redundant capacitor is C′r, an (r−1)th bit of redundant capacitor is C′r-1, . . . , a first bit of redundant capacitor is C′1, C′r is a highest weight redundant capacitor with the weight of W′r, C′1 is a lowest weight redundant capacitor with the weight of W′1, the redundant weight capacitor array may comprise one or more bits of redundant capacitors from C′r, . . . , C′1 for analog-to-digital conversion, and at least one bit of redundant capacitor is present at each redundant weight.

3. The high-precision analog-to-digital converter according to claim 2, wherein the redundant capacitors are located behind the effective capacitors having the same weight as the redundant capacitors.

4. The high-precision analog-to-digital converter according to claim 2, wherein a maximum capacitor mismatch error determined by a process and a circuit structure is Nmismatch_max LSB, and a minimum redundant weight number required by the redundant weight capacitor array is Nr_min=1+log2(Nmismatch_max).

5. The high-precision analog-to-digital converter according to claim 1, wherein the redundant weight capacitor array and the comparator simultaneously employ a differential structure for connection or simultaneously employ a single-end structure for connection.

6. A DNL-based performance improvement method, the method being adapted to a high-precision analog-to-digital converter, comprising the following steps: receiving external input voltages Vin+ and Vin− for sampling, generating output voltages Vout+ and Vout− after sampling and supplying the output voltages Vout+ and Vout− to a comparator for comparison, by a redundant weight capacitor array; comparing the output voltages Vout+ and Vout− by the comparator to obtain a comparison output result; controlling a corresponding weight capacitor of the redundant weight capacitor array according to the comparison output result to perform a voltage addition and subtraction operation, regenerating output voltages Vout+ and Vout− and supplying the output voltages Vout+ and Vout− to the comparator for comparison, by a control logic circuit, repeating as such until a lowest weight bit of capacitor completes the voltage addition and subtraction operation, and implementing digital correction for a capacitor mismatch error by the redundant weight capacitor array in combination with a weight storage circuit to prevent code missing for the analog-to-digital converter; and storing each comparison output result, reading an actual capacitor weight extracted according to DNL in the weight storage circuit and calculating an output code of the successive approximation type analog-to-digital converter, by a code reestablishment circuit.

7. The DNL-based performance improvement method according to claim 6, wherein after the redundant weight capacitor array performs sampling, the output voltage Vout+ is equal to βVin+, the output voltage Vout− is equal to βVin−, and the comparator compares a first output of the output voltages Vout+ and Vout− to obtain a comparison output result Dn; the control logic circuit controls an effective capacitor Cn to perform the voltage addition and subtraction operation according to the comparison output result Dn to obtain a second output of Vout+ and Vout−; and the comparator compares the second output of the output voltages Vout+ and Vout− to obtain a comparison output result Dn-1, repeating as such until a lowest weight bit of capacitor completes the voltage addition and subtraction operation.

8. The DNL-based performance improvement method according to claim 7, wherein if the comparison output result Dn is 1, an output voltage of an nth effective capacitor after operation is:

[(Vout+)-(Vout-)]n=[(Vout+)-(Vout-)]0-βVrefWnk=i+1nWk;

if the comparison output result Dn is 0, an output voltage of the nth effective capacitor after operation is:

[(Vout+)-(Vout-)]n=[(Vout+)-(Vout-)]0-βVrefWnk=i+1nWk;

and Cn, Cn-1, . . . , Cr, C′r, Cr-1, C′r-1, . . . , C1, C′1 sequentially perform the voltage addition and subtraction operation in turn, wherein β is a ratio of a sum of sampling capacitors to a sum of all the capacitors; β=k=i+1nWKk=1nCk+k=1rCk.

9. The DNL-based performance improvement method according to claim 6, wherein the code reestablishment circuit calculates the output code of the successive approximation type analog-to-digital converter with a formula as follows:

Dout=WnDn+Wn-1Dn-1+ . . . +WrDr+W′rD′r+ . . . +W1D1+W′1D′1 wherein Wn, Wn-1, . . . , Wr, W′r, . . . , W1, W′1 are capacitor weights stored in the weight storage circuit, and Dn, Dn-1, . . . , Dr, D′r, D1, D′1 are comparison output results of the comparator.

10. The DNL-based performance improvement method according to claim 6, wherein extraction of the actual capacitor weight extracted according to DNL, stored in the weight storage circuit, comprises the following steps: setting a capacitor weight initial value in the weight storage circuit as an ideal weight; turning off all the redundant capacitors and then performing analog-to-digital (A/D) conversion to obtain a first output sequence code of the code reestablishment circuit; calculating a first DNL sequence of the analog-to-digital converter according to the first output sequence code; extracting actual weights of effective capacitors according to the first DNL sequence; turning off the effective capacitors corresponding to all the redundant capacitors and then performing A/D conversion to obtain a second output sequence code of the code reestablishment circuit; calculating a second DNL sequence of the analog-to-digital converter according to the second output sequence code; and extracting actual weights of the redundant capacitors according to the second DNL sequence.

11. The DNL-based performance improvement method according to claim 10, wherein the setting a capacitor weight initial value in the weight storage circuit as an ideal weight specifically comprises: setting a significant bit weight, with a jth significant bit weight Wj=2j-1, wherein j=1, 2, . . . , n; and setting a redundant bit weight, with a kth redundant bit weight W′k=Wk=2k-1, wherein k=1, 2, . . . , r.

12. The DNL-based performance improvement method according to claim 10, wherein the extracting actual weights of effective capacitors according to the first DNL sequence specifically comprises the following steps: restoring according to the first DNL sequence to obtain an input output relation of the analog-to-digital converter as follows:

Ain(x)=j=1xA(j)=x+j=1xDNL(j),

 wherein Ain(x) is an analog input voltage increment corresponding to a digital code x; extracting a weight of an nth effective capacitor as follows:

Wn=12n-1-2Ne(n)[j=2n-1+Ne(n)2n-Ne(n)Ain(j)-j=Ne(n)2n-1-Ne(n)Ain(j)],

 wherein Ne(n) is a number of rejection points determined by a process mismatch; assuming a maximum mismatch determined by a process variation is e %, Ne(n) is a rounded product of 2n*e % in the calculation of an nth bit of capacitor weight, i.e. Ne(n)=int(2n×e %); extracting a weight Wn-1 of an (n−1)th bit of effective capacitor as follows:

W(n-1)1=12n-2-2Ne(n-1)[j=2n-2+Ne(n-1)2n-1-Ne(n-1)Ain(j)-j=Ne(n-1)2n-2-Ne(n-1)Ain(j)]

W(n-1)2=12n-2-2Ne(n-1)[j=2n-2+Ne(n-1)+2n-12n-1-Ne(n-1)+2n-1Ain(j)-j=Ne(n-1)+2n-12n-2-Ne(n-1)+2n-1Ain(j)]

W(n-1)=12[W(n-1)1+W(n-1)2],

wherein Ne(n−1)=int(2n-1×e %); extracting a weight Wm of an mth bit of effective capacitor as follows:

Wm1=12m-1-2Ne(m)[j=2m-1+Ne(m)2m-Ne(m)Ain(j)-j=Ne(m)2m-1-Ne(m)Ain(j)]

Wm2=12m-1-2Ne(m)[j=2m-1+Ne(m)+2m2m-Ne(m)+2mAin(j)-j=Ne(m)+2m2m-1-Ne(m)+2mAin(j)]

Wm(2n-m)=12m-1-2Ne(m)[j=2m-1+Ne(m)+(2n-m-1)2m2m-Ne(m)+(2n-m-1)2mAin(j)-j=Ne(m)+(2n-m-1)2m2m-1-Ne(m)+(2n-m-1)2mAin(j)]

Wm=12n-mj=12n-mWmj;

repeating as such to extract all capacitor weights remained after the mth capacitor; if the capacitor weights of the capacitors after the mth capacitor as determined by the process variation have no effect on the monotonicity of the capacitor array, a mismatch error of a capacitor with the weight of less than Wm is negligible, and the weight of the capacitor is an ideal weight.

13. The DNL-based performance improvement method according to claim 10, wherein the extracting actual weights of redundant capacitors according to the second DNL sequence specifically comprises the following steps: restoring according to the second DNL sequence to obtain an input output relation of the analog-to-digital converter as follows:

Ain(x)=j=1xA(j)=x+j=1xDNL(j),

 wherein A′in(x) is an analog input voltage increment corresponding to a digital code x; extracting a weight Wr′ of an r′th redundant capacitor as follows:

Wr1=12r-1-2Ne(r)[j=2r-1+Ne(r)2r-Ne(r)Ain(j)-j=Ne(r)2r-1-Ne(r)Ain(j)]

Wr2=12r-1-2Ne(r)[j=2r-1+Ne(r)+2r2r-Ne(r)+2rAin(j)-j=Ne(r)+2r2r-1-Ne(r)+2rAin(j)]

Wr(2n-r)=12r-1-2Ne(r)[j=2r-1+Ne(r)+(2n-r-1)2r2r-Ne(r)+(2n-r-1)2rAin(j)-j=Ne(r)+(2n-r-1)2r2r-1-Ne(r)+(2n-r-1)2rAin(j)]

Wr=12n-rj=12n-rWrj;

repeating as such to extract all capacitor weights remained after the r′th capacitor; if the capacitor weights of the capacitors after the mth capacitor as determined by the process variation have no effect on the monotonicity of the capacitor array, a mismatch error of a capacitor with the weight of less than Wm′ is negligible, and the weight of the capacitor is an ideal weight.

14. The DNL-based performance improvement method according to claim 10, wherein the method further comprises the following steps: writing the extracted actual weight into the weight storage circuit; turning on all the effective capacitors and redundant capacitors to enable the same to participate in the A/D conversion; and performing the A/D conversion and obtaining a correct output code by using the actual weights.

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Claim Tree

  • 1
    1. A high-precision analog-to-digital converter, comprising
    • a redundant weight capacitor array, a comparator, a code reestablishment circuit, a weight storage circuit and a control logic circuit
    • wherein the redundant weight capacitor array receives external input voltages Vin+ and Vin−, generates output voltages Vout+ and Vout− under the control of the control logic circuit, supplies the output voltages Vout+ and Vout− to the comparator for comparison, and controls each bit of capacitor to participate in a voltage addition and subtraction operation in sequence under the control of the control logic circuit according to a comparison result of the comparator to regenerate output voltages Vout+ and Vout− which are supplied to the comparator for comparison, repeating as such until a last bit of capacitor completes the voltage addition and subtraction operation, and the redundant weight capacitor array is combined with the weight storage circuit to implement digital correction of a capacitor mismatch error, thereby preventing code missing for the analog-to-digital converter
    • the comparator compares the output voltages Vout+ and Vout− of the redundant weight capacitor array, outputs 1 if Vout+ is more than Vout−, or else, outputs 0
    • the code reestablishment circuit calculates an output code of the successive approximation type analog-to-digital converter according to an output result of the comparator and an actual capacitor weight extracted according to DNL in the weight storage circuit
    • the weight storage circuit stores the actual capacitor weight extracted according to DNL
    • and the control logic circuit controls the redundant weight capacitor array to collect the input voltages in a sampling stage and controls a corresponding weight capacitor of the redundant weight capacitor array to implement the voltage addition and subtraction operation according to the output result of the comparator in a conversion stage.
    • 2. The high-precision analog-to-digital converter according to claim 1, wherein
      • the redundant weight capacitor array comprises
    • 5. The high-precision analog-to-digital converter according to claim 1, wherein
      • the redundant weight capacitor array and the comparator simultaneously employ a differential structure for connection or simultaneously employ a single-end structure for connection.
  • 6
    6. A DNL-based performance improvement method, the method being adapted to a high-precision analog-to-digital converter, comprising
    • the following steps: receiving external input voltages Vin+ and Vin− for sampling, generating output voltages Vout+ and Vout− after sampling and supplying the output voltages Vout+ and Vout− to a comparator for comparison, by a redundant weight capacitor array
    • comparing the output voltages Vout+ and Vout− by the comparator to obtain a comparison output result
    • controlling a corresponding weight capacitor of the redundant weight capacitor array according to the comparison output result to perform a voltage addition and subtraction operation, regenerating output voltages Vout+ and Vout− and supplying the output voltages Vout+ and Vout− to the comparator for comparison, by a control logic circuit, repeating as such until a lowest weight bit of capacitor completes the voltage addition and subtraction operation, and implementing digital correction for a capacitor mismatch error by the redundant weight capacitor array in combination with a weight storage circuit to prevent code missing for the analog-to-digital converter
    • and storing each comparison output result, reading an actual capacitor weight extracted according to DNL in the weight storage circuit and calculating an output code of the successive approximation type analog-to-digital converter, by a code reestablishment circuit.
    • 7. The DNL-based performance improvement method according to claim 6, wherein
      • after the redundant weight capacitor array performs sampling, the output voltage Vout+ is equal to βVin+, the output voltage Vout− is equal to βVin−, and the comparator compares a first output of the output voltages Vout+ and Vout− to obtain a comparison output result Dn; the control logic circuit controls an effective capacitor Cn to perform the voltage addition and subtraction operation according to the comparison output result Dn to obtain a second output of Vout+ and Vout−; and the comparator compares the second output of the output voltages Vout+ and Vout− to obtain a comparison output result Dn-1, repeating as such until a lowest weight bit of capacitor completes the voltage addition and subtraction operation.
    • 9. The DNL-based performance improvement method according to claim 6, wherein
      • the code reestablishment circuit calculates the output code of the successive approximation type analog-to-digital converter with a formula as follows: Dout=WnDn+Wn-1Dn-1+ . . . +WrDr+W′rD′r+ . . . +W1D1+W′1D′1 wherein
    • 10. The DNL-based performance improvement method according to claim 6, wherein
      • extraction of the actual capacitor weight extracted according to DNL, stored in the weight storage circuit, comprises
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Description

BACKGROUND OF THE INVENTION

Technical Field

The present invention belongs to the technical field of analog-to-digital converters, and in particular to a high-precision analog-to-digital converter and a DNL-based performance improvement method.

Description of Related Art

A successive approximation type analog-to-digital (A/D) converter typically comprises a comparator, a capacitor array, a successive approximation register and a control logic circuit, with most of these circuit modules being digital circuits; and therefore, with the reduction of a technological dimension, the successive approximation type A/D converter starts to demonstrate an innate structural advantage thereof, where the digital circuit is not only faster in speed and lower in power consumption, but also smaller in area along with the reduction of the technological dimension, and this is in line with the requirements for low power consumption and miniaturization of a modern electronic product. Of course, an analog circuit therein also faces the problem of gain reduction and power consumption increase brought by the reduction of the technological dimension, but the advantage outweighs its disadvantage from a comprehensive view. Therefore, a successive approximation type structure becomes an international research hotspot in recent years.

The research on the successive approximation type A/D converter at present mainly focuses on the low-medium precision, and the research on the high precision is relatively scant, with the reason that a mismatch error of a capacitor array results in the linearity reduction and signal to noise ratio reduction of a high-precision successive type A/D converter due to the presence of a process variation, therefore, the mismatch error of the capacitor array becomes a key limiting factor restricting the performance of the high-precision successive type A/D converter. Based on studies, the inventor of the present invention has found that when a traditional capacitor array mismatch error measurement and correction method for the successive approximation type A/D converter is applied to the high-precision successive approximation type A/D converter, there are the following problems.

1. Structural Problem:

In a successive approximation type A/D converter of a traditional structure, if a digital correction method is adopted to record an actual weight of each capacitor, a code missing phenomenon may occur when a high bit weight is more than a sum of all the residual bit weights plus 1LSB (Least Significant Bit), even though the actual weight of each capacitor can be measured correctly. For example, a 4-bit A/D converter has an actual weight of (9, 3, 2, 1), with an input output corresponding relation as follows:


Input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Output
0
1
2
3
4
5
6
6
6
9
10
11
12
13
14
15

It follows that 7 and 8 in an output code are missing. Therefore, for the successive approximation type A/D converter of the traditional structure, the digital method cannot be used for correcting the capacitor mismatch error.

2. Problem on Mismatch Error Measurement:

For the traditional measurement of the capacitor mismatch error, a small capacitor array is typically introduced for assistance, meanwhile, a corresponding control switch and a corresponding control logic circuit are required, which not only increases the complexity of a circuit design but also results in the measurement precision reduction of the capacitor mismatch error since the introduced small capacitor array likewise has a capacitor mismatch error, and it is very difficult to meet the requirement on measurement precision during application to the high-precision successive approximation type A/D converter.

3. Problem on Capacitor Mismatch Error Correction:

With the traditional correction method for the capacitor mismatch error, a compensating capacitor array is typically used to compensate the capacitor mismatch error; when a certain capacitor participates in an addition and subtraction operation of a charge, a corresponding compensating capacitor array compensates a charge change caused by the mismatch error thereof; since the compensation precision must be within 1LSB, the compensating capacitor array must employ a complex structure to implement high compensation precision when the precision of the successive approximation type A/D converter increases, therefore, it is very difficult to implement the compensating capacitor array.

BRIEF SUMMARY OF THE INVENTION

Specific to the technical problems existing in the prior art, the present invention provides a high-precision successive approximation type analog-to-digital converter, which effectively reduces the complexity of a circuit design and may accurately measure a capacitor mismatch error and perform capacitor mismatch error correction without an auxiliary capacitor array, an auxiliary switch and a control logic, thereby achieving the object of promoting the signal to noise ratio, linearity and conversion speed of the A/D converter.

To achieve the object as described above, a technical solution employed by the present invention is as follows:

A high-precision analog-to-digital converter, characterized by comprising a redundant weight capacitor array, a comparator, a code reestablishment circuit, a weight storage circuit and a control logic circuit; wherein

the redundant weight capacitor array receives external input voltages Vin+ and Vin−, generates output voltages Vout+ and Vout− under the control of the control logic circuit, supplies the output voltages Vout+ and Vout− to the comparator for comparison, and controls each bit of capacitor to participate in a voltage addition and subtraction operation in sequence under the control of the control logic circuit according to a comparison result of the comparator to regenerate output voltages Vout+ and Vout− which are supplied to the comparator for comparison, repeating as such until a last bit of capacitor completes the voltage addition and subtraction operation, and the redundant weight capacitor array is combined with the weight storage circuit to implement digital correction of a capacitor mismatch error, thereby preventing code missing for the analog-to-digital converter;

the comparator compares the output voltages Vout+ and Vout− of the redundant weight capacitor array, outputs 1 if Vout+ is more than Vout−, or else, outputs 0;

the code reestablishment circuit calculates an output code of the successive approximation type analog-to-digital converter according to an output result of the comparator and an actual capacitor weight extracted according to DNL in the weight storage circuit;

the weight storage circuit stores the actual capacitor weight extracted according to DNL; and

the control logic circuit controls the redundant weight capacitor array to collect the input voltages in a sampling stage and controls a corresponding weight capacitor of the redundant weight capacitor array to implement the voltage addition and subtraction operation according to the output result of the comparator in a conversion stage.

The high-precision analog-to-digital converter provided by the present invention employs a capacitor array with redundant weights to enable the digital correction of a capacitor mismatch error, and with the use of the redundant weight, an error brought by the incomplete establishment of the capacitor array can be withstood, thereby promoting the conversion speed of the analog-to-digital converter; and with the measurement of the capacitor mismatch error in the present invention, the capacitor mismatch error can be measured without the auxiliary capacitor array, the auxiliary switch and the control logic, thereby reducing the complexity of the circuit design, and saving layout area and power consumption, meanwhile, with a digital method in the present invention for measuring and correcting the capacitor mismatch, the error measurement and correction precision is not limited by a technological condition, thereby improving the measurement and correction precision, and the signal to noise ratio and linearity of the analog-to-digital converter are improved by measuring and correcting the capacitor mismatch error.

Further, the redundant weight capacitor array comprises n bits of effective capacitors (corresponding to n effective weights) and at least r bits of redundant capacitors (corresponding to r redundant weights), and the number of capacitors included in each bit of the effective capacitor and redundant capacitor is an integral multiple of 2, wherein an nth bit of effective capacitor is Cn, an (n−1)th bit of effective capacitor is Cn-1, . . . , a first bit of effective capacitor is C1, Cn is a highest weight effective capacitor with the weight of Wn, C1 is a lowest weight effective capacitor with the weight of W1; and an rth bit of redundant capacitor is C′r, an (r−1)th bit of redundant capacitor is C′r-1 . . . , a first bit of redundant capacitor is C′1, C′r is a highest weight redundant capacitor with the weight of W′r, C′1 is a lowest weight redundant capacitor with the weight of W′1, the redundant weight capacitor array may comprise one or more bits of redundant capacitors from C′r, . . . , C′1 for analog-to-digital conversion, and at least one bit of redundant capacitor is present at each redundant weight.

Further, the redundant capacitors are located behind the effective capacitors having the same weight as the redundant capacitors.

Further, a maximum capacitor mismatch error determined by a process and a circuit structure is Nmismatch_max LSB, and a minimum redundant weight number required by the redundant weight capacitor array is Nr_min=1+log2(Nmismatch_max).

Further, the redundant weight capacitor array and the comparator simultaneously employ a differential structure for connection or simultaneously employ a single-end structure for connection.

The present invention also provides a DNL-based performance improvement method, the method being adapted to the foregoing high-precision successive approximation type analog-to-digital converter, comprising the following steps:

Receiving external input voltages Vin+ and Vin− for sampling, generating output voltages Vout+ and Vout− after sampling and supplying the output voltages Vout+ and Vout− to a comparator for comparison, by a redundant weight capacitor array;

comparing the output voltages Vout+ and Vout− by the comparator to obtain a comparison output result;

controlling a corresponding weight capacitor of the redundant weight capacitor array according to the comparison output result to perform a voltage addition and subtraction operation, regenerating output voltages Vout+ and Vout− and supplying the output voltages Vout+ and Vout− to the comparator for comparison, by a control logic circuit, repeating as such until a lowest weight bit of capacitor completes the voltage addition and subtraction operation, and implementing digital correction for a capacitor mismatch error by the redundant weight capacitor array in combination with a weight storage circuit to prevent code missing for the analog-to-digital converter; and

storing each comparison output result, reading an actual capacitor weight extracted according to DNL in the weight storage circuit and calculating an output code of the successive approximation type analog-to-digital converter, by a code reestablishment circuit.

The DNL-based performance improvement method adapted to the foregoing high-precision successive approximation type analog-to-digital converter provided by the present invention employs a capacitor array with redundant weights to enable the digital correction of the capacitor mismatch error, and with the use of the redundant weight, an error brought by the incomplete establishment of the capacitor array can be withstood, thereby promoting the conversion speed of the analog-to-digital converter; and with the measurement of the capacitor mismatch error in the present invention, the capacitor mismatch error can be measured without the auxiliary capacitor array, the auxiliary switch and the control logic, thereby reducing the complexity of the circuit design, and saving layout area and power consumption, meanwhile, with a digital method in the present invention for measuring and correcting the capacitor mismatch, the error measurement and correction precision is not limited by a technological condition, thereby improving the measurement and correction precision, and the signal to noise ratio and linearity of the analog-to-digital converter are improved by measuring and correcting the capacitor mismatch error.

Further, after the redundant weight capacitor array performs sampling, the output voltage Vout+ is equal to βVin+, the output voltage Vout− is equal to βVin−, and the comparator compares a first output of the output voltages Vout+ and Vout− to obtain a comparison output result Dn; the control logic circuit controls an effective capacitor Cn to perform the voltage addition and subtraction operation according to the comparison output result Dn to obtain a second output of Vout+ and Vout−; and the comparator compares the a second output of the output voltages Vout+ and Vout− to obtain a comparison output result Dn-1, repeating as such until a lowest weight bit of capacitor completes the voltage addition and subtraction operation.

Further, if the comparison output result Dn is 1, an output voltage of the nth effective capacitor after operation is

[(Vout+)-(Vout-)]n=[(Vout+)-(Vout-)]0-βVrefWnk=i+1nWk;

if the comparison output result Dn is 0, an output voltage of the nth effective capacitor after operation is

[(Vout+)-(Vout-)]n=[(Vout+)-(Vout-)]0-βVrefWnk=i+1nWk;

and Cn, Cn-1, . . . , Cr, C′r, Cr-1, C′r-1, . . . , C1, C′1 sequentially perform the voltage addition and subtraction operation in turn, wherein β is a ratio of a sum of sampling capacitors to a sum of all the capacitors, i.e.,

β=k=i+1nWkk=1nCk+k=1rCk.

Further, the code reestablishment circuit calculates the output code of the successive approximation type analog-to-digital converter with a formula as follows:

Dout=WnDn+Wn-1Dn-1+ . . . +WrDr+W′rD′r+ . . . +W1D1+W1D′1,

wherein Wn, Wn-1, . . . , Wr, W′r, . . . , W1, W′1 are capacitor weights stored in the weight storage circuit, and Dn, Dn-1, . . . , Dr, D′r, . . . , D1, D′1 are comparison output results of the comparator.

Further, the extracting of the actual capacitor weight extracted according to DNL, stored in the weight storage circuit, comprises the following steps:

Setting a capacitor weight initial value in the weight storage circuit as an ideal weight;

turning off all the redundant capacitors and then performing A/D conversion to obtain a first output sequence code of the code reestablishment circuit;

calculating a first DNL sequence of the analog-to-digital converter according to the first output sequence code;

extracting actual weights of effective capacitors according to the first DNL sequence;

turning off the effective capacitors corresponding to all the redundant capacitors and then performing A/D conversion to obtain a second output sequence code of the code reestablishment circuit;

calculating a second DNL sequence of the analog-to-digital converter according to the second output sequence code; and

extracting actual weights of the redundant capacitors according to the second DNL sequence.

Further, the setting a capacitor weight initial value in the weight storage circuit as an ideal weight specifically comprises:

Setting a significant bit weight, with a jth significant bit weight Wj=2j-1, wherein j=1, 2, . . . , n; and

setting a redundant bit weight, with a kth redundant bit weight W′k=Wk=2k-1, wherein k=1, 2, . . . , r.

Further, the extracting actual weights of effective capacitors according to the first DNL sequence specifically comprises the following steps:

restoring according to the first DNL sequence to obtain an input output relation of the analog-to-digital converter as follows:

Am(x)=j=1xA(j)=x+j=1xDNL(j),

wherein Ain(x) is an analog input voltage increment corresponding to a digital code x;

extracting a weight of an nth effective capacitor as follows:

Wn=12n-1-2Ne(n)[j=2n-1+Ne(n)2n-Ne(n)Ain(j)-j=Ne(n)2n-1-Ne(n)Ain(j)],

wherein Ne(n) is a number of rejection points determined by process mismatch; assuming a maximum mismatch determined by a process variation is e %, Ne(n) is a rounded product of 2″*e % in the calculation of an nth bit of capacitor weight, i.e. Ne(n)=int(2n×e %);

extracting a weight Wn-1 of an (n−1)th bit of effective capacitor as follows:

W(n-1)1=12n-2-2Ne(n-1)[j=2n-2+Ne(n-1)2n-1-Ne(n-1)Ain(j)-j=Ne(n-1)2n-2-Ne(n-1)Ain(j)]W(n-1)2=12n-2-2Ne(n-1)[j=2n-2+Ne(n-1)+2n-12n-1-Ne(n-1)+2n-1Ain(j)-j=Ne(n-1)+2n-12n-2-Ne(n-1)+2n-1Ain(j)]W(n-1)=12[W(n-1)1+W(n-1)2],

wherein Ne(n−1)=int(2n−1×e %); and

extracting a weight Wm of an mth bit of effective capacitor as follows:

Wm1=12m-1-2Ne(m)[j=2m-1+Ne(m)2m-Ne(m)Ain(j)-j=Ne(m)2m-1-Ne(m)Ain(j)]Wm2=12m-1-2Ne(m)[j=2m-1+Ne(m)+2m2m-Ne(m)+2mAin(j)-j=Ne(m)+2m2m-1-Ne(m)+2mAin(j)]Wm(2n-m)=12m-1-2Ne(m)[j=2m-1+Ne(m)+(2n-m-1)2m2m-Ne(m)+(2n-m-1)2mAin(j)-j=Ne(m)+(2n-m-1)2m2m-1-Ne(m)+(2n-m-1)2mAin(j)]Wm=12n-mj=12n-mWmj;

repeating as such to extract all capacitor weights remained after the mth capacitor;

if the capacitor weights of the capacitors after the mth capacitor as determined by the process variation have no effect on the monotonicity of the capacitor array, a mismatch error of a capacitor with the weight of less than Wm is negligible, and the weight of the capacitor is an ideal weight.

Further, the extracting actual weights of the redundant capacitors according to the second DNL sequence specifically comprises the following steps:

Restoring according to the second DNL sequence to obtain an input output relation of the analog-to-digital converter as follows:

Ain(x)=j=1xA(j)=x+j=1xDNL(j),

wherein A′in(x) is an analog input voltage increment corresponding to a digital code x;

extracting a weight Wr′ of an r′th redundant capacitor as follows:

Wr1=12r-1-2Ne(r)[j=2r-1+Ne(r)2r-Ne(r)Ain(j)-j=Ne(r)2r-1-Ne(r)Ain(j)]Wr2=12r-1-2Ne(r)[j=2r-1+Ne(r)+2r2r-Ne(r)+2rAin(j)-j=Ne(r)+2r2r-1-Ne(r)+2rAin(j)]Wr(2n-r)=12r-1-2Ne(r)[j=2r-1+Ne(r)+(2n-r-1)2r2r-Ne(r)+(2n-r-1)2rAin(j)-j=Ne(r)+(2n-r-1)2r2r-1-Ne(r)+(2n-r-1)2rAin(j)]Wr=12n-rj=12n-rWrj;

repeating as such to extract all capacitor weights remained after the r′th capacitor;

if the capacitor weights of the capacitors after the mth capacitor as determined by the process variation have no effect on the monotonicity of the capacitor array, a mismatch error of a capacitor with the weight of less than Wm′ is negligible, and the weight of the capacitor is an ideal weight.

Further, the method further comprises the following steps:

Writing the extracted actual weight into the weight storage circuit;

turning on all the effective capacitors and redundant capacitors to enable the same to participate in the A/D conversion; and

performing the A/D conversion and obtaining a correct output code by using the actual weights.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a block diagram of a structure of a high-precision analog-to-digital converter provided by the present invention.

FIG. 2 is a schematic diagram of a structure of a redundant weight capacitor array in FIG. 1.

FIG. 3 is a schematic diagram of a flow of extracting an actual capacitor weight of an analog-to-digital converter based on DNL provided by the present invention.

FIG. 4 is a schematic diagram of a flow of performance improvement of the analog-to-digital converter based on DNL provided by the present invention.

In the drawings, reference signs are as follows: 11, redundant weight capacitor array; 12, comparator; 13, code reestablishment circuit; 14, weight storage circuit; and 15, control logic circuit.

DETAILED DESCRIPTION OF THE INVENTION

For a better understanding of the implemented technical means, inventive features, and achieved objects and effects of the present invention, the present invention will be further illustrated below in combination with specific drawings.

As is shown by referring to FIG. 1, the present invention provides a high-precision analog-to-digital converter, comprising a redundant weight capacitor array 11, a comparator 12, a code reestablishment circuit 13, a weight storage circuit 14 and a control logic circuit 15; wherein

the redundant weight capacitor array 11 receives external input voltages Vin+ and Vin−, generates output voltages Vout+ and Vout− under the control of the control logic circuit 15, supplies the output voltages Vout+ and Vout− to the comparator 12 for comparison, and controls each bit of capacitor to participate in a voltage addition and subtraction operation in sequence under the control of the control logic circuit 15 according to a comparison result of the comparator 12 to regenerate output voltages Vout+ and Vout− which are supplied to the comparator 12 for comparison, repeating as such until a last bit of capacitor completes the addition and subtraction operation, and the redundant weight capacitor array is combined with the weight storage circuit to implement digital correction of a capacitor mismatch error, thereby preventing code missing for the analog-to-digital converter;

the comparator 12 compares the output voltages Vout+ and Vout− of the redundant weight capacitor array 11, outputs 1 if Vout+ is more than Vout−, or else, outputs 0;

the code reestablishment circuit 13 calculates an output code of the successive approximation type analog-to-digital converter according to an output result of the comparator 12 and an actual capacitor weight extracted according to DNL in the weight storage circuit 14;

the weight storage circuit 14 stores the actual capacitor weight extracted according to DNL; and

the control logic circuit 15 controls the redundant weight capacitor array 11 to collect the input voltages in a sampling stage and controls a corresponding weight capacitor of the redundant weight capacitor array 11 to implement the voltage addition and subtraction operation according to the output result of the comparator 12 in a conversion stage.

The high-precision analog-to-digital converter provided by the present invention employs a capacitor array with redundant weights to enable the digital correction of a capacitor mismatch error, and with the use of the redundant weight, an error brought by the incomplete establishment of the capacitor array can be withstood, thereby promoting the conversion speed of the analog-to-digital converter; and with the measurement of the capacitor mismatch error in the present invention, the capacitor mismatch error can be measured without the auxiliary capacitor array, the auxiliary switch and the control logic, thereby reducing the complexity of the circuit design, and saving layout area and power consumption, meanwhile, with a digital method in the present invention for measuring and correcting the capacitor mismatch, the error measurement and correction precision is not limited by a technological condition, thereby improving the measurement and correction precision, and the signal to noise ratio and linearity of the analog-to-digital converter are improved by measuring and correcting the capacitor mismatch error.

The high-precision analog-to-digital converter provided by the present invention has a working principle specifically as follows: External input voltages Vin+ and Vin− are supplied to the redundant weight capacitor array, which samples input voltages Vin+ and Vin−, generates output voltages Vout+ and Vout− and supplies the output voltages Vout+ and Vout− to the comparator for comparison, the redundant weight capacitor array is controlled in sequence according to a comparator output result to regenerate output voltages Vout+ and Vout− and supply the output voltages Vout+ and Vout− to the comparator for comparison, repeating as such until a lowest weight bit capacitor completes a voltage addition and subtraction operation, the redundant weight capacitor array is combined with the weight storage circuit to enable digital correction for the capacitor mismatch error, thereby preventing code missing for the analog-to-digital converter; and meanwhile, each output result of the comparator is sent to the code reestablishment circuit, which reestablishes a code according to the comparator output result and an actual capacitor weight information extracted according to DNL, read from the weight storage circuit, to finally obtain an output of the analog-to-digital converter.

As a particular embodiment, as is shown by referring to FIG. 2, the redundant weight capacitor array includes n bits of effective capacitors (corresponding to n effective weights) and at least r bits of redundant capacitors (corresponding to r redundant weights), and the number of capacitors included in each bit of the effective capacitor and redundant capacitor is an integral multiple of 2, wherein an nth bit of effective capacitor is Cn, an (n−1)th bit of effective capacitor is Cn-1, . . . , a first bit of effective capacitor is C1, Cn, is a highest weight effective capacitor with the weight of Wn, and C1 is a lowest weight effective capacitor with the weight of W1; an rth bit of redundant capacitor is Cr, an (r−1)th bit of redundant capacitor is C′r-1, . . . , a first bit of redundant capacitor is C′1, C′r is a highest weight redundant capacitor with the weight of W′r, C′1 is a lowest weight redundant capacitor with the weight of W′1, the redundant weight capacitor array may comprise one or more bits of redundant capacitors from C′r, . . . , C′1 for analog-to-digital conversion, that is, the redundant weight capacitor array may select p bits of redundant capacitors from the at least r bits of redundant capacitor for analog-to-digital conversion, and when the redundant weight capacitor array comprises all the capacitors of C′r, . . . , C′1, p is more than or equal to r, or else, p is less than r; moreover, at least one bit of redundant capacitor is present at each redundant weight, and in a structure of the redundant weight capacitor array as shown in FIG. 2, one bit of the redundant capacitor is present at each redundant weight. However, the redundant capacitor of each redundant weight is not limited to be one bit and may also be designed as required, two or more bits of redundant capacitors are set in one redundant weight, i.e., two or more redundant capacitors of the same weight are set in one redundant weight, for example, two bits of first C′r redundant capacitor and second C′r redundant capacitor with the same weight can be set in the redundant weight with the weight of W′r; and when two bits of first C′r redundant capacitor and second C′r redundant capacitor with the same weight can be set in the redundant weight with the weight of W′r, the redundant weight capacitor array comprises r+1 bits of redundant capacitors.

As a particular embodiment, the at least r bits of redundant capacitor C′r, . . . , C′1 in the redundant weight capacitor array may not participate in an analog-to-digital conversion process, i.e. a voltage addition and subtraction operation, under the control of the control logic circuit. The effective capacitors Cr, . . . , C1 corresponding to r bits of redundant capacitor may also not participate in the analog-to-digital process under the control of the control logic circuit. But the effective capacitors and the redundant capacitors may not participate in the analog-to-digital process simultaneously. That is, at each weight, at least one of the effective capacitor and the redundant capacitor needs to participate in the analog-to-digital process. When two or more bits of redundant capacitors of the same weight are set at some redundant weights, one bit of redundant capacitor at a certain redundant weight may be selected at first to participate in the analog-to-digital conversion in a capacitor weight extraction process, and after one capacitor weight extraction period is completed, one bit of residual redundant capacitor is selected from two or more bits of redundant capacitors with the same weight for capacitor weight extraction until the extraction of all the capacitor weights is completed. Meanwhile, in the redundant weight capacitor array provided by the present invention, the redundant capacitor is located behind the effective capacitor of the same weight, thereby possibly guaranteeing that the conversion process is performed in a descending order of the capacitor weights to enable the digital correction of the weight error.

As a particular embodiment, the weight storage circuit 14 is used for storing an actual capacitor weight extracted according to DNL, an nth bit of effective capacitor Cn has a weight of Wn, an (n−1)th bit of effective capacitor Cn-1 has a weight of Wn-1, . . . , a first bit of effective capacitor C1 has a weight of W1; and an rth bit of redundant capacitor C′r has a weight of W′r, an (r−1)th bit of redundant capacitor C′r-1 has a weight of W′r-1, . . . , a first redundant capacitor C′1 has a weight of W′1.

As a particular embodiment, in the redundant weight capacitor array provided by the present invention, the number of the least redundant weight as required is determined by a maximum capacitor mismatching determined by a process. If a maximum capacitor mismatch error determined by a process and a circuit structure is Nmismatch_max LSB, a minimum redundant weight number required by the redundant weight capacitor array is Nr_min=1+log2(Nmismatch_max).

As a particular embodiment, the redundant weight capacitor array and the comparator simultaneously employ a differential structure for connection or simultaneously employ a single-end structure for connection, thereby enabling structure consistency between the redundant weight capacitor array and the comparator. Specifically, the redundant weight capacitor array and the comparator simultaneously employing a differential structure for connection or simultaneously employing a single-end structure for connection specifically refers to that if the differential structure is employed, a differential manner is used for connection, with the capacitor array for differential output and the comparator for differential input; and if the single-end structure is employed, the single-end manner is used for connection, with the capacitor array for single-end output and the comparator for single-end input.

As a particular embodiment, the specific circuit structures of the control logic circuit, weight storage circuit and code reestablishment circuit in the present invention can be implemented with the existing circuit structure.

The present invention also provides a DNL-based performance improvement method, the method being adapted to the foregoing high-precision successive approximation type analog-to-digital converter, comprising the following steps:

Receiving external input voltages Vin+ and Vin− for sampling, generating output voltages Vout+ and Vout− after sampling and supplying the output voltages Vout+ and Vout− to a comparator for comparison, by a redundant weight capacitor array;

comparing the output voltages Vout+ and Vout− by the comparator to obtain a comparison output result;

controlling a corresponding weight capacitor of the redundant weight capacitor array according to the comparison output result to perform a voltage addition and subtraction operation, regenerating output voltages Vout+ and Vout− and supplying the output voltages Vout+ and Vout− to the comparator for comparison, by a control logic circuit, repeating as such until a lowest weight bit of capacitor completes the voltage addition and subtraction operation, and implementing digital correction for a capacitor mismatch error by the redundant weight capacitor array in combination with a weight storage circuit to prevent code missing for the analog-to-digital converter; and

storing each comparison output result, reading an actual capacitor weight extracted according to DNL in the weight storage circuit and calculating an output code of the successive approximation type analog-to-digital converter, by a code reestablishment circuit.

The DNL-based performance improvement method adapted to the foregoing high-precision successive approximation type analog-to-digital converter provided by the present invention employs a capacitor array with redundant weights to enable the digital correction of the capacitor mismatch error, and with the use of the redundant weight, an error brought by the incomplete establishment of the capacitor array can be withstood, thereby promoting the conversion speed of the analog-to-digital converter; and with the measurement of the capacitor mismatch error in the present invention, the capacitor mismatch error can be measured without the auxiliary capacitor array, the auxiliary switch and the control logic, thereby reducing the complexity of the circuit design, and saving layout area and power consumption, meanwhile, with a digital method in the present invention for measuring and correcting the capacitor mismatch, the error measurement and correction precision is not limited by a technological condition, thereby improving the measurement and correction precision, and the signal to noise ratio and linearity of the analog-to-digital converter are improved by measuring and correcting the capacitor mismatch error.

As a particular embodiment, in a sampling stage, the effective capacitor in the redundant weight capacitor array collects the input voltages, the effective capacitors Cn, Cn-1, . . . , C1 may partially or completely participate in the sampling, in case of partial participation in the sampling, all the capacitors from the ith bit to the lowest bit do not participate in the sampling, where i is more than or equal to 1; and after the redundant weight capacitor array performs the sampling, the output voltage Vout+ is equal to βVin+, the output voltage Vout− is equal to βVin−, and before all the capacitors participate in the voltage addition and subtraction operation, the input voltage of the comparator is as follows: [(Vout+)−(Vout−)]0=[(Vin+)−(Vin−)]. In a conversion stage, the control logic circuit controls a corresponding weight capacitor of the redundant weight capacitor array to implement the voltage addition and subtraction operation according to the comparator output result, at first, the comparator compares a first output of the output voltages Vout+ and Vout− to obtain a comparison output result Dn; the control logic circuit controls an effective capacitor Cn to perform the voltage addition and subtraction operation according to the comparison output result Dn to obtain a second output of Vout+ and Vout−, i.e. to obtain the output voltage [(Vout+)−(Vout−)]n after the operation of the nth effective capacitor; and the comparator compares the second output of the output voltages Vout+ and Vout− to obtain a comparison output result Dn-1, repeating as such until a lowest weight bit of capacitor completes the voltage addition and subtraction operation.

As a preferred embodiment, if the comparison output result Dn is 1, it indicates that the output voltage Vout+ is more than the output voltage Vout−, the control logic circuit needs to control a capacitor Cn corresponding to an nth weight in the redundant weight capacitor array, and if a voltage of the weight corresponding to Cn is subtracted from a previous output voltage, an output voltage of the nth bit of effective capacitor Cn after the current operation is:

[(Vout+)-(Vout-)]n=[(Vout+)-(Vout-)]0-βVrefWnk=i+1nWk;

if the comparison output result Dn is 0, it indicates that the output voltage Vout+ is less than the output voltage Vout−, the control logic circuit needs to control a capacitor Cn corresponding to an nth weight in the redundant weight capacitor array, and if a voltage of the weight corresponding to Cn is added to a previous output voltage, an output voltage of the nth bit of effective capacitor Cn after the current operation is:

[(Vout+)-(Vout-)]n=[(Vout+)-(Vout-)]0-βVrefWnk=i+1nWk,

wherein β is a ratio of a sum of sampling capacitors and a sum of all the capacitors, i.e.

β=k=i+1nWkk=1nCk+k=1rCk.

Based on the method above, Cn, Cn-1, . . . , Cr, C′r, Cr-1, C′r-1, . . . , C1, C′1 sequentially perform the voltage addition and subtraction operation in turn. Specifically, if the comparison output result Dj is 1, it indicates that the output voltage Vout+ is more than the output voltage Vout−, the control logic circuit needs to control a capacitor Cj corresponding to a jth weight in the redundant weight capacitor array, and if a voltage of the weight corresponding to Cj is subtracted from a previous output voltage, for example, when a previous operating capacitor is a capacitor Cj+1 corresponding to a (j+1)th weight, an output voltage of Cj after the current operation is

[(Vout+)-(Vout-)]j=[(Vout+)-(Vout-)]j+1-βVrefWjk=i+1nWk,

wherein j=1, 2, . . . , n−1; if the comparison output result Dj is 0, it indicates that the output voltage Vout+ is less than the output voltage Vout−, the control logic circuit needs to control a capacitor Cj corresponding to a jth weight in the redundant weight capacitor array, and if a voltage of the weight corresponding to Cj is added to a previous output voltage, for example, when a previous operating capacitor is a capacitor Cj+1 corresponding to a (j+1)th weight, an output voltage of Cj after the current operation is

[(Vout+)-(Vout-)]j=[(Vout+)-(Vout-)]j+1+βVrefWjnW,

wherein j=1, 2, . . . , n−1, repeating as such until a lowest weight bit capacitor completes the voltage addition and subtraction operation.

As a particular embodiment, the code reestablishment circuit calculates an output code of the successive approximation type analog-to-digital converter according to an output result of the comparator and a capacitor weight in the weight storage circuit, with the steps as follows:

Reading output results Dn, Dn-1, . . . , Dr, D′r, Dr-1, D′r-1, . . . , D1, D′1 of the comparator;

reading capacitor weights Wn, Wn-1, . . . , Wr, W′r, Wr-1, W′r-1, . . . , W1, W′1 in the weight storage circuit; and

calculating an output code, i.e. adding all the output results of the comparator in terms of weight as follows: Dout=WnDn+Wn-1Dn-1+ . . . +WrDr+W′rD′r+ . . . +W1D1+W′1D′1.

Due to the presence of the capacitor mismatch in a technological processing process, the actual weight of the capacitor is not equal to the ideal weight thereof, resulting in the reduction of the performance of the analog-to-digital converter, therefore, it is necessary to extract the actual capacitor weight and promote the signal to noise ratio and linearity of the analog-to-digital conversion by using the actual weight. Therefore, as a particular embodiment, as is shown by referring to FIG. 3, the extracting of the actual capacitor weight extracted according to DNL, stored in the weight storage circuit comprises the following steps:

S1, setting a capacitor weight initial value in the weight storage circuit as an ideal weight, specifically comprising the following settings:

setting a significant bit weight, with a jth significant bit weight Wj=2j-1, wherein j=1, 2, . . . , n and

setting a redundant bit weight, with a kth redundant bit weight W′k=Wk=2k-1, wherein k=1, 2, . . . , r.

S2, turning off all the redundant capacitors so that they do not participate in the analog-to-digital conversion, and then performing analog-to-digital (A/D) conversion according to the set ideal weight value to obtain a first output sequence code of the code reestablishment circuit;

S3, calculating a first DNL (Differential Nonlinear Error) of the analog-to-digital converter according to the first output sequence code, where a universal calculation method (for example a code density method) in the industry may be used as a specific method for calculating the first DNL sequence, and the detailed description thereof will be omitted herein;

S4, extracting actual weights of capacitors according to the first DNL sequence to obtain the actual weight of the effective capacitor, with the specific steps as follows:

S41, restoring according to the first DNL sequence to obtain an input output relation of the analog-to-digital converter as follows:

Assuming that the analog-to-digital converter outputs a DNL corresponding to a digital code 1 as DNL(1), outputs a DNL corresponding to a digital code 2 as DNL(2), . . . , outputs a DNL corresponding to a digital code x as DNL(x), an analog step height corresponding to an xth digital code jump may be obtained according to the DNL as follows: A(x)=DNL(x)+1, that is, an analog input needs to be added by A(1)=DNL(1)+1LSB for a first output code jump (from 0 to 1), an analog input needs to be added by A(2)=DNL(2)+1LSB for a second output code jump (from 1 to 2), . . . , an analog input needs to be added by A(x)=DNL(x)+1LSB for an xth output code jump (from x−1 to x), . . . , and an analog input needs to be added by A(2n−1)=DNL(2n−1)+1LSB for a (2n−1)th output code jump (from 2n−1 to 2n−1). As such, it is possible to further obtain the input output relation of the analog-to-digital converter as follows:

Ain(x)=j=1xA(j)=x+j=1xDNL(j),

wherein Ain(x) is an analog-to-digital input voltage increment corresponding to a digital code x.

S42, extracting a weight Wn of an nth bit of effective capacitor Cn:

The capacitor Cn is a most significant bit capacitor, with a weight of

Wn=12n-1-2Ne(n)[j=2n-1+Ne(n)2n-Ne(n)Ain(j)-j=Ne(n)2n-1-Ne(n)Ain(j)]

wherein Ne(n) is a number of rejection points determined by process mismatch; assuming a maximum mismatch determined by a process variation is e %, Ne(n) is a rounded product of 2n*e % in the calculation of an nth bit of capacitor weight, i.e. Ne(n)=int(2n×e %);

S43, extracting a weight Wn-1 of an (n−1)th bit of effective capacitor Cn-1 as follows:

The capacitor Cn-1 is a sub-most significant bit capacitor, with a capacitor weight W(n-1) calculated as follows:

W(n-1)1=12n-2-2Ne(n-1)[j=2n-2+Ne(n-1)2n-1-Ne(n-1)Ain(j)-j=Ne(n-1)2n-2-Ne(n-1)Ain(j)]W(n-1)2=12n-2-2Ne(n-1)[j=2n-2+Ne(n-1)+2n-12n-1-Ne(n-1)+2n-1Ain(j)-j=Ne(n-1)+2n-12n-2-Ne(n-1)+2n-1Ain(j)]W(n-1)=12[W(n-1)1+W(n-1)2],

wherein Ne(n−1)=int(2n-1×e %).

S44, extracting a weight Wm of an mth bit of effective capacitor as follows:

Wm1=12m-1-2Ne(m)[j=2m-1+Ne(m)2m-Ne(m)Ain(j)-j=Ne(m)2m-1-Ne(m)Ain(j)]Wm2=12m-1-2Ne(m)[j=2m-1+Ne(m)+2m2m-Ne(m)+2mAin(j)-j=Ne(m)+2m2m-1-Ne(m)+2mAin(j)]Wm(2n-m)=12m-1-2Ne(m)[j=2m-1+Ne(m)+(2n-m-1)2m2m-Ne(m)+(2n-m-1)2mAin(j)-j=Ne(m)+(2n-m-1)2m2m-1-Ne(m)+(2n-m-1)2mAin(j)]Wm=12n-mj=12n-mWmj;

S45, repeating as such to extract all capacitor weights remained after the mth capacitor;

if the capacitor weights of the capacitors after the mth capacitor as determined by the process variation have no effect on the monotonicity of the capacitor array, a mismatch error of a capacitor with the weight of less than Wm is negligible, and the weight of the capacitor is an ideal weight.

S5, turning off the effective capacitors corresponding to all the redundant capacitors so that they do not participate in the A/D conversion and then performing A/D conversion to obtain a second output sequence code of the code reestablishment circuit;

S6, calculating a second DNL sequence of the analog-to-digital converter according to the second output sequence code; and

S7, extracting an actual capacitor weight according to the second DNL sequence to obtain an actual weight of the redundant capacitor, where the method is the same as that for extracting the effective capacitor weight, specifically comprising the following steps:

S71, restoring according to the second DNL sequence to obtain an input output relation of the analog-to-digital converter as follows:

Assuming that the analog-to-digital converter outputs a DNL corresponding to a digital code 1 as DNL′(1), outputs a DNL corresponding to a digital code 2 as DNL′(2), . . . , outputs a DNL corresponding to a digital code x as DNL′(x), an analog step height corresponding to an xth digital code jump may be obtained according to the DNL as follows: A′(x)=DNL′(x)+1, that is an analog input needs to be added by A′(1)=DNL′(1)+1LSB for a first output code jump (from 0 to 1), an analog input needs to be added by A′(2)=DNL′(2)+1LSB for a second output code jump (from 1 to 2), . . . , an analog input needs to be added by A′(x)=DNL′(x)+1LSB for an xth output code jump (from x−1 to x), . . . , and an analog input needs to be added by A′(2n−1)=DNL′(2n−1)+1LSB for a (2n−1)th output code jump (from 2n−2 to 2n−1). As such, it is possible to further obtain the input output relation of the analog-to-digital converter as follows:

Ain(x)=j=1xA(j)=x+j=1xDNL(j),

wherein A′in(x) is an analog input voltage increment corresponding to a digital code x.

S72, extracting a weight Wr′ of an r′th redundant capacitor as follows:

Wr1=12r-1-2Ne(r)[j=2r-1+Ne(r)2r-Ne(r)Ain(j)-j=Ne(r)2r-1-Ne(r)Ain(j)]Wr2=12r-1-2Ne(r)[j=2r-1+Ne(r)+2r2r-Ne(r)+2rAin(j)-j=Ne(r)+2r2r-1-Ne(r)+2rAin(j)]Wr(2n-r)=12r-1-2Ne(r)[j=2r-1+Ne(r)+(2n-r-1)2r2r-Ne(r)+(2n-r-1)2rAin(j)-j=Ne(r)+(2n-r-1)2r2r-1-Ne(r)+(2n-r-1)2rAin(j)]Wr=12n-rj=12n-rWrj;

S73, repeating as such to extract all capacitor weights remained after the r′thcapacitor;

and if the capacitor weights of the capacitors after the mth capacitor as determined by the process variation have no effect on the monotonicity of the capacitor array, a mismatch error of a capacitor with the weight of less than Wm′ is negligible, and the weight of the capacitor is an ideal weight.

As a preferred embodiment, when two or more bits of redundant capacitors of the same weight are set in some redundant weights, one bit of redundant capacitor in a certain redundant weight may be selected at first to participate in the analog-to-digital conversion in a capacitor weight extraction process, and after one capacitor weight extraction period is completed, one bit of residual redundant capacitor is selected from two or more bits of redundant capacitors with the same weight for capacitor weight extraction until the extraction of all the capacitor weights is completed.

As a particular embodiment, as is shown by referring to FIG. 4, the extracted actual capacitor weight is used to improve the performance of the analog-to-digital conversion, which further comprises the following steps:

Writing the extracted actual weight into the weight storage circuit;

turning on all the effective capacitors and redundant capacitors to enable the same to participate in the A/D conversion; and

performing the A/D conversion and obtaining a correct output code by using the actual weights.

The foregoing merely provides the embodiments of the present invention, but is not intended to thereby limit the patent scope of the present invention. Any equivalent structures made by utilizing the specification and accompanying drawings of the present invention and applied to other relevant technical fields directly or indirectly likewise fall under the scope of patent protection of the present invention.

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Patent Valuation

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11.0/100 Score

Market Attractiveness

It shows from an IP point of view how many competitors are active and innovations are made in the different technical fields of the company. On a company level, the market attractiveness is often also an indicator of how diversified a company is. Here we look into the commercial relevance of the market.

50.0/100 Score

Market Coverage

It shows the sizes of the market that is covered with the IP and in how many countries the IP guarantees protection. It reflects a market size that is potentially addressable with the invented technology/formulation with a legal protection which also includes a freedom to operate. Here we look into the size of the impacted market.

69.17/100 Score

Technology Quality

It shows the degree of innovation that can be derived from a company’s IP. Here we look into ease of detection, ability to design around and significance of the patented feature to the product/service.

13.0/100 Score

Assignee Score

It takes the R&D behavior of the company itself into account that results in IP. During the invention phase, larger companies are considered to assign a higher R&D budget on a certain technology field, these companies have a better influence on their market, on what is marketable and what might lead to a standard.

27.77/100 Score

Legal Score

It shows the legal strength of IP in terms of its degree of protecting effect. Here we look into claim scope, claim breadth, claim quality, stability and priority.

Citation

Patents Cited in This Cited by
Title Current Assignee Application Date Publication Date
提高逐次逼近ADC输出信噪比的转换和校准算法及ADC 东南大学无锡分校 13 January 2011 04 May 2011
逐次逼近模数转换器及其转换方法 中国电子科技集团公司第二十四研究所 29 April 2014 16 July 2014
一种低功耗逐次逼近型模数转换器及其转换方法 东南大学无锡分校 11 April 2013 19 June 2013
逐次逼近型模数转换器 中国科学院微电子研究所 17 August 2012 28 November 2012
带数字校正的逐次逼近全差分模数转换器及其处理方法 电子科技大学 20 May 2013 04 September 2013
See full citation <>

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US10003352 High-precision analog-to-digital converter DNL-based 1 US10003352 High-precision analog-to-digital converter DNL-based 2 US10003352 High-precision analog-to-digital converter DNL-based 3