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Patent Analysis of

Fixed frequency DC-DC converter

Updated Time 12 June 2019

Patent Registration Data

Publication Number

US10063143

Application Number

US15/725767

Application Date

05 October 2017

Publication Date

28 August 2018

Current Assignee

TEXAS INSTRUMENTS INCORPORATED

Original Assignee (Applicant)

TEXAS INSTRUMENTS INCORPORATED

International Classification

G05F1/00,H01F27/29,H01F41/04,H02M3/156,H02M5/458

Cooperative Classification

H02M3/156,H02M5/458,H01F41/04,H01F27/292,H02M2001/0025

Inventor

FAN, JIWEI,ZHAO, MINGYUE,NGUYEN, HUY LE NHAT

Patent Images

This patent contains figures and images illustrating the invention and its embodiment.

US10063143 Fixed frequency DC-DC converter 1 US10063143 Fixed frequency DC-DC converter 2 US10063143 Fixed frequency DC-DC converter 3
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Abstract

In a power converter system, circuitry generates first and second PWM signals during a PWM cycle for controlling application of power to an inductor. Circuitry generates error signals having AC- and DC-components, the error signals being generated in response to indications of the power applied to or developed by the inductor. Circuitry generates a feedback control signal in response to the error signals. The first and second PWM signals are controlled in response to the feedback control signals.

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Claims

1. A circuit, comprising:

a pulse width modulation (PWM) logic circuit arranged for generating during a PWM cycle a first PWM signal for controlling application of power to an inductor and arranged for generating during the PWM cycle a second PWM signal overlapping the first PWM signal, wherein the second PWM signal is asserted before the first PWM signal; loop circuitry arranged for generating error control signals in response to an indication of power associated with the inductor and in response to the second PWM signal; and a comparator arranged for generating a feedback control signal in response to comparing the error signals, wherein the width of the first PWM signal is selectively controlled in response to the feedback control signal.

2. The circuit of claim 1, wherein the PWM logic circuit is arranged for generating each PWM cycle in response to a fixed-frequency clock signal.

3. The circuit of claim 2, wherein the width of the second PWM signal is selectively controlled in response to the feedback control signal.

4. The circuit of claim 1, wherein one of the error control signals is a slope compensation signal generated by the loop circuitry in response to an average voltage of a sawtooth waveform for emulating a voltage response of the inductor, wherein the slope compensation signal includes a slope determined in response to an RC- (resistor-capacitor) time constant, and wherein the slope compensation signal is reset in response to the second PWM signal.

5. The circuit of claim 1, wherein the loop circuitry includes a voltage loop circuit arranged for generating an AC-component error signal in response to high-pass filtering an indication of an output voltage developed by the inductor.

6. The circuit of claim 5, wherein the loop circuitry includes a voltage loop circuit arranged for generating a DC-component error signal in response to integrating an indication of an output voltage developed by the inductor, wherein the DC-component error signal controls a gain of a differential difference amplifier (DDA) for generating the DC-component error signal.

7. The circuit of claim 4, wherein the loop circuitry includes a ramp loop circuit arranged for generating an AC-component error signal in response to an indication of an input voltage for coupling to the inductor.

8. The circuit of claim 7, wherein the AC-component error signal of the ramp loop circuit is generated by charging and discharging an emulation capacitor in response to the second PWM signal, and wherein the emulation capacitor is arranged for emulating a ramp response of the inductor to the input voltage for coupling to the inductor.

9. The circuit of claim 7, wherein the ramp loop circuit is arranged for generating a DC-component error signal in response to periodically sampling a slope generated in response to low-pass filtering the AC-component error signal of the ramp loop circuit.

10. The circuit of claim 1, wherein the loop circuitry includes a voltage loop circuit arranged for generating an AC-component error signal in response to high-pass filtering an indication of an output voltage developed by the inductor and for generating a DC-component error signal in response to integrating an indication of an output voltage developed by the inductor.

11. The circuit of claim 10, wherein the loop circuitry includes a ramp loop circuit arranged for generating an AC-component error signal in response to an indication of an input voltage for coupling to the inductor and for generating a DC-component error signal in response to periodically sampling a slope generated in response to low-pass filtering the AC-component error signal of the ramp loop circuit.

12. The circuit of claim 11, wherein the comparator is arranged to generate the feedback control signal in response to the AC-component error signal of the voltage loop circuit, in response to the DC-component error signal of the voltage loop circuit, in response to the AC-component error signal of the ramp loop circuit, and in response to the DC-component error signal of the ramp loop circuit.

13. The circuit of claim 12, further comprising a switching circuit arranged for coupling power to the inductor in response to the first PWM signal, wherein the switching circuit includes an upper transistor for coupling an input terminal of the inductor to the input voltage for coupling to the inductor and a lower transistor for coupling the input terminal of the inductor to a ground voltage.

14. The circuit of claim 13, wherein the comparator is arranged to generate the feedback control signal in response to a voltage developed across the source and drain of the lower transistor.

15. A system, comprising;

a substrate; a pulse width modulation (PWM) logic circuit arranged on the substrate and for generating during a PWM cycle a first PWM signal for controlling application of power to an inductor and for generating during the PWM cycle a second PWM signal overlapping the first PWM signal, wherein the second PWM signal is asserted before the first PWM signal; loop circuitry arranged on the substrate and for generating error control signals in response to an indication of power associated with the inductor; a comparator arranged on the substrate and for generating a feedback control signal in response to comparing the error signals, wherein the width of the first PWM signal and the width of the second PWM signal are selectively controlled in response to the feedback control signal; and switching circuitry arranged on the substrate and for coupling an input terminal of the inductor to the input voltage for coupling to the inductor when the first PWM signal is asserted and for coupling the input terminal of the inductor to a ground voltage when the PWM signal is de-asserted.

16. The system of claim 15, wherein the loop circuitry is arranged to generate the error control signals in response to the second PWM signal, wherein the loop circuitry includes a voltage loop circuit arranged for generating an AC-component error signal in response to high-pass filtering an indication of an output voltage developed by the inductor and for generating a DC-component error signal in response to integrating an indication of an output voltage developed by the inductor, and wherein the loop circuitry includes a ramp loop circuit arranged for generating an AC-component error signal in response to an indication of an input voltage for coupling to the inductor and for generating a DC-component error signal in response to periodically sampling a slope generated in response to low-pass filtering the AC-component error signal of the ramp loop circuit.

17. The system of claim 16, wherein the comparator is arranged to generate the feedback control signal in response to the AC-component error signal of the voltage loop circuit, in response to the DC-component error signal of the voltage loop circuit, in response to the AC-component error signal of the ramp loop circuit, in response to the DC-component error signal of the ramp loop circuit, and in response to a voltage developed in the switching circuit when the first PWM signal is de-asserted.

18. The method of claim 17, comprising:

coupling an input terminal of the inductor to the input voltage for coupling to the inductor when the first PWM signal is asserted and coupling the input terminal of the inductor to a ground voltage when the first PWM signal is de-asserted.

19. The method of claim 17, wherein one or more of the error control signals is generated in response to a high-pass filtering of an indication of power associated with the inductor, and wherein one or more of the error control signals is generated in response to a low-pass filtering of an indication of power associated with the inductor.

20. A method, comprising:

generating during a PWM cycle a first PWM signal for controlling application of power to an inductor; generating during the PWM cycle a second PWM signal overlapping the first PWM signal wherein the second PWM signal is asserted before the first PWM signal; generating error control signals in response to an indication of power associated with the inductor; and generating a feedback control signal in response to comparing the error signals, wherein the width of the first PWM signal and the width of the second PWM signal are selectively controlled in response to the feedback control signal.

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Claim Tree

  • 1
    sing: a pulse width modu
    • tion (PWM) logic circuit arranged for generating during a PWM cycle a first PWM signal for controlling application of power to an inductor and arranged for generating during the PWM cycle a second PWM signal overlapping the first PWM signal, wherein the second PWM signal is asserted before the first PWM signal; loop circuitry arr
    • ged for generating error control signals in response to an indication of power associated with the inductor and in response to the second PWM signal; and a comparator a
    • anged for generating a feedback control signal in response to comparing the error signals, wherein the width of the first PWM signal is selectively controlled in response to the feedback control signal. 2. The circuit of c
    • aim 1, wherein the PWM log c circu
      • t is arranged for generating each PWM cycle in response to a fixed-frequency clock signal. 3. The circuit of c
    • aim 1, wherein one of the rror co
      • trol signals is a slope compensation signal generated by the loop circuitry in response to an average voltage of a sawtooth waveform for emulating a voltage response of the inductor, wherein the slope c mpensat
    • aim 1, wherein the loop ci cuitry
      • ncludes a voltage loop circuit arranged for generating an AC-component error signal in response to high-pass filtering an indication of an output voltage developed by the inductor. 6. The circuit of c
    • laim 1, wherein the loop ci cuitry
      • ncludes a voltage loop circuit arranged for generating an AC-component error signal in response to high-pass filtering an indication of an output voltage developed by the inductor and for generating a DC-component error signal in response to integrating an indication of an output voltage developed by the inductor. 11. The circuit of
  • 15
    sing; a subst ate; a pul
    • width modu
    • tion (PWM) logic circuit arranged on the substrate and for generating during a PWM cycle a first PWM signal for controlling application of power to an inductor and for generating during the PWM cycle a second PWM signal overlapping the first PWM signal, wherein the second PWM signal is asserted before the first PWM signal; loop circuitry arr
    • ged on the substrate and for generating error control signals in response to an indication of power associated with the inductor; a comparator arran
    • d on the substrate and for generating a feedback control signal in response to comparing the error signals, wherein the width of the first PWM signal and the width of the second PWM signal are selectively controlled in response to the feedback control signal; and switching circ
    • try arranged on the substrate and for coupling an input terminal of the inductor to the input voltage for coupling to the inductor when the first PWM signal is asserted and for coupling the input terminal of the inductor to a ground voltage when the PWM signal is de-asserted. 16. The system of c
    • aim 15, wherein the loop ci cuitry
      • s arranged to generate the error control signals in response to the second PWM signal, wherein the loop ci cuitry
  • 18
    aim 17, comprising: couplin an input
    • rminal of the inductor to the input voltage for coupling to the inductor when the first PWM signal is asserted and coupling the input terminal of the inductor to a ground voltage when the first PWM signal is de-asserted. 19. The method of c
  • 19
    aim 17, wherein one or more of the
    • rror control signals is generated in response to a high-pass filtering of an indication of power associated with the inductor, and wherein one or more of the
  • 20
    sing: generat ng during
    • PWM cycle a first PWM signal for controlling application of power to an inductor; generating during
    • e PWM cycle a second PWM signal overlapping the first PWM signal wherein the second PWM signal is asserted before the first PWM signal; generating error c
    • trol signals in response to an indication of power associated with the inductor; and generating a f
    • dback control signal in response to comparing the error signals, wherein the width of the first PWM signal and the width of the second PWM signal are selectively controlled in response to the feedback control signal.
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Description

BACKGROUND

Electronic devices are increasingly used in a greater diversity of applications for which switching-type power supplies are called upon to operate more efficiently and effectively over increasingly wider ranges of conditions. The control circuitry for some power supplies is optimized to have a wide stability range. However, the control circuitry optimized for maintaining stability over a wide range of conditions can have a slower ability to respond to fast transients in DC (direct current) loads. In contrast, the control circuitry for power supplies optimized for responding to fast transients can have a lower stability and often emit relatively large amounts of EMI when responding to the fast transients. Accordingly, there is a need to respond quickly to transients while providing relatively stable operation and minimizing EMI emissions.

SUMMARY

In a power converter system, circuitry generates first and second PWM signals during a PWM cycle for controlling application of power to an inductor. Circuitry generates error signals having AC- and DC-components, the error signals being generated in response to indications of the power applied to or developed by the inductor. Circuitry generates a feedback control signal in response to the error signals. The first and second PWM signals are controlled in response to the feedback control signals.

This Summary is submitted with the understanding that it is not be used to interpret or limit the scope or meaning of the claims. Further, the Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a directly amplified ramp tracking-controlled Buck converter system in accordance with this disclosure.

FIG. 2 is a schematic diagram of a directly amplified ramp tracking converter in accordance with this disclosure.

FIG. 3 is a schematic diagram of an integrator for directly amplified ramp tracking in accordance with this disclosure.

FIG. 4 is a spectrum diagram of the frequency response of an integrator for directly amplified ramp tracking in accordance with this disclosure.

FIG. 5A is a functional diagram of a gain and level shifter for directly amplified ramp tracking in accordance with this disclosure.

FIG. 5B is a schematic diagram of a differential difference amplifier-based gain and level shifter for directly amplified ramp tracking in accordance with this disclosure.

FIG. 5C is a schematic diagram of a transconductance-based gain and level shifter for directly amplified ramp tracking in accordance with this disclosure.

FIG. 6A is a functional diagram of a transient feedforward circuit for directly amplified ramp tracking in accordance with this disclosure.

FIG. 6B is a schematic diagram of a differential difference amplifier-based transient feedforward circuit for directly amplified ramp tracking in accordance with this disclosure.

FIG. 6C is a schematic diagram of a transconductance-based transient feedforward circuit for directly amplified ramp tracking in accordance with this disclosure.

FIG. 7 is a functional diagram of a ramp loop circuit for directly amplified ramp tracking in accordance with this disclosure.

FIG. 8 is a schematic diagram of a switching circuit sample-and-hold current information generator for directly amplified ramp tracking in accordance with this disclosure.

FIG. 9 is a schematic diagram of a loop comparator for directly amplified ramp tracking in accordance with this disclosure.

FIG. 10 is a schematic diagram of a pulse width modulation logic circuit for directly amplified ramp tracking in accordance with this disclosure.

FIG. 11 is a waveform diagram of selected waveforms in steady state operation of a directly amplified ramp tracking converter in accordance with this disclosure.

FIG. 12 is a waveform diagram of combined waveforms of a directly amplified ramp tracking converter in accordance with this disclosure.

FIG. 13 is a waveform diagram of combined waveforms in response to an increased load of a directly amplified ramp tracking converter in accordance with this disclosure.

FIG. 14 is a waveform diagram of combined waveforms in response to a decreased load of a directly amplified ramp tracking converter in accordance with this disclosure.

FIG. 15 is a waveform diagram of waveform response to an increased load followed by a decreased load of a directly amplified ramp tracking converter in accordance with this disclosure.

DETAILED DESCRIPTION

DC-to-DC power converters control (e.g., switch on and off) the application of input power to inductive components such that currents greater than the current of the input power can be output. The application of the input power to the inductive components is switched in accordance with a switching frequency, which can be fixed or variable. Fixed-frequency converters include true fixed-frequency converters (in which the switching frequency remains fixed) and pseudo fixed-frequency converters (in which the switching frequency can be changed to respond to transient load conditions).

The DC-to-DC power converters can include compensation circuits for responding to transient load conditions (e.g., where the response is for maintaining a constant output voltage when the applied load changes). Internal compensation circuits can be implemented entirely within the packaging of a DC to DC power converter, whereas external compensation circuits require external components.

Fixed-frequency power converters with internal compensation can operate in accordance with peak current mode control techniques. However, fixed-frequency power converters with internal compensation can be relatively slow in responding to fast transient load conditions. The absence of external compensation components (which are often omitted due to size, cost, and power considerations) can limit the range of stability of the compensation circuits as well as the speed at which the internal loop compensation and slope compensation circuits can respond to fast transient (e.g., quickly changing) load conditions. Further, internally compensated fixed-frequency power converters are often limited to small-load current applications because of difficulties associated with measuring large load currents.

Pseudo-fixed-frequency converters can operate in accordance with constant-on-time (or hysteresis) control of feedback-based phase lock loop (PLL) circuits. The pseudo-fixed-frequency converters also can operate in accordance with internal compensation and/or an external compensation. The internally compensated pseudo-fixed-frequency converters can respond to fast transient load conditions by changing the switching frequency. However, changing the switching frequency normally results in additional radiation of electromagnetic interference (EMI), which can increase electrical noise and degrade signal-to-noise ratios. In compensation circuits designed for wide loop bandwidth operation, changing the switching frequency often induces jitter in the switching frequency, which contributes to emission of EMI.

In portable applications (such as handheld or automotive applications), relatively high switching frequencies are used to reduce the size and weight of fixed-frequency power converters. However, the switching speed of fixed-frequency converters can be limited by switching noise and architectural limitations. For example, latency results from the noise-blanking time for high-current/low-Rdson (on-resistance drain-to-source) sensing, loop comparator response times, and driver (e.g., for switching the input power) propagation delays. Such latencies tend to limit the overall frequency at which a converter can operate. The limitations on the overall frequency can limit the switching frequency of the fixed-frequency converter to less than around 3 MHz, for example.

In contrast, directly amplified ramp tracking (DART) control for fixed-frequency operation of power converters described herein permit true fixed-frequency power converter operation for responding to fast transient load conditions while relying upon internal compensation controls even at relatively high load currents. Fixed-frequency power converters operating in accordance with the described DART control methods can operate at high switching frequencies greater than around 3 or 4 MHz, for example.

FIG. 1 is a schematic diagram of an example directly amplified ramp tracking-controlled Buck converter system in accordance with this disclosure, generally as 100. In FIG. 1, the DART converter 110 is an internally compensated controller for controlling the operation of the Buck converter system 100.

In operation, the DART converter 110 receives input power from the input signal VIN. The DART converter 110 generates the switched output power signal VSW in response to the input signal VIN and in response to a feedback voltage signal VFB. The switched output power signal VSW is arranged for regulating a generated output voltage VSW. The switched output power signal VSW is coupled to a first terminal of a coil LO. The coil LO, for example, is an inductor for converting the voltage of the switched output power signal VSW to a second voltage at the second terminal of the coil LO.

The second voltage output at the second terminal of the coil LO is low-pass filtered by capacitor Cout to generate the output voltage Vout. The load Rload receives a current IO at the regulated output voltage Vout. However, the load Rload dynamically varies (such as when generating fast transient load conditions), which changes the voltage of Vout. The voltage divider formed by the series of Rs1 and Rs2 generates the signal VFB (at a center node) for providing an indication of the changes in the voltage of Vout. An optional feedforward capacitor CFF can be coupled in parallel with Rs1 to increase the slew rate of the indication of the changes in the voltage of Vout to control circuitry (discussed below with reference to FIG. 2, for example) within the DART converter 110.

Accordingly, the DART converter 110 can operate with or without external compensation components and can regulate the voltage of Vout using (e.g., only) one voltage-regulation control-loop input pin (e.g., used for coupling the externally generated feedback voltage VFB, which can lower packaging costs). Reducing the number of external components required can reduce system costs and overall size. The reduction of the required external components also can simplify the end-use design of a packaged DART converter 110.

FIG. 2 is a schematic diagram of an example directly amplified ramp tracking converter in accordance with this disclosure, generally as 200. In FIG. 2, an example DART converter 200 (which is similar to the DART converter 110) is generally described as including a voltage loop 210 circuit, a loop comparator 220, a ramp loop 230 circuit, a PWM logic 240 circuit, a fixed frequency oscillator 250, a driver 260, a switching circuit 270, a sample/hold 280 circuit, and a DC-current feedback indicator generator 290. The components of the DART converter 200 can be formed on a single substrate (e.g., coextensive with 200). Alternatively, converter 200 can be implemented with a DART controller integrated circuit (IC) and an external switching circuit 270 (i.e., external switching transistors), with the DART controller IC including a driver output terminal for driving the switching circuit).

The voltage loop 210 circuit and the ramp loop 230 circuit each are arranged to separately optimize the AC (alternating current) and DC (direct current) components of control signals for internally generating a feedback control signal (e.g., presented at the output of the loop comparator 220). The control signals are coupled for controlling the switching of an external inductor (e.g., via the output signal VSW).

The example voltage loop 210 circuit is responsive to the externally generated VFB signal to generate DC-component control signals and AC-component control signals for generating the feedback control signal of loop comparator 220. The voltage loop 210 circuit includes a DC portion optimized for generating higher gain and very slow slew rate control signals (e.g., the VREF-INT and the Vctrl signals, discussed below). The voltage loop 210 circuit also includes an AC portion for generating high slew rate and relatively limited gain control signals (e.g., a voltage feedforward VTFF signal, also discussed below).

The voltage loop 210 circuit includes a transient feedforward 212 circuit, a gain and level shifter 214, and an integrator 216. In general, the voltage loop 210 circuit compares the feedback voltage signal VFB with the voltage reference signal VREF for generating control signals (e.g., VTFF, VCOM, and Vctrl) for input to the loop converter 220.

The transient feedforward 212 circuit generates the signals VTFF and VCOM in response to the signals VFB and VREF. The transient feedforward 212 circuit compares VFB and VREF to generate a first error signal for indicating a high-frequency difference between the VFB and VREF signals. The first error signal is amplified with a fixed gain of around 500 percent through around 1000 percent. The first amplified error signal is high-pass filtered to generate the VTFF signal. The transient feedforward block to improves the response of the DART converter 200 to fast transient load conditions by quickly providing high-frequency information to the loop comparator 200 for immediate processing. The transient feedforward 212 circuit is further described with reference to FIG. 6A, FIG. 6B, and FIG. 6C below.

The signal VCOM is a DC voltage reference signal, which can be generated by a voltage divider to generate a voltage between the high and low analog power rails. When the generated voltage is halfway between (e.g., the average of) the high and low analog power rails, the dynamic ranges of signals generated in comparison with the signal VCOM are optimized.

The integrator 216 integrates the difference between VFB and VREF, and generates the signal VREF-INT. The integrator 216 operates in accordance with a long time constant for reducing (if not virtually eliminating) DC output voltage errors in a system (such as system 100). For example, a drop in the VFB signal causes the signal VREF-INT to rise in accordance the time constant determined in response to an input resistor (e.g., 5 MOhms) and feedback capacitor (e.g., 20 pF).

The gain and level shifter 214 generates the Vctrl signal in response to the VFB and the VREF-INT signals. The gain and level shifter 214 senses the difference between the VFB and the VREF-INT signals to generate a second error signal (e.g., which increases in response to a decrease in VFB voltage). The second error signal is amplified with a fixed gain of around 500 percent through around 1000 percent. The second amplified error signal is normalized (e.g., level-shifted) based on a fixed common voltage to generate the Vctrl signal for output.

The gain and level shifter 214 is further described with reference to FIG. 5A, FIG. 5B, and FIG. 5C below.

The ramp loop 230 circuit is responsive to the input voltage VIN signal to generate DC-component control signals and AC-component control signals for generating the feedback control signal. The ramp loop 230 circuit includes an AC-component portion for generating a first error signal (of the ramp loop 230 circuit) for increasing the stability of loop feedback and minimize switching jitter. The ramp loop 230 circuit also includes a DC-component portion optimized for generating a second error signal for slope compensation. The second error signal includes a low DC-offset, which reduces the speed requirement of the integration of the second error signal.

The ramp loop 230 circuit includes a ramp generator 232 and the slope compensation 234 circuit. The ramp loop 230 circuit generates a ramp voltage signal VRAMP in response to VIN and the PWMINT (signals VRAMP and PWMINT are discussed below with reference to FIG. 11-FIG. 15, for example). The slope compensation functionality can also be provided when the duty cycle of PWMINT is greater than 50 percent.

The ramp generator 232 changes the ramp slope of VSLOPE based on the voltage VIN (e.g., the signal VSLOPE is discussed below with reference to FIG. 11). The voltage VIN is an indication of the power applied to the switched inductor. When the signal PWMINT is high, the signal VRAMP rises to a peak amplitude (during a rising edge). When the signal PWMINT is low, the signal VRAMP falls (during a falling edge).

The slope compensation 234 circuit generates the of VSLOPE and the VS/H signals. The VSLOPE signal is a sawtooth waveform having a rising slope of around 80 mV/μsec and a near vertical falling slope. The VS/H signal is generated in response to the DISCHARGE and S/H signals generated by the PWM logic 240 circuit. As described below with reference to FIG. 7, the VRAMP is low-pass filtered to generate VSLOPE, and VSLOPE is sampled each PWM cycle in response to the S/H signal for generating the VS/H signal.

The ramp loop 230 circuit (and the ramp generator 232 and the slope compensation 234 circuit) are further described with reference to FIG. 7 below.

The loop comparator 220 combines each input signal (e.g., each error signal) and generates the feedback control signal for indicating when a PWM cycle is to be terminated. The indication for terminating the PWM cycle is asserted when the sum of positive inputs to the loop comparator 220 is higher than the sum of the negative inputs to the loop comparator 220. The operation of the loop comparator 220 is discussed below with regards to FIG. 9.

The PWM logic 240 circuit is responsive to the feedback control signal for indicating when a PWM cycle is to be terminated. The PWM logic 240 circuit generates the PWMINT signal (an “internal” PWM signal for controlling the ramp generator 232) and generates the PWMEXT signal (an “external” PWM signal for controlling the Driver 260). The PWMINT signal and the PWMEXT signal are generated responsive to a system clock (generated by the fixed-frequency oscillator 250) and the indication for terminating the PWM cycle output by the loop comparator 220 (e.g., the feedback control signal). The PWM logic 240 circuit is further described with reference to FIG. 10 below.

The (e.g., fixed-frequency) oscillator 250 is arranged to generated a (e.g., fixed-frequency) clock signal. The control signals generated by the PMW logic 240 circuit are synchronized with respect to the clock signal. Although electrical noise (e.g., EMI) is generated by changing the frequency of the oscillator 250, implementations are contemplated in which the operating frequency of the oscillator can be changed (e.g., such that the frequency of the clock signal can be changed). In various examples, DART converters can be used in response to external and/or pseudo-fixed-frequency oscillators although higher EMI levels can ensue.

The switching circuit 270 is responsive to the PWMEXT signal to source (e.g., apply) current through the high side transistor for energizing an external coil (e.g., coil LO of FIG. 1, which is coupled to node VSW) and to source current through the low side transistor for de-energizing the external coil. In a continuous mode of operation, the current in the coil does not reach a zero level at any point of a PWM switching cycle. The switching circuit 270 circuit is further described with reference to FIG. 8 below.

The current sourced through the low side transistor of switching circuit 270 can be measured to provide an indication of the current load (e.g., current IO of FIG. 1). The sample/hold 280 circuit is arranged to sample the voltage developed across the lower transistor during a noise-blanking time. The sampled voltage is voltage developed drain-to-source across the lower transistor in accordance with the Rdson (on-resistance drain-to-source) of the lower transistor. The sample/hold circuit is arranged to maintain the sampled voltage as a constant during each PWM switching cycle. The DC-current feedback indicator generator 290 is arranged to generate signal DCI (direct current indication). The signal DCI can be used by the loop comparator 220 for generating the indication for terminating the PWM cycle (as discussed below with reference to FIG. 9).

FIG. 3 is a schematic diagram of an example integrator for directly amplified ramp tracking in accordance with this disclosure, generally as 300. In FIG. 3, an example integrator 300 (which is similar to the integrator 216) is generally described as including a differential difference amplifier 310 (AMPERROR). The differential difference amplifier 310 includes a first gm (transconductance) amplifier 312 and a second gm amplifier 314. The outputs of the first gm amplifier 312 and the second gm amplifier 314 are summed together and buffered by unity gain buffer 316 (X1). The output of the buffer 316 is the output signal VREF-INT of the differential difference amplifier 312.

The differential difference amplifier 310 is arranged as a four-input error amplifier arranged as an integrator. The first gm amplifier 312 includes a non-inverting input V1 and an inverting input V2. The first gm amplifier 312 integrates the difference of the feedback voltage VFB and the reference voltage VREF in response to the resistor Rint (integrator resistor) and the capacitor Cult (integrator capacitor) and the output of the differential difference amplifier 310.

The second gm amplifier 314 includes a non-inverting input V3 and an inverting input V4. The second gm amplifier 314 controls the gain of the integration in response to the reference voltage VREF (coupled to the node V3 via buffer 320) and in response to a feedback resistor network including resistors RK1, RK2, and RDCM. The buffer 320 isolates the VREF signal from the loading of RK1 and Rk2. The resistor RDCM is selectively coupled in parallel with resistor RK2 in response to the selection signal DCM. The selection signal DCM is asserted during discontinuous mode operation for reducing the feedback resistance RK2 to reduce the gain of the integration result VREF-INT. Reducing the gain of the integrator 300 helps, for example, to prevent saturation of the integrator 300 in the event of a long period that occurs when a power stage is tri-stated.

In various examples in which the DCM function is not required, the DCM selection signal terminal can be eliminated such that the resistor Rk2 is constant and the integrator 300 has a fixed gain.

The differential difference amplifier 310 includes the V1, V2, V3, and V4 inputs, such that:

V1−V2=V4−V3  (1)

and, solving for V4:

V4=2VREFV2  (2)

For V2 and V4, respectively:

VREF-int-V21/sCint=V2-VFBRint(3)VREF-int-V4RK2=V4-VFBRK1(4)

Accordingly, the AC response (e.g., transfer function) of integrator 300 is:

VREF-int=VREF·s+k·(VREF-VFB)+VREF(k+1)·VREF·CintRints+1(k+1)·CintRintwhere,(5)k=RK2+RK1RK1(6)

and s is a Laplacian operator.

FIG. 4 is an example spectrum diagram of the frequency response of an integrator for directly amplified ramp tracking in accordance with this disclosure. FIG. 4 shows a spectrum diagram, generally as 400. Plot 402 shows gain (e.g., in dB) over frequency (e.g., DC through 1 GHz). The gain at low frequencies (e.g., around 10 Hz) varies from around 23 dB for a value k of 15 up to around 34 dB for a value k of 50, where k is the ratio of the output resistor Rk2 to the input resistor RK1 of the integrator 300.

The DC gain of the integrator 300 is a function of k, which is determined in accordance with the values of resistors Rk1 and Rk2. The value of k is select to provide a sufficient (but not excessive) amount of gain for offsetting system losses without excessive gain (which otherwise might increase interference with a main fast control loop). The “zero” of the integrator transfer function helps to enhance the stability of the feedback loop of a DART controller.

In a hysteresis control example (e.g., in PLL pseudo-fixed-frequency converters), the location of the “pole” of the integrator 300 is selected to be sufficiently low so as to not interfere with the fast loop of the feedback controller. The pole location of the integrator 300 is minimized in accordance with a relatively small input capacitor Cint. in conjunction with the Miller effect (e.g., parasitic capacitance input to output). The pole location can be expressed as:

1(k+1)·CintRint(7)

FIG. 5A is a functional diagram of an example gain and level shifter for directly amplified ramp tracking in accordance with this disclosure. FIG. 5A shows a Vctrl signal generator, generally as 500. The Vctrl signal generator 500 is similar to the gain and level shifter 214. The Vctrl signal generator 500 includes a subtractor (SUB) 502 for determining a difference (e.g., which is an error signal) between the signal VREF-INT and the signal VFB. The gain buffer 504 is arranged to normalize the output of the subtractor 502 for addition with the signal VCOM. The signal VCOM is a constant signal which is the average of (e.g., “in common with”) the analog high power rail (e.g., AVDD) and the analog low power rail (e.g., analog ground). The adder 506 is arranged to generate the Vctrl signal in response to adding the signal VCOM to the normalized output of the gain buffer 504.

In various examples, the Vctrl signal generator 500 can be a differential difference amplifier (e.g., see DDA 510 of FIG. 5B) or a gm amplifier (e.g., transconductance, e.g., gm amplifier 510 of FIG. 5C). In general, a DDA includes a low output impedance and an accurate gain control but entails higher costs and consumes a higher bias current. In contrast, a gm amplifier entails lower implementation costs and includes a higher bandwidth but also includes a higher output impedance.

The Vctrl signal generator 500 generates the Vctrl signal for controlling the DART converter 110, which in turn controls the Buck converter system 100. When the Buck converter system 100 does not include additional (e.g., internal) control circuits (e.g., which further load the output of the Vctrl signal), the Vctrl signal generator does not necessarily require a low output impedance. In such a case, the gm amplifier example can be selected for reasons of lower costs and lower power consumption. When the Buck converter system 100 does include additional control circuits the DDA example can be selected for reasons of lower costs and lower power consumption.

FIG. 5B is a schematic diagram of an example differential difference amplifier-based gain and level shifter for directly amplified ramp tracking in accordance with this disclosure. FIG. 5B shows a differential difference amplifier circuit, generally as 510. The differential difference amplifier circuit 510 is a DDA-implemented example of the Vctrl signal generator 500. The differential difference amplifier circuit 510 includes DDA 512, which includes gm amplifiers 514 and 516, capacitor CT, resistor RT, and buffer 518.

The buffer 518 is a low impedance output buffer for sufficiently driving the signal Vctrl for overcoming injection of EMI-based noise. The signal Vctrl is coupled to a gain-control resistor network including a first resistor RN1 and a second resistor RN2. The resistor-based feedback helps ensure accurate gain control. The capacitor CT and the resistor RT provide compensation for helping to ensure stability for the feedback loop architecture.

The gm amplifiers 514 and 516 can draw a large quiescent current and are relatively costly. The gm amplifier 514 includes a non-inverting input coupled to VREF-INT and an inverting input coupled to VFB. The gm amplifier 516 includes a non-inverting input coupled to VCOM and an inverting input coupled to VFfbn.

The signal Vfbn (resistive network “n” feedback voltage) is generated at the common node of the first resistor RN1 and a second resistor RN2 in response to the resistive network, signal VCOM and signal Vctrl. The outputs of the gm amplifiers 514 and 516 are commonly coupled such that the feedback loop formed by RN1 and RN2 for both outputs are equal to each other. Accordingly:

Vfbn−VCOM=VREF-INT−VFB  (8)

Moreover, Vctrl can be expressed as:

Vctrl=Rn2+Rn1Rn2(VREF-INT-VFB)+VCOM(9)

FIG. 5C is a schematic diagram of an example transconductance-based gain and level shifter for directly amplified ramp tracking in accordance with this disclosure. FIG. 5C shows a gm amplifier circuit, generally as 520, which includes gm amplifier 520 and resistor Rgain. The gm amplifier 520 is a gm amplifier-implemented example of the Vctrl signal generator 500.

In comparison with the differential difference amplifier circuit 510, the gm amplifier 520 can be implemented at a lower cost and having a lower quiescent power consumption. The gain of the gm amplifier circuit 520 is determined by the gm amplifier 522 and the resistor Rgain. The transconductance output is the voltage developed across the (e.g., fixed) resistor Rgain, where the transconductance output is proportional to 1/Rgain. Accordingly, the total gain for the output signal Vctrl is well controlled by the resistor Rgain, and can be expressed as:

Vctrl=Gm·Rgain·(VREF-INT−VFB)+VCOM  (10)

The gm amplifier circuit 520 output impedance is the output impedance of gm amplifier 522 in parallel with the resistor Rgain. Accordingly, an extra output buffer can be used to support additional line loading of the signal Vctrl when loaded down by inputs of additional circuits.

FIG. 6A is a functional diagram of an example transient feedforward circuit for directly amplified ramp tracking in accordance with this disclosure. FIG. 6A shows a VTFF (transient feedforward voltage) signal generator, generally as 600. The VTFF signal generator 600 is similar to the transient feedforward 212 circuit. The VTFF signal generator 600 includes a subtractor (SUB) 602 for determining a difference (e.g. which is a) between the signal VFB and the signal VREF.

The gain buffer 604 is arranged to buffer the output of the subtractor 602 for high-pass filtering performed by capacitor CHPF and resistor RHPF. The gain buffer 604 output is coupled to a first terminal of the capacitor CHPF, of which the second terminal is coupled to a first terminal of the resistor RHPF. The second terminal of the resistor RHPF is coupled to the signal VCOM. The signal VTFF signal is developed at the common node between the capacitor CHPF and the resistor RHPF.

The signal VTFF signal can be expressed as:

VTFF=Gain·(VFB-VREF-INT)·RHPFRHPF+1s·CHPF(11)

FIG. 6B is a schematic diagram of an example differential difference amplifier-based transient feedforward circuit for directly amplified ramp tracking in accordance with this disclosure. FIG. 6B shows a differential difference amplifier circuit, generally as 610. The differential difference amplifier circuit 610 is a DDA-implemented example of the VTFF signal generator 600. The differential difference amplifier circuit 610 includes DDA 612, which includes gm amplifiers 614 and 616, capacitor CT, resistor RT, and buffer 618.

The buffer 618 is a low impedance output buffer for driving the signal VTFF sufficiently for overcoming injection of EMI-based noise. The buffer 618 is arranged to buffer the output of the gm amplifiers 614 and 616 (and compensation network capacitor CT and resistor RT) for high-pass filtering performed by capacitor CHPF and resistor RHPF. The buffer 618 output is coupled to a first terminal of the capacitor CHPF, which includes a second terminal coupled to a first terminal of the resistor RHPF. The second terminal of the resistor RHPF is coupled to the signal VCOM. The signal VTFF signal is developed at the common node between the capacitor CHPF and the resistor RHPF.

The gm amplifiers 614 and 616 can draw a large quiescent current and are relatively costly. The gm amplifier 614 includes a non-inverting input coupled to VFB and an inverting input coupled to VREF. The gm amplifier 616 includes a non-inverting input coupled to VCOM and an inverting input coupled to the common node (Vfbn) between resistors Rn2 and Rn1.

The signal Vfbn (feedback voltage “n”) is generated at the common node of the first resistor Rn1 and a second resistor Rn2 in response to the resistive network, signal VCOM and signal Vfbn. The outputs of the gm amplifiers 614 and 616 are commonly coupled such that the feedback loop formed by Rn1 and Rn2 for both outputs is driven by the same node. Accordingly, the gain of the differential difference amplifier circuit 610 can be expressed as:

Rn1=(GAIN−1)×Rn2  (12)

FIG. 6C is a schematic diagram of an example transconductance-based transient feedforward circuit for directly amplified ramp tracking in accordance with this disclosure. FIG. 6C shows a gm amplifier circuit, generally as 620, which includes gm amplifier 622, resistor Rgain, capacitor CHPF, and resistor RHPF. The gm amplifier 620 is a gm amplifier-implemented example of the VTFF signal generator 600.

In comparison with the differential difference amplifier circuit 610, the gm amplifier 620 can be implemented at a lower cost and having a lower quiescent power consumption. The transfer function of the gm amplifier circuit 620 is determined by the gain of the gm amplifier 622 and the resistor Rgain, as well as the high-pass filter (formed by the capacitor CHPF and the resistor RHPF). Accordingly, the output of the gm amplifier circuit 620 can be expressed in accordance with Eq. 11.

The differential difference amplifier circuit 610 and/or the gm amplifier circuit 620 transient feedforward transient block are for amplifying (e.g., isolating and magnifying) the transient voltage change between VFB and VREF. The amplified transient signal is high-pass filtered (e.g., by CHPF and RHPF) to generate the signal VTFF. The signal VTIFF is compared with the signal VCOM by the loop comparator 220 for generation of the loop comparator output signal (which forms a portion of a feedback control loop including the PWM logic 240 circuit, the ramp loop 230 circuit, and the loop comparator 220 itself).

In a same-gain-stage DDA example, the output of the gain buffer 504 can also be used to drive the high-pass filter formed by the capacitor CHPF and the resistor RHPF of the differential difference amplifier circuit 610. However, loading effects of the high-pass filter can affect the signal Vctrl.

In a same-gain-stage gm amplifier example, an extra branch (e.g., current mirror) can source an output current for coupling to the high-pass filter formed by the capacitor CHPF and the resistor RHPF of the gm amplifier example 620. The cost of the extra branch is relatively very low.

FIG. 7 is a functional diagram of an example ramp loop circuit for directly amplified ramp tracking in accordance with this disclosure. FIG. 7 shows a ramp loop circuit, generally as 700. The ramp loop circuit 700 (which is similar to the ramp loop 230 circuit) includes a ramp generator 710 and a slope compensator 720 circuit.

The ramp generator 710 includes level shifters 712 and 714 and an RC network including resistors RRAMP and RBIAS and programmable capacitor CRAMP. The ramp generator 710 is arranged to receive the timing signal PWMINT. The timing signal PWMINT is an internal PWM signal characterized by a rising edge occurring around 80 ns before the rising edge of the external PWM signal PWMEXT (which is for controlling the driver 260 for selectively toggling for switching circuit 270). Accordingly, a first PWM signal (e.g., PWMEXT) and a second PWM signal (e.g., PWMINT) can overlap (e.g., such that at least a portion of the first PWM signal is asserted at the same time as a portion of the second PWM signal).

The high portion of the PWMINT signal is level shifted up to VDD by level shifters 712 and is shifted up to VIN by level shifter 714. The level-shifted PWMINT signal is coupled to drive the RC network. The VRAMP signal is generated on the positive plate (e.g., terminal) of CRAMP. The slew rate of the VRAMP (and the slew rate of the VSLOPE signal) can be adjusted (e.g., fine-tuned) by changing the capacitance of CRAMP based on the value of the RAMP-ADJ (ramp adjust) signal. The value of the RAMP-ADJ signal can be adjusted via pin-strapping or PMBus (power management bus) commands to optimize transient-response performance.

The slope compensator 720 circuit includes averaging low-pass filter (LPF) 722, buffer 724, an RC network including resistor RSLOPE and programmable capacitor CSLOPE, switch 726 for discharging the slope capacitor CSLOPE, and averaging LPF 728. The slope compensator 720 circuit generates a sawtooth waveform VSLOPE (signal VSLOPE is discussed below with reference to FIG. 11, for example). The falling edge of VRAMP signal has a slope similar and/or equal to (but opposite in polarity to) the slope of the rising edge of the VSLOPE.

The averaging LPF 722 and the buffer 724 generate an average DC voltage (e.g., proportional to the actual Vout voltage) in response to the VRAMP signal. The average DC voltage is for driving the RC network (including RSLOPE and CSLOPE) of the slope compensator 720, where the slope compensation voltage VSLOPE is generated at the common node of RSLOPE and CSLOPE. The slope of the slope compensation voltage VSLOPE is determined in response to the RC- (resistor-capacitor) time constant of the RC network. The signal VSLOPE is coupled to an input of the loop comparator 220 for generation of the loop comparator output signal.

The DISCHARGE signal is a short pulse generated by the PWM logic circuit 240 in response to a clock signal change from a zero to a one (logic state). The DISCHARGE signal closes switch 726 to discharge the slope capacitor CSLOPE (which terminates the rise of the VSLOPE signal and causes the VSLOPE signal to fall to the generated average DC voltage). After the DISCHARGE signal pulse terminates (transitions to the inactive state), the switch 726 is opened such that the slope capacitor CSLOPE begins to charge again based on the average DC voltage (which causes the VSLOPE signal to rise again such that a sawtooth waveform is generated).

The S/H signal is a short pulse generated by the PWM logic circuit 240 in response to a PWMINT signal change from a zero to a one. The S/H signal triggers the average LPF 728 to generate a hold DC voltage in response to the (e.g., instantaneous) value of the slope compensation signal VSLOPE when the PWMINT transitions to an inactive state. The hold DC voltage of VSLOPE is coupled to an input of the loop comparator 220 to lower the effect of the DC offset of the VSLOPE signal.

To help ensure the (e.g., feedback-driven) converter 200 is stable when the duty cycle of PWMINT is higher than 50%, the slope compensation is input to the loop comparator 220 for generation of the loop comparator output signal. The average of signal VRAMP can be expressed as:

VRAMP-AVEVout·RBIASRRAMP+RBIAS(13)

where RBIAS and RRAMP are resistors of the RC network of the ramp generator 710.

The discharging current through RRAMP and RBIAS can be expressed as:

Ioffdischrg=VoutRRAMP(14)

The falling slope m2 can be expressed as:

m2=IoffidschrgCRAMP=VoutRRAMP·CRAMP(15)

To help ensure loop stability when duty cycle of PWMINT is higher than 50%, the rising slope m can be expressed as:

m12m2=Vout2·RRAMP·CRAMP(16)

Vout, RRAMP and CRAMP can be predetermined values, such that the slope compensation can be inherently optimized (e.g., before deployment of the system 100). The inherently optimized slope compensation of the DART converter can be more efficient than some peak current mode control methods.

For peak current mode control, the slope compensation can be fixed with respect to worst-case conditions that could occur due to a selection of a particular inductor after deployment. As a result, relatively large margins for slope compensation are provided, such that system response to load transients is degraded from optimum response times.

In contrast, the slew rate of the falling slope of the VRAMP can be predetermined. Accordingly, the directly amplified ramp tracking-controlled converter slope compensation design can be optimized without providing relatively wide design margins, which would otherwise affect the system transient response.

FIG. 8 is a schematic diagram of an example switching circuit sample-and-hold signal generator for directly amplified ramp tracking in accordance with this disclosure. In FIG. 8, an example switching circuit sample-and-hold signal generator 800 is generally described as including a switching circuit 810 (which is similar to the switching circuit 270), a sample/hold 812 circuit (which is similar to the sample/hold 280 circuit), and a DC-current feedback indicator generator 814 (which is similar to the DC-current feedback indicator generator 290 circuit).

To decrease the Q value (e.g. quality factor) at the double pole frequency (where a Q value of 1 or lower increases loop stability), a small DC current feedback is added to the feedback loop driven by the loop comparator 220. The current information is sensed from a power stage of a Buck-converter (e.g., from a voltage developed across the low-side FET of the switching circuit 810). The voltage developed across the low-side FET is proportional to current (e.g., flowing through the external inductor when the low-side FET is on).

This voltage developed across the low-side FET is sampled and held by the sample/hold 812 circuit after a noise-blanking time. The DC-current feedback indicator generator 814 is a transimpedance amplifier for converting the current information from the sampled and held (S/H) voltage to a current proportional to the current drawn through the lower FET of the switching circuit 810. The output of the DC-current (DCI) feedback indicator generator 814 (e.g., signal DCI) is coupled as feedback current to the loop comparator 220.

Because the VRAMP emulates the AC portion of the inductor current change, complex impedances exist. For example, a double pole peak exists based on the LC-based transfer function in accordance with a Bode plot analysis of DART. The complex impedances result in frequency dependence of the feedback signal in both amplitude and phase. Accordingly, the phase angle decreases around the double pole. When the transimpedance bandwidth is around the double pole frequency, the phase margin is often decreased. To maintain an adequate phase margin, a relatively small amount of DC current information is added via signal DCI as input to the loop comparator 220. The signal DCI is processed by the loop comparator 220 to adjust the Vctrl level. Accordingly, adding the DCI signal feedback improves the phase margin at the double pole frequency and can achieve a wider stability range by DART (e.g., when the DART circuitry is coupled to an inductor having an inductance chosen by a user of a deployed DART circuit).

FIG. 9 is a schematic diagram of an example loop comparator for directly amplified ramp tracking in accordance with this disclosure, generally as 900. In FIG. 9, the example loop comparator 900 (which can be similar to loop comparator 220) is generally described as including DCI feedback 910 circuit, subtractors (SUB) 920, 922, and 924, adder 930, and output buffer 940.

The loop comparator 900 is arranged for comparing the input signals VTFF (transient feedforward voltage), VCOM (common reference voltage), VRAMP, Vctrl, DCI (load current feedback information), VSLOPE, and VS/H (a portion of the slope compensation signal VSLOPE sampled in response to the falling edge of the PWMINT signal). The falling edges of each of the PWMINT and the PWMEXT signals are initiated in response to the feedback control signal output by the loop comparator 220. Accordingly, the loop comparator 220 terminates the PWM pulse (e.g., for driving the external coil) based on the comparison of the input signals in a feedback loop-based configuration.

For example, the subtractor 920 is arranged to subtract the VTFF signal from the VCOM and to provide the (e.g., analog) result of the comparison to a first input of the adder 930. The DCI feedback circuit 910 is arranged to subtract the DCI signal from the Vctrl signal to generate the VCVI (control voltage-current) signal. The subtractor 922 is arranged to subtract the VCVI signal from the VRAMP and to provide the (e.g., analog) result of the comparison to a second input of the adder 930. The subtractor 924 is arranged to subtract the VS/H signal from the VSLOPE and to provide the (e.g., analog) result of the comparison to a third input of the adder 930 The adder 930 is arranged to add the first, second, and third inputs to generate a combined output signal, which is buffered by the buffer 940 to generate the loop comparator output.

Accordingly, the sum of the positive inputs: Vpos=VTFF+VRAMP+VSLOPE is compared to the sum of the negative inputs: Vneg=VCVI+VCOM+VS/H. When Vpos becomes larger than the Vneg, the output of the loop comparator transitions high, which terminates the assertion of PWMINT and PWMEXT (e.g., forces the PWMINT and PWMEXT signals low).

The load current feedback information DCI can also be combined with any one of the six other inputs of loop comparator. For example, the signal DCI can be combined with either the VCOM and Vctrl signals because their rates of change are relative slow and the source impedance is low. Accordingly, the voltage difference between VCVI and Vctrl changes proportionally to the load current in response to the load current feedback information DCI.

FIG. 10 is a schematic diagram of an example pulse width modulation logic circuit for directly amplified ramp tracking in accordance with this disclosure, generally as 1000. In FIG. 10, the example PWM logic 1000 circuit (which can be similar to PWM logic 240 circuit) includes latch 1002, AND gate 1004, rising edge delay buffer 1006, inverter 1008, S/H pulse generator 1010, and a discharge pulse generator 1012. In general, the PWM logic 1000 circuit is arrange to receive the loop comparator output and a system clock signal for generating the PWMINT signal (for driving the ramp generator 232), the PWMEXT signal (for driving the driver 260), and the S/H and the discharge signals (for driving the slope compensation circuit 234).

The clock signal 1022 (as shown in waveforms 1020) synchronizes circuitry of the DART converter 200 for controlling DART in each PWM cycle. For example, the discharge signal 1030 pulse is generated every clock cycle by triggering the discharge pulse generator 1012 in response to the rising edge of the clock signal 1022.

The latch 1002 asserts the PWMINT signal 1026 in response to the rising edge of the clock signal 1022. The latch 1002 de-asserts the PWMINT signal 1026 in response to the rising edge of the loop comparator signal 1024. The PWMINT signal 1026 controls the timing of the VRAMP signal. For example, the VRAMP signal rises when the PWMINT signal 1026 is high, and the VRAMP signal falls when the PWMINT signal 1026 is low (e.g., see waveforms 1114 and 1108 of FIG. 11).

The PWMEXT signal 1028 is generated in delayed response to the PWMINT signal 1026. For example, the PWMINT signal 1026 is coupled to the rising edge delay buffer 1006. The rising edge delay buffer 1006 is arranged to delay the rising edge of an input signal by, for example, 80 ns. The output of the rising edge delay buffer 1006 is logically ANDed with the PWMINT signal 1026 to generate the PWMEXT signal 1028. Accordingly, the PWMEXT signal 1028 is driven high after a fixed rising edge delay time 1034 (e.g., of about 80 ns) after the rising edge of the PWMINT signal 1028 rising edge. Moreover, the PWMEXT signal 1028 is driven low concurrently with the falling edge of the PWMINT signal 1026. The PWMEXT signal 1028 is coupled to the driver 260 for driving the switch node voltage of switching circuit 270. When the switch node voltage of switching circuit 270 is driven high, the node of the signal VSW node is driven high.

The S/H signal 1032 is generated in response to the PWMINT signal 1026. For example, the S/H signal 1032 is coupled to the inverter 1008, which in turn is coupled to the S/H pulse generator 1010. The generated S/H signal 1032 includes a narrow pulse (about 10 ns wide), which is triggered by the falling edge of the PWMINT signal 1026. The S/H signal 1032 initiates the sampling of the slope compensation sawtooth voltage (e.g., by closing switch 726) in response to the falling edge of the PWMINT signal 1026. The sampled-and-held voltage is coupled to a loop comparator 220 input for reducing the DC offset of the VSLOPE signal.

FIG. 11 is an example waveform diagram of selected waveforms in steady state operation of a directly amplified ramp tracking converter in accordance with this disclosure, generally as 1100. In FIG. 11, waveforms 1100 include the waveforms VCOM 1102, VTFF 1104, VCVI 1106, VRAMP 1108, VS/H 1110, VSLOPE 1112, PWMINT 1114, and PWMEXT 1116. The waveforms 1100 show, for example, a DART converter 200 operating in a steady state.

A first pair of signals VCOM 1102 and VTFF 1104 are combined (e.g., by subtracting VCOM 1102 from VTFF 1104) to remove DC components of VTFF 1104 such that the response to load transients of loop comparator 220 is enhanced. The signal VCOM 1102 is a constant signal generated (e.g., by a voltage divider) as being the average of the analog high power rail and the analog low power rail, which maximizes the dynamic range of signals compared with VCOM 1102. VTFF 1104 is the amplified AC-components of signal VFB (e.g., which is generated by the voltage divider formed by the series of Rs1 and Rs2 in response to the generated output voltage Vout of FIG. 1).

During steady-state operation of the DART converter (e.g., 110 and/or 200), the transient change is zero and the value of the signal VTFF 1104 is about equal to the value of the VCOM 1102 signal. As indicated by the illustrated waveform, VTFF 1104 includes a relatively small amount of Vout ripple. The average voltage level of VTFF 1104 is equal to the value of VCOM 1102, which minimizes offsets from other system signals normalized with respect to VCOM.

A second pair of signals VCVI 1106 and VRAMP 1108 are combined (e.g., where VCVI 1106 is subtracted from VRAMP 1108) for enhancing stability of the feedback loop. During steady state operation, the average voltage of VRAMP 1108 is about the same as the voltage of VCOM 1102. The waveform of VRAMP 1108 ramps higher when PWMINT 1114 is high. The slope of VRAMP 1108 is determined in response to VIN and the resistor RRAMP and capacitor CRAMP of the ramp generator 710. When VRAMP 1108 amplitude reaches the level of the VCVI, signal 1106, the PWMINT 1114 transitions low in response (e.g., after the propagation delay of the loop comparator 220). After the PWMINT 1114 signal transitions low, the VRAMP signal 1108 ramps lower until the PWMINT 1114 signal is asserted again during the next clock signal.

The VCVI signal 1106 is generated in response to the DC current feedback signal DCI (e.g., which is generated by the DC-current feedback indicator generator 290) and in response to the Vctrl signal (e.g., which is generated by the gain and level shifter 214). When the load current is increased, the increase of the signal DCI causes the level of the signal VCVI 1106 to decrease (e.g., moving downwards from the level of the Vctrl signal). In response to the decrease in VCVI 1106, the DART feedback loop forces the Vctrl signal higher (e.g., such that the Vctrl signal is forced higher in response to the increase of the load current). Accordingly, the signal VCVI 1106 intersects the peak of VRAMP 1108, and the level of the Vctrl signal varies in response to changes in the load current. When there is no load current, the voltage of the signal VCVI 1106 is about the same as the voltage of the Vctrl signal.

A third pair of signals VS/H 1110 and VSLOPE 1112 are combined (e.g., where VS/H 1110 is subtracted from VSLOPE 1112 by loop comparator 220) for providing slope compensation. The slope compensation sawtooth waveform VSLOPE 1112 adds slope compensation to the feedback control loop. The VS/H 1110 signal is generated by sampling and holding the value of the VSLOPE 1112 in response to each PWMINT falling edge. Subtracting the sampled voltage VS/H 1110 from the (e.g., instantaneous) values of the VSLOPE 1112 reduces the DC offset of the feedback control loop before integration (which increases the dynamic range of the feedback control loop).

As discussed above, the PWMEXT 1116 signal controls the switching circuit (e.g., 270) for switching an external inductor. The PWMINT 1114 signal (for controlling the internal feedback control loop) is about 80 ns wider than (and initiated about 80 ns before) the PWMEXT 1116 signal. The 80 ns delay time provides time for the loop comparator 220 circuits to respond to the feedback control loop (e.g., before the external inductor is switched).

FIG. 12 is an example waveform diagram of combined waveforms of a directly amplified ramp tracking converter in accordance with this disclosure, generally as 1200. In FIG. 12, waveforms 1200 include the combined positive-input waveform (Vpos) 1204 and the combined negative-input waveform (Vneg) 1202. For example, the positive-input waveform 1204 can be expressed as the positive sum:

Vpos=VTFF+VRAMP+VSLOPE  (17)

and the negative-input waveform 1202 can be expressed as the negative sum:

Vneg=VCVI+VCOM+VS/H  (18)

When the signal Vpos 1204 is higher than Vneg 1202, the loop comparator 220 transitions high (e.g., after the latency of the loop comparator 220). Both the signals PWMINT 1206 and PWMEXT 1208 are forced low (e.g., in response to the output of the loop comparator 220 transitioning to a high state), which terminates the “on-time” portion of the PWM cycle in which “on-time” portion the external inductor is being energized.

The assertion of the discharge pulse (e.g., see 1012) at the beginning of the assertion of the signal PWMINT 1206 forces the Vpos 1204 signal downwards below a minimum Vneg voltage 1210. After the end of the discharge pulse, the VRAMP and VSLOPE signals increase, which causes the Vneg 1204 signal to rise above the minimum voltage 1210. When the Vpos 1204 signal reaches the Vneg 1202 signal, the loop comparator 220 is triggered for ending the assertions of the PWMINT signal 1206 and the PWMEXT signal 1208.

The rise time of the Vpos 1204 signal to rise from the minimum voltage 1210 to reach the Vneg 1202 signal determines the minimum on time of the PWMEXT signal 1208. By inspection of the scaling of voltages and time, it is evident that even when the width of the PWMEXT signal 1208 is relatively close to zero (e.g., 10 nanoseconds), there is sufficient PWMINT signal 1206 width and headroom of the VRAMP amplitude to provide sufficient margins for control. Accordingly, DART techniques are well suited for very high switching frequency operation (e.g., as compared to lower frequency limitations of some peak current mode controls).

FIG. 13 is an example waveform diagram of combined waveforms in response to an increased load of a directly amplified ramp tracking converter in accordance with this disclosure, generally as 1300. In FIG. 13, waveforms 1300 include the Vneg 1302 signal, the Vpos 1304 signal, the PWMINT signal 1310, PWMEXT signal 1312, and the SW 1314 signal. Generally, FIG. 13 shows an example system response to an increased load.

During a load step-up transient, the output voltage Vout falls based on the increase in current drawn by an increased load. In response to the lowered output voltage Vout, the Vneg 1302 signal (the sum of the negative inputs of the loop comparator 220) increases and slope of the Vpos 1304 signal (the sum of the positive inputs of the loop comparator 220) decreases. The on-percentage of duty cycle is increased to raise the output voltage Vout towards a target voltage.

In an example scenario, a load step-up transient occurs around the 1 ms mark. Without delay buffer-induced delay (and/or clock synchronization gating), the DART control loop quickly initiates a response to the load step-up transient. For example, the Vneg 1302 signal rises upwards and beyond recent voltages, while the VTFF voltage component of the Vpos 1304 signal lowers the valley point 1306 and changes the slope of the Vpos 1304 signal. Accordingly, the ON-percentage of duty cycle is increased response to the load step-up transient.

Because the Vneg 1302 signal continues to increase in the next PWM cycle, the VTFF voltage component of the Vpos 1304 signal induces another lowered valley point of the Vpos 1304 signal, and the succeeding duty cycle is elongated for increasing the output voltage Vout. Accordingly, the ON-percentage of a duty cycle is increased response to a load step-up transient. The switching signal SW 1314 is similar to the timing (and the ON-percentage) as the PWMEXT 1312 (e.g., as modified by the switching circuit driver propagation latency).

FIG. 14 is an example waveform diagram of combined waveforms in response to a decreased load of a directly amplified ramp tracking converter in accordance with this disclosure, generally as 1400. In FIG. 14, waveforms 1400 include the Vneg 1402 signal, the Vpos 1404 signal, the PWMINT signal 1406, PWMEXT signal 1408, and the SW 1410 signal. Generally, FIG. 14 shows an example system response to a decreased load.

During a load step-down transient, the output voltage Vout rises based on a decrease in the current drawn by a decreased load. In response to the raised output voltage Vout, the Vneg 1402 signal (the sum of the negative inputs of the loop comparator 220) decreases and slope of the Vpos 1404 signal (the sum of the positive inputs of the loop comparator 220) initially increases. The ON-percentage of duty cycle is decreased (even to zero percent) to help the output voltage Vout fall towards a target voltage.

In an example scenario, a load step-down transient occurs around the 1.5 ms mark and the output voltage Vout rises. Without delay buffer-induced delay (and/or clock synchronization gating), the DART control loop responds to the output voltage Vout rise. For example, the Vneg 1402 signal falls, while the VTFF voltage component of the Vpos 1404 signal rises upwards in accordance with a change to the slope of the Vpos 1404 signal. Because the magnitude of the load step-down transient is relatively large, the VTFF component of the Vpos 1404 signal is relatively large and a portion of the Vpos 1404 signal (e.g., which usually tends downwards) is changed to a positive slope. Accordingly, the ON-percentage of duty cycle is reduced in response to the load step-down transient and the output voltage Vout is lowered towards a target voltage.

When the load transient release is sufficiently large, the PWMEXT signal 1408 and SW signal 1410 can be omitted so as to provide an optimal response to the load step-down transient. In such cases where the PWMEXT 1408 signal is not asserted (e.g., because the asserted PWMEXT 1408 signal would not otherwise meet a minimum PWMEXT width requirement), the internal PWMINT 1406 signal is still periodically asserted such that the DART control loop is maintained over the successive periods in which the output voltage Vout is being lowered towards the target voltage.

FIG. 15 is an example waveform diagram of waveform response to an increased load followed by a decreased load of a directly amplified ramp tracking converter in accordance with this disclosure, generally as 1500. In FIG. 15, waveforms 1500 include the Vout 1502 signal, the inductor current 1504, the Vctrl signal 1508, and the VCVI signal 1510. Generally, FIG. 15 shows an example system response to an increased load and to a decreased load.

When the load current increases, for example, the Vout 1502 signal falls until such time the inductor current 1504 rises to a level sufficient to restore the Vout 1502 signal to the targeted (e.g., regulated) voltage. In response to the drop in the Vout. 1502 signal, the Vctrl signal 1508 and the VCVI signal 1510 rise such that the PWM ON-percentage increases (which increases the inductor current 1504). When the load current changes from 0 A to 20 A, the inductor current 1504 changes by the same amounts of current. The DC current feedback (DCI) raises the level of the Vctrl signal 1508 above the VCVI signal 1510 by about 60 mV for the 20 A load current increase.

When the load current decreases, for example, the Vout 1502 signal rises until such time the PWM ON-percentage decreases inductor current 1504 to a level sufficient for the Vout 1502 signal to fall to the targeted (e.g., regulated) voltage. When the Vout 1502 signal rises above the targeted voltage, the Vctrl signal 1508 and the VCVI signal 1510 fall such that the PWM ON-percentage decreases (which decreases the inductor current 1504). When the Vout 1502 signal falls below the targeted voltage, the Vctrl signal 1508 and the VCVI signal 1510 rise such that the PWM ON-percentage increases (which increases the inductor current 1504) and the Vout 1502 signal rises such that the Vout 1502 signal is regulated around the targeted voltage.

When load current changes, the DCI signal (e.g., which is used to form a DC current feedback loop) changes the voltage level of the Vctrl signal 1508. The DCI signal decreases the Q value of the power stage double pole and increases the phase margin associated with relatively large output capacitors (e.g., capacitor Cout of the Buck converter system 100).

At the 1 ms mark, the control voltages Vctrl 1508 and VCVI 1510 rise rapidly to quickly respond to a load step-up transient. After the load step-up transient event, the control voltage VCVI returns the same level as the low load current condition whereas the Vctrl signal 1508 returns to a level about 60 mV above the low load current condition level of the Vctrl signal 1508. The integrator 216 is arranged to accommodate voltage swings of at least 60 mV system offset efficiently. Accordingly, converters arranged in accordance with the DART description are suited for high frequency operation at high load currents (e.g., operation above around 4 MHz at currents of greater than around 40 amps).

In contrast, the control voltage for peak current mode controls can change about 400 mV in response to similar load currents. The relatively large voltage swing of the control voltage presents a greater challenge for optimizing internal compensation during peak current mode.

Although the invention has been described in detail, it should be understood that various changes, substitutions and alterations can be made thereto without departing from the spirit and scope of the invention as defined by the appended claims.

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Citation

Patents Cited in This Cited by
Title Current Assignee Application Date Publication Date
DC-to-DC converter with inductor current sensing and related methods INTERSIL AMERICAS, INC. 24 December 1998 09 November 1999
Pulse-width modulation current control with reduced transient time TEXAS INSTRUMENTS INCORPORATED 23 July 2008 10 April 2012
Pulse width modulation DC-DC converter for stabilizing output voltage LG DISPLAY CO., LTD. 08 November 2013 29 December 2015
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