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Patent Analysis of

Data replication

Updated Time 12 June 2019

Patent Registration Data

Publication Number

US10152271

Application Number

US15/616446

Application Date

07 June 2017

Publication Date

11 December 2018

Current Assignee

MICRON TECHNOLOGY, INC.

Original Assignee (Applicant)

MICRON TECHNOLOGY, INC.

International Classification

G11C7/00,G06F3/06

Cooperative Classification

G06F3/065,G06F3/0619,G06F3/0688,G06F3/0625,G06F12/00

Inventor

WILLCOCK, JEREMIAH J.

Patent Images

This patent contains figures and images illustrating the invention and its embodiment.

US10152271 Data replication 1 US10152271 Data replication 2 US10152271 Data replication 3
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Abstract

The present disclosure includes apparatuses and methods for data replication. An example apparatus includes a plurality of sensing circuitries comprising respective sense amplifiers and compute components and a controller. The controller may be configured to cause replication of a data value stored in a first compute component such that the data value is propagated to a second compute component.

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Claims

1. An apparatus, comprising:

a plurality of sensing circuitries each comprising a sense amplifier and a compute component; anda controller configured to cause:

replication of a data value stored in a first compute component such that the data value is propagated to a second compute component; and a data value received at the first respective compute component to be transferred to the second respective compute component in response to a determination that the first respective compute component has a replicate mask associated therewith.

2. The apparatus of claim 1, wherein:

the first compute component is associated with a first sensing circuitry among the plurality of sensing circuitries; the second compute component is associated with a second sensing circuitry among the plurality of sensing circuitries; and the first compute component is in a same physical position with respect to the first sensing circuitry as the second compute component is with respect to the second sensing circuitry.

3. The apparatus of claim 1, wherein:

the first compute component is associated with a first sensing circuitry among the plurality of sensing circuitries; the second compute component is associated with a second sensing circuitry among the plurality of sensing circuitries; and the first compute component is in a same logical position with respect to the first sensing circuitry as the second compute component is with respect to the second sensing circuitry.

4. The apparatus of claim 1, wherein a storage location associated with the first compute component is coupled to a storage location associated with the second compute component.

5. The apparatus of claim 1, wherein the controller is configured to cause the data value to be replicated in response to receiving a global control signal.

6. The apparatus of claim 1, wherein k respective compute components are used to transfer a data word comprising k elements.

7. A method, comprising:

determining that a replicate mask associated with a second storage location is enabled; generating a replicated data value; and transferring the replicated data value from a first storage location to the second storage location based, at least in part, on a determination that a replicate mask associated with the second storage location is enabled.

8. The method of claim 7, further comprising:

determining that a replicate mask associated with a third storage location is disabled; and retaining a data value associated with the third storage location in response to the determination that the replicate mask associated with the third storage location is disabled.

9. The method of claim 7, further comprising:

receiving the replicated data value at the second storage location; and transferring the replicated data value from the second storage location to a different storage location based, at least in part, on the determination that the replicate mask associated with the second storage location is enabled.

10. The method of claim 7, further comprising determining that a replicate mask associated with the first storage location is disabled, wherein the first storage location is a closest storage location having a disabled replicate mask to the second storage location.

11. The method of claim 7, further comprising shifting data values stored in the first storage location and the second storage location in response to a determination that a data replication operation is complete.

12. An apparatus, comprising:

a plurality of sensing circuitries each comprising a sense amplifier and a compute component; anda controller configured to cause:

replication of a data value stored in a first compute component such that the data value is propagated to a second compute component; and a data value received at the first respective compute component to be retained at the first respective compute component in response to a determination that the first respective compute component does not have a replicate mask associated therewith.

13. An apparatus, comprising:

a plurality of sensing circuitries each comprising a sense amplifier and a compute component; anda controller configured to cause:

replication of a data value stored in a first compute component such that the data value is propagated to a second compute component; and a data value received at the first respective compute component to be transferred to the second respective compute component in response to a determination that the second respective compute component has a replicate mask associated therewith.

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Claim Tree

  • 1
    1. An apparatus, comprising:
    • a plurality of sensing circuitries each comprising a sense amplifier and a compute component
    • anda controller configured to cause: replication of a data value stored in a first compute component such that the data value is propagated to a second compute component
    • and a data value received at the first respective compute component to be transferred to the second respective compute component in response to a determination that the first respective compute component has a replicate mask associated therewith.
    • 2. The apparatus of claim 1, wherein
      • : the first compute component is associated with a first sensing circuitry among the plurality of sensing circuitries; the second compute component is associated with a second sensing circuitry among the plurality of sensing circuitries; and the first compute component is in a same physical position with respect to the first sensing circuitry as the second compute component is with respect to the second sensing circuitry.
    • 3. The apparatus of claim 1, wherein
      • : the first compute component is associated with a first sensing circuitry among the plurality of sensing circuitries; the second compute component is associated with a second sensing circuitry among the plurality of sensing circuitries; and the first compute component is in a same logical position with respect to the first sensing circuitry as the second compute component is with respect to the second sensing circuitry.
    • 4. The apparatus of claim 1, wherein
      • a storage location associated with the first compute component is coupled to a storage location associated with the second compute component.
    • 5. The apparatus of claim 1, wherein
      • the controller is configured to cause the data value to be replicated in response to receiving a global control signal.
    • 6. The apparatus of claim 1, wherein
      • k respective compute components are used to transfer a data word comprising
  • 7
    7. A method, comprising:
    • determining that a replicate mask associated with a second storage location is enabled
    • generating a replicated data value
    • and transferring the replicated data value from a first storage location to the second storage location based, at least in part, on a determination that a replicate mask associated with the second storage location is enabled.
    • 8. The method of claim 7, further comprising:
      • determining that a replicate mask associated with a third storage location is disabled
      • and retaining a data value associated with the third storage location in response to the determination that the replicate mask associated with the third storage location is disabled.
    • 9. The method of claim 7, further comprising:
      • receiving the replicated data value at the second storage location
      • and transferring the replicated data value from the second storage location to a different storage location based, at least in part, on the determination that the replicate mask associated with the second storage location is enabled.
    • 10. The method of claim 7, further comprising
      • determining that a replicate mask associated with the first storage location is disabled, wherein the first storage location is a closest storage location having a disabled replicate mask to the second storage location.
    • 11. The method of claim 7, further comprising
      • shifting data values stored in the first storage location and the second storage location in response to a determination that a data replication operation is complete.
  • 12
    12. An apparatus, comprising:
    • a plurality of sensing circuitries each comprising a sense amplifier and a compute component
    • anda controller configured to cause: replication of a data value stored in a first compute component such that the data value is propagated to a second compute component
    • and a data value received at the first respective compute component to be retained at the first respective compute component in response to a determination that the first respective compute component does not have a replicate mask associated therewith.
  • 13
    13. An apparatus, comprising:
    • a plurality of sensing circuitries each comprising a sense amplifier and a compute component
    • anda controller configured to cause: replication of a data value stored in a first compute component such that the data value is propagated to a second compute component
    • and a data value received at the first respective compute component to be transferred to the second respective compute component in response to a determination that the second respective compute component has a replicate mask associated therewith.
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Description

TECHNICAL FIELD

The present disclosure relates generally to semiconductor memory and methods, and more particularly, to apparatuses and methods for data replication.

BACKGROUND

Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic systems. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), among others.

Electronic systems often include a number of processing resources (e.g., one or more processors), which may retrieve and execute instructions and store the results of the executed instructions to a suitable location. A processor can comprise a number of functional units such as arithmetic logic unit (ALU) circuitry, floating point unit (FPU) circuitry, and a combinatorial logic block, for example, which can be used to execute instructions by performing an operation on data (e.g., one or more operands). As used herein, an operation can be, for example, a Boolean operation, such as AND, OR, NOT, NAND, NOR, and XOR, and/or other operations (e.g., invert, shift, arithmetic, statistics, among many other possible operations). For example, functional unit circuitry may be used to perform the arithmetic operations, such as addition, subtraction, multiplication, and division on operands, via a number of operations.

A number of components in an electronic system may be involved in providing instructions to the functional unit circuitry for execution. The instructions may be executed, for instance, by a processing resource such as a controller and/or host processor. Data (e.g., the operands on which the instructions will be executed) may be stored in a memory array that is accessible by the functional unit circuitry. The instructions and/or data may be retrieved from the memory array and sequenced and/or buffered before the functional unit circuitry begins to execute instructions on the data. Furthermore, as different types of operations may be executed in one or multiple clock cycles through the functional unit circuitry, intermediate results of the instructions and/or data may also be sequenced and/or buffered. A sequence to complete an operation in one or more clock cycles may be referred to as an operation cycle. Time consumed to complete an operation cycle costs in terms of processing and computing performance and power consumption, of a computing apparatus and/or system.

In many instances, the processing resources (e.g., processor and associated functional unit circuitry) may be external to the memory array, and data is accessed via a bus between the processing resources and the memory array to execute a set of instructions. Processing performance may be improved in a processor-in-memory (PIM) device, in which a processor may be implemented internally and near to a memory (e.g., directly on a same chip as the memory array). A processing-in-memory device may save time and/or power by reducing and/or eliminating external communications.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an apparatus in the form of a computing system including a memory device in accordance with a number of embodiments of the present disclosure.

FIG. 2 is a schematic diagram illustrating sensing circuitry of a memory device in accordance with a number of embodiments of the present disclosure.

FIG. 3 is a schematic diagram illustrating circuitry for data replication in a memory device in accordance with a number of embodiments of the present disclosure.

FIG. 4 is a schematic diagram illustrating sensing circuitry in accordance with a number of embodiments of the present disclosure.

FIG. 5 is a schematic diagram illustrating an example wiring configuration for data replication in accordance with a number of embodiments of the present disclosure.

FIG. 6A is a flow diagram illustrating an example of data replication in accordance with a number of embodiments of the present disclosure.

FIG. 6B is a flow diagram illustrating another example of data replication in accordance with a number of embodiments of the present disclosure.

FIG. 7 is a logic table illustrating selectable logic operation results implemented by a sensing circuitry shown in FIG. 5 in accordance with a number of embodiments of the present disclosure.

DETAILED DESCRIPTION

The present disclosure includes apparatuses and methods for data replication. An example apparatus includes a plurality of sensing circuitries comprising respective sense amplifiers and compute components, and a controller. The controller may be configured to cause replication of a data value stored in a first compute component such that the data value is propagated to a second compute component.

Carry propagation (e.g., transfer of data between storage locations in a memory device) may be a bottleneck for various arithmetic operations such as horizontal arithmetic operations. As used herein, horizontal arithmetic operations include operations in which bits of the same number are located in different storage locations.

In a number of embodiments, an amount of time and/or power consumed, and/or an amount of physical wiring used for carry propagation operations may be reduced versus some approaches. For example, embodiments described herein may allow for data replication in a single step as opposed to multiple steps, as utilized in some approaches. As another example, embodiments may allow for faster data transfers in comparison to some approaches that may rely on shifting data between multiple storage locations for carry propagation. For example, some embodiments may utilize k storage locations for carry propagation on words of length k, as opposed to 2k as used in some shift-chain based approaches to carry propagation. As used herein, “data replication” refers to an operation in which a data value that is stored in a storage location is copied and propagated to one or more different storage locations. In a number of embodiments, the data value may be erased after the replication operation; however, embodiments are not so limited and the data value may be stored in the storage location after the data replication operation is performed.

In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how one or more embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and structural changes may be made without departing from the scope of the present disclosure.

As used herein, designators such as “X”, “Y”, “N”, “M”, etc., particularly with respect to reference numerals in the drawings, indicate that a number of the particular feature so designated can be included. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting. As used herein, the singular forms “a”, “an”, and “the” can include both singular and plural referents, unless the context clearly dictates otherwise. In addition, “a number of”, “at least one”, and “one or more” (e.g., a number of memory banks) can refer to one or more memory banks, whereas a “plurality of” is intended to refer to more than one of such things. Furthermore, the words “can” and “may” are used throughout this application in a permissive sense (i.e., having the potential to, being able to), not in a mandatory sense (i.e., must). The term “include,” and derivations thereof, means “including, but not limited to.” The terms “coupled” and “coupling” mean to be directly or indirectly connected physically or for access to and movement (transmission) of commands and/or data, as appropriate to the context. The terms “data” and “data values” are used interchangeably herein and can have the same meaning, as appropriate to the context.

The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number and the remaining digits identify an element or component in the figure. Similar elements or components between different figures may be identified by the use of similar digits. For example, 150 may reference element “50” in FIG. 1, and a similar element may be referenced as 250 in FIG. 2. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, the proportion and/or the relative scale of the elements provided in the figures are intended to illustrate certain embodiments of the present disclosure and should not be taken in a limiting sense.

FIG. 1 is a block diagram of an apparatus in the form of a computing system 100 including a memory device 120 in accordance with a number of embodiments of the present disclosure. As used herein, a memory device 120, controller 140, channel controller 143, memory array 130, sensing circuitry 150, and/or a number of additional latches 170 might also be separately considered an “apparatus.”

As used herein, the additional latches 170 are intended to provide additional functionalities (e.g., peripheral amplifiers) that sense (e.g., read, store, cache) data values of memory cells in an array and that are distinct from the sense amplifiers of the sensing component stripes described herein (e.g., as shown at 206 in FIG. 2 and at corresponding reference number in FIG. 3). As such, the additional latches can be included in a “latch component 170.” For example, latches of the latch component 170 can be located on a periphery of a bank 121 of the memory device. In contrast, the sense amplifiers located in a plurality of sensing component stripes may be physically associated with each subarray of memory cells in the bank.

System 100 in FIG. 1 includes a host 110 coupled (e.g., connected) to memory device 120, which includes a memory array 130. Host 110 can be a host system such as a personal laptop computer, a desktop computer, a digital camera, a smart phone, or a memory card reader, among various other types of hosts. Host 110 can include a system motherboard and/or backplane and can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry). The system 100 can include separate integrated circuits or both the host 110 and the memory device 120 can be on the same integrated circuit. The system 100 can be, for instance, a server system and/or a high performance computing (HPC) system and/or a portion thereof. Although the example shown in FIG. 1 illustrate a system having a Von Neumann architecture, embodiments of the present disclosure can be implemented in non-Von Neumann architectures, which may not include one or more components (e.g., CPU, ALU, etc.) often associated with a Von Neumann architecture.

For clarity, the system 100 has been simplified to focus on features with particular relevance to the present disclosure. The memory array 130 can be a DRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash array, and/or NOR flash array, among other types of arrays. The array 130 can include memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as data lines or digit lines). Although a single array 130 is shown in FIG. 1, embodiments are not so limited. For instance, memory device 120 may include a number of arrays 130 (e.g., a number of banks of DRAM cells, NAND flash cells, etc.).

The memory device 120 can include address circuitry 142 to latch address signals provided over a bus 156 (e.g., an external data bus, external I/O bus connected to the host 110, a 64 bit wide data bus, etc.) by I/O circuitry 144, which can comprise an internal I/O bus. The internal I/O bus (e.g., internal bus 147-1, . . . , 147-N illustrated in FIG. 1B), can transfer data between memory banks and I/O pins (e.g., DRAM DQs), for example.

Status and exception information can be provided from the controller 140 of the memory device 120 to a channel controller 143, for example, through an out-of-band (00B) bus 157, which in turn can be provided from the channel controller 143 to the host 110. The channel controller 143 can include a logic component 160 to allocate a plurality of locations (e.g., controllers for subarrays) in the arrays of each respective bank to store bank commands, application instructions (e.g., for sequences of operations), and arguments (e.g., PIM commands) for the various banks associated with operations of each of a plurality of memory devices. The channel controller 143 can send commands (e.g., PIM commands) to the plurality of memory devices 120-1, . . . , 120-N to store those program instructions within a given bank of a memory device. As used herein, “PIM commands” are commands executed by processing elements within a memory bank (e.g., via sensing circuitry 150), as opposed to normal DRAM commands (e.g., read/write commands) that result in data being operated on by an external processing component such as the host 110.

Address signals are received through address circuitry 142 and decoded by a row decoder 146 and a column decoder 152 to access the memory array 130. Data can be sensed (read) from memory array 130 by sensing voltage and/or current changes on sense lines (digit lines) using a number of sense amplifiers, as described herein, of the sensing circuitry 150. A sense amplifier can read and latch a page (e.g., a row) of data from the memory array 130. Additional compute circuitry, as described herein, can be coupled to the sensing circuitry 150 and can be used in combination with the sense amplifiers to sense, store (e.g., cache and/or buffer), perform compute functions (e.g., operations), and/or move data. The I/O circuitry 144 can be used for bi-directional data communication with host 110 over the bus 156. The write circuitry 148 can be used to write data to the memory array 130.

Controller 140 (e.g., bank control logic and sequencer) can decode signals (e.g., commands) provided by control bus 154 from the host 110. These signals can include chip enable signals, write enable signals, and/or address latch signals that can be used to control operations performed on the memory array 130, including data sense, data store, data movement (e.g., copying, transferring, and/or transporting data values), data write, and/or data erase operations, among other operations. In various embodiments, the controller 140 can be responsible for executing instructions from the host 110 and accessing the memory array 130. The controller 140 can be a state machine, a sequencer, or some other type of controller.

Examples of the sensing circuitry 150 are described further below (e.g., in FIGS. 2 and 3). For instance, in a number of embodiments, the sensing circuitry 150 can include a number of sensing components (e.g., a number of sense amplifiers and compute components), which may serve as an accumulator and can be used to perform operations in each subarray (e.g., on data associated with complementary sense lines).

In a number of embodiments, the sensing circuitry 150 can be used to perform operations using data stored in memory array 130 as inputs and participate in movement of the data for copy, transfer, writing, logic, and/or storage operations to a different location in the memory array 130 without transferring the data via a sense line address access (e.g., without firing a column decode signal). As such, various compute functions can be performed using, and within, sensing circuitry 150 rather than (or in association with) being performed by processing resources external to the sensing circuitry 150 (e.g., by a processor associated with host 110 and/or other processing circuitry, such as ALU circuitry, located on memory device 120, such as on controller 140 or elsewhere).

In various previous approaches, data associated with an operand, for instance, would be read from memory via sensing circuitry and provided to external ALU circuitry via I/O lines (e.g., via local I/O lines and/or global I/O lines) and/or a bus (e.g., external data bus 156). The external ALU circuitry could include a number of registers and could perform compute functions using the operands, and the result would be transferred back to the array via the I/O lines. In contrast, in a number of embodiments of the present disclosure, sensing circuitry 150 is configured to perform operations on data stored in memory array 130 and store the result back to the memory array 130 without enabling an I/O line (e.g., a local I/O line) coupled to the sensing circuitry 150. In a number of embodiments, methods, and apparatuses are provided which can function as a PIM RAM. As used herein, “PIM RAM” refers to random access memory in which operations may be performed without transferring the data on which the operations are to be performed to an external location such as a host processor via a bus (e.g., external bus 156). In PIM RAM operation it is useful to transfer data between banks without using a data bus external to the die. The sensing circuitry 150 can be formed on a same pitch as sense lines of the array. As an example, a pair of complementary memory cells may have a cell size with a 6F2 pitch (e.g., 3F×2F). If the pitch of a pair of complementary sense lines for the complementary memory cells is 3F, then the sensing circuitry being on pitch indicates the sensing circuitry (e.g., a sense amplifier and corresponding compute component per respective pair of complementary sense lines) is formed to fit within the 3F pitch of the complementary sense lines. The latch component 170 can include latches, as described herein, and can be coupled to the sensing circuitry 150 via a shared I/O line, but can be distinct from the sensing circuitry 150.

In a number of embodiments, circuitry external to array 130 and sensing circuitry 150 is not needed to perform compute functions as the sensing circuitry 150 can be controlled to perform the appropriate operations associated with such compute functions without the use of an external processing resource. In some embodiments, sensing components can serve as 1-bit processing elements on a per column basis. Therefore, the sensing circuitry 150 may be used to complement or to replace, at least to some extent, such an external processing resource (or at least the bandwidth consumption of such an external processing resource).

However, in a number of embodiments, the sensing circuitry 150 may be used to perform operations (e.g., to execute instructions) in addition to operations performed by an external processing resource (e.g., host 110). For instance, host 110 and/or sensing circuitry 150 may be limited to performing only certain operations and/or a certain number of operations.

Enabling an I/O line can include enabling (e.g., turning on, activating) a transistor having a gate coupled to a decode signal (e.g., a column decode signal) and a source/drain coupled to the I/O line. However, embodiments are not limited to not enabling an I/O line. For instance, in a number of embodiments, the sensing circuitry 150 can be used to perform operations without enabling column decode lines of the array; however, the local I/O line(s) may be enabled in order to transfer a result to a suitable location other than back to the array 130, for example, to an external register. Enabling (e.g., firing) a DQ pin can similarly consume significant power and time (e.g., require additional clock cycles (tck) for data transfers).

FIG. 2 is a schematic diagram illustrating sensing circuitry 250 in accordance with a number of embodiments of the present disclosure. The sensing circuitry 250 can correspond to sensing circuitry 150 shown in FIG. 1.

A memory cell can include a storage element (e.g., capacitor) and an access device (e.g., transistor). For instance, a first memory cell can include transistor 202-1 and capacitor 203-1, and a second memory cell can include transistor 202-2 and capacitor 203-2, etc. In this embodiment, the memory array 230 is a DRAM array of 1T1C (one transistor one capacitor) memory cells, although other embodiments of configurations can be used (e.g., 2T2C with two transistors and two capacitors per memory cell). In a number of embodiments, the memory cells may be destructive read memory cells (e.g., reading the data stored in the cell destroys the data such that the data originally stored in the cell is refreshed after being read).

The cells of the memory array 230 can be arranged in rows coupled by access (word) lines 204-X (Row X), 204-Y (Row Y), etc., and columns coupled by pairs of complementary sense lines (e.g., digit lines DIGIT(D) and DIGIT(D)_ shown in FIG. 2 and DIGIT_0 and DIGIT_0* shown in FIG. 3). The individual sense lines corresponding to each pair of complementary sense lines can also be referred to as digit lines 205-1 for DIGIT (D) and 205-2 for DIGIT (D)_, respectively, or corresponding reference numbers in FIG. 3. Although only one pair of complementary digit lines are shown in FIG. 2, embodiments of the present disclosure are not so limited, and an array of memory cells can include additional columns of memory cells and digit lines (e.g., 4,096, 8,192, 16,384, etc.).

Although rows and columns are illustrated as orthogonally oriented in a plane, embodiments are not so limited. For example, the rows and columns may be oriented relative to each other in any feasible three-dimensional configuration. For example, the rows and columns may be oriented at any angle relative to each other, may be oriented in a substantially horizontal plane or a substantially vertical plane, and/or may be oriented in a folded topology, among other possible three-dimensional configurations.

Memory cells can be coupled to different digit lines and word lines. For example, a first source/drain region of a transistor 202-1 can be coupled to digit line 205-1 (D), a second source/drain region of transistor 202-1 can be coupled to capacitor 203-1, and a gate of a transistor 202-1 can be coupled to word line 204-Y. A first source/drain region of a transistor 202-2 can be coupled to digit line 205-2 (D)_, a second source/drain region of transistor 202-2 can be coupled to capacitor 203-2, and a gate of a transistor 202-2 can be coupled to word line 204-X. A cell plate, as shown in FIG. 2, can be coupled to each of capacitors 203-1 and 203-2. The cell plate can be a common node to which a reference voltage (e.g., ground) can be applied in various memory array configurations.

The memory array 230 is configured to couple to sensing circuitry 250 in accordance with a number of embodiments of the present disclosure. In this embodiment, the sensing circuitry 250 comprises a sense amplifier 206 and a compute component 231 corresponding to respective columns of memory cells (e.g., coupled to respective pairs of complementary digit lines). The sense amplifier 206 can be coupled to the pair of complementary digit lines 205-1 and 205-2. The compute component 231 can be coupled to the sense amplifier 206 via pass gates 207-1 and 207-2. The gates of the pass gates 207-1 and 207-2 can be coupled to operation selection logic 213.

The operation selection logic 213 can be configured to include pass gate logic for controlling pass gates that couple the pair of complementary digit lines un-transposed between the sense amplifier 206 and the compute component 231 and swap gate logic for controlling swap gates that couple the pair of complementary digit lines transposed between the sense amplifier 206 and the compute component 231. The operation selection logic 213 can also be coupled to the pair of complementary digit lines 205-1 and 205-2. The operation selection logic 213 can be configured to control pass gates 207-1 and 207-2 based on a selected operation.

The sense amplifier 206 can be operated to determine a data value (e.g., logic state) stored in a selected memory cell. The sense amplifier 206 can comprise a cross coupled latch, which can be referred to herein as a primary latch or a “B” latch. In the example illustrated in FIG. 2, the circuitry corresponding to sense amplifier 206 comprises a latch 215 including four transistors coupled to a pair of complementary digit lines (D) 205-1 and (D)_ 205-2. However, embodiments are not limited to this example. The latch 215 can be a cross coupled latch (e.g., gates of a pair of transistors) such as n-channel transistors (e.g., NMOS transistors) 227-1 and 227-2 are cross coupled with the gates of another pair of transistors, such as p-channel transistors (e.g., PMOS transistors) 229-1 and 229-2).

In operation, when a memory cell is being sensed (e.g., read), the voltage on one of the digit lines 205-1 (D) or 205-2 (D)_ will be slightly greater than the voltage on the other one of digit lines 205-1 (D) or 205-2 (D)_. An ACT signal and an RNL* signal can be driven low to enable (e.g., fire) the sense amplifier 206. The digit lines 205-1 (D) or 205-2 (D)_ having the lower voltage will turn on one of the PMOS transistor 229-1 or 229-2 to a greater extent than the other of PMOS transistor 229-1 or 229-2, thereby driving high the digit line 205-1 (D) or 205-2 (D)_ having the higher voltage to a greater extent than the other digit line 205-1 (D) or 205-2 (D)_ is driven high.

Similarly, the digit line 205-1 (D) or 205-2 (D)_ having the higher voltage will turn on one of the NMOS transistor 227-1 or 227-2 to a greater extent than the other of the NMOS transistor 227-1 or 227-2, thereby driving low the digit line 205-1 (D) or 205-2 (D)_ having the lower voltage to a greater extent than the other digit line 205-1 (D) or 205-2 (D)_ is driven low. As a result, after a short delay, the digit line 205-1 (D) or 205-2 (D)_ having the slightly greater voltage is driven to the voltage of the supply voltage VDD through a source transistor, and the other digit line 205-1 (D) or 205-2 (D)_ is driven to the voltage of the reference voltage (e.g., ground) through a sink transistor. Therefore, the cross coupled NMOS transistors 227-1 and 227-2 and PMOS transistors 229-1 and 229-2 serve as a sense amplifier pair, which amplify the differential voltage on the digit lines 205-1 (D) and 205-2 (D)_ and operate to latch a data value sensed from the selected memory cell.

Embodiments are not limited to the sense amplifier 206 configuration illustrated in FIG. 2. As an example, the sense amplifier 206 can be a current-mode sense amplifier and a single-ended sense amplifier (e.g., sense amplifier coupled to one digit line). Also, embodiments of the present disclosure are not limited to a folded digit line architecture such as that shown in FIG. 2.

The sense amplifier 206 can, in conjunction with the compute component 231, be operated to perform various operations using data from an array as input. In a number of embodiments, the result of an operation can be stored back to the array without transferring the data via a digit line address access and/or moved between banks without using an external data bus (e.g., without firing a column decode signal such that data is transferred to circuitry external from the array and sensing circuitry via local I/O lines). As such, a number of embodiments of the present disclosure can enable performing operations and compute functions associated therewith using less power than various previous approaches. Additionally, since a number of embodiments provide an ability to transfer data without the need to transfer data across local and/or global I/O lines and/or external data buses, a number of embodiments can enable an improved processing capability as compared to previous approaches.

The sense amplifier 206 can further include equilibration circuitry 214, which can be configured to equilibrate the digit lines 205-1 (D) and 205-2 (D)_. In this example, the equilibration circuitry 214 comprises a transistor 224 coupled between digit lines 205-1 (D) and 205-2 (D)_. The equilibration circuitry 214 also comprises transistors 225-1 and 225-2 each having a first source/drain region coupled to an equilibration voltage (e.g., VDD/2), where VDD is a supply voltage associated with the array. A second source/drain region of transistor 225-1 can be coupled digit line 205-1 (D), and a second source/drain region of transistor 225-2 can be coupled digit line 205-2 (D)_. Gates of transistors 224, 225-1, and 225-2 can be coupled together, and to an equilibration (EQ) control signal line 226. As such, activating EQ enables the transistors 224, 225-1, and 225-2, which effectively shorts digit lines 205-1 (D) and 205-2 (D)_ together and to the equilibration voltage (e.g., VDD/2).

Although FIG. 2 shows sense amplifier 206 comprising the equilibration circuitry 214, embodiments are not so limited, and the equilibration circuitry 214 may be implemented discretely from the sense amplifier 206, implemented in a different configuration than that shown in FIG. 2, or not implemented at all.

As shown in FIG. 2, the compute component 231 can also comprise a latch, which can be referred to herein as a secondary latch 264 or an “A” latch. The secondary latch 264 can be configured and operated in a manner similar to that described above with respect to the primary latch 215. In this example, the pair of cross coupled p-channel transistors (e.g., PMOS transistors) included in the secondary latch have their respective sources coupled to a supply voltage 212-2 (e.g., VDD), and the pair of cross coupled n-channel transistors (e.g., NMOS transistors) of the secondary latch have their respective sources selectively coupled to a reference voltage 212-1 (e.g., ground), such that the secondary latch is continuously enabled. The configuration of the compute component 231 is not limited to that shown in FIG. 2, and various other embodiments are feasible.

FIG. 3 is a schematic diagram illustrating circuitry for data replication in a memory device in accordance with a number of embodiments of the present disclosure. FIG. 3 shows eight sense amplifiers (e.g., sense amplifiers 0, 1, . . . , 7 shown at 306-0, 306-1, . . . , 306-7, respectively) each coupled to a respective pair of complementary sense lines (e.g., digit lines 305-1 and 305-2). FIG. 3 also shows eight compute components (e.g., compute components 0, 1, . . . , 7 shown at 331-0, 331-1, . . . , 331-7) each coupled to a respective sense amplifier (e.g., as shown for sense amplifier 0 at 306-0) via respective pass gates 307-1 and 307-2 and digit lines 305-1 and 305-2. For example, the pass gates can be connected as shown in FIG. 2 and can be controlled by an operation selection signal, Pass. For example, an output of the selection logic can be coupled to the gates of the pass gates 307-1 and 307-2 and digit lines 305-1 and 305-2. Corresponding pairs of the sense amplifiers and compute components can contribute to formation of the sensing circuitry indicated at 350-0, 350-1, . . . , 350-7.

The sense amplifiers 306-0, 306-1, . . . , 306-7 in FIG. 3 can each correspond to sense amplifier 206 shown in FIG. 2. The compute components 331-0, 331-1, . . . , 331-7 shown in FIG. 3 can each correspond to compute component 231 shown in FIG. 2. A combination of one sense amplifier with one compute component can contribute to the sensing circuitry (e.g., 350-0, 350-1, . . . , 350-7) of a portion of a DRAM memory subarray 325 configured to a shared I/O (SIO) line 355 shared by a number of sensing component stripes for subarrays and/or latch components, as described herein. The paired combinations of the sense amplifiers 306-0, 306-1, . . . , 306-7 and the compute components 331-0, 331-1, . . . , 331-7, shown in FIG. 3, can be included in the sensing component stripe. In some embodiments, data can be transferred via the SIO lines 355 between subarrays and/or banks in the memory device.

The memory device can include a number of sensing component stripes configured to include a number of a plurality of sense amplifiers and compute components (e.g., 306-0, 306-1, . . . , 306-7 and 331-0, 331-1, . . . , 331-7, respectively, as shown in FIG. 3) that can correspond to a number of the plurality of columns (e.g., 305-1 and 305-2 in FIG. 3) of the memory cells, where the number of sense amplifiers and/or compute components can be selectably coupled to the plurality of SIO lines (e.g., via column select circuitry 358-1 and 358-2). The column select circuitry can be configured to selectably sense data in a particular column of memory cells of a subarray by being selectably coupled to a plurality of (e.g., four, eight, and sixteen, among other possibilities) sense amplifiers and/or compute components.

The circuitry illustrated in FIG. 3 also shows column select circuitry 358-1 and 358-2 that is configured to implement data movement operations with respect to particular columns 322 of a subarray 325, the complementary digit lines 305-1 and 305-2 associated therewith, and the shared I/O line 355 (e.g., as directed by the controller 140 shown in FIG. 1). For example, column select circuitry 358-1 has select lines 0, 2, 4, and 6 that are configured to couple with corresponding columns, such as column 0 (332-0), column 2, column 4, and column 6. Column select circuitry 358-2 has select lines 1, 3, 5, and 7 that are configured to couple with corresponding columns, such as column 1, column 3, column 5, and column 7.

For example, as described herein, the array of memory cells can include an implementation of DRAM memory cells where the controller is configured, in response to a command, to move (e.g., copy, transfer, and/or transport) data from the source location to the destination location via a shared I/O line. In various embodiments, the source location can be in a first bank and the destination location can be in a second bank in the memory device and/or the source location can be in a first subarray of one bank in the memory device and the destination location can be in a second subarray of a different bank. The first subarray and the second subarray can be in the same section of a bank or the subarrays can be in different sections of the bank.

While example embodiments including various combinations and configurations of sensing circuitry, sense amplifiers, compute components, sensing component stripes, shared I/O lines, column select circuitry, multiplexers, latch components, latch stripes, and/or latches, etc., have been illustrated and described herein, embodiments of the present disclosure are not limited to those combinations explicitly recited herein. Other combinations and configurations of the sensing circuitry, sense amplifiers, compute components, sensing component stripes, shared I/O lines, column select circuitry, multiplexers, latch components, latch stripes, and/or latches, etc., disclosed herein are expressly included within the scope of this disclosure.

FIG. 4 is a schematic diagram illustrating sensing circuitry capable of implementing an XOR logical operation in accordance with a number of embodiments of the present disclosure. FIG. 4 shows a sense amplifier 406 coupled to a pair of complementary sense lines 405-1 and 405-2, logical operation select logic 413, and a compute component 431 coupled to the sense amplifier 406 via pass gates 407-1 and 407-2. The sense amplifier 406 shown in FIG. 4 can correspond to sense amplifier 206 shown in FIG. 2 and corresponding sense amplifiers 306 shown in FIG. 3. The compute component 431 shown in FIG. 4 can correspond to sensing circuitry, including compute component, 150 in FIG. 1. The logical operation selection logic 413 shown in FIG. 4 can correspond to logical operation selection logic 213 shown in FIG. 2. The gates of the pass gates 407-1 and 407-2 can be controlled by a logical operation selection logic 413 signal, (e.g., Pass). For example, an output of the logical operation selection logic 413 can be coupled to the gates of the pass gates 407-1 and 407-2.

In some approaches, the compute components 431 can comprise respective stages (e.g., shift cells) of a loadable shift register configured to shift data values left and right. For example, as illustrated in FIG. 4, each compute component 431 (e.g., stage) of the shift register comprises a pair of right-shift transistors 481 and 486, a pair of left-shift transistors 489 and 490, and a pair of inverters 487 and 488. The signals PHASE 1R, PHASE 2R, PHASE 1L, and PHASE 2L can be applied to respective control lines 482, 483, 491 and 492 to enable/disable feedback on the latches of the corresponding compute components 431 in association with performing logical operations and/or shifting data in accordance with embodiments described herein.

However, in a number of embodiments, the compute components can comprise respective storage locations that may be used for data replication. For example, each compute component 431 can include at least one storage location that may be used as part of a data replication operation as described in more detail in connection with FIGS. 5, 6A, and 6B, herein. In a number embodiments, each compute component 431 (and/or each storage location associated with each compute component) may be a transparent latch, which may allow data values to be copied for as long as a clock signal is present.

The sensing circuitry shown in FIG. 4 shows operation selection logic 413 coupled to a number of logic selection control input control lines, including ISO, TF, TT, FT, and FF. Selection of a logical operation from a plurality of logical operations is determined from the condition of logic selection control signals on the logic selection control input lines, as well as the data values present on the pair of complementary sense lines 405-1 and 405-2 when isolation transistors 450-1 and 450-2 are enabled via an ISO control signal being asserted.

In a number of embodiments, the operation selection logic 413 can include four logic selection transistors: logic selection transistor 462 coupled between the gates of the swap transistors 442 and a TF signal control line, logic selection transistor 452 coupled between the gates of the pass gates 407-1 and 407-2 and a TT signal control line, logic selection transistor 454 coupled between the gates of the pass gates 407-1 and 407-2 and a FT signal control line, and logic selection transistor 464 coupled between the gates of the swap transistors 442 and a FF signal control line. Gates of logic selection transistors 462 and 452 are coupled to the true sense line through isolation transistor 450-1 (having a gate coupled to an ISO signal control line). Gates of logic selection transistors 464 and 454 are coupled to the complementary sense line through isolation transistor 450-2 (also having a gate coupled to an ISO signal control line).

Data values present on the pair of complementary sense lines 405-1 and 405-2 can be loaded into the compute component 431 via the pass gates 407-1 and 407-2. When the pass gates 407-1 and 407-2 are OPEN, data values on the pair of complementary sense lines 405-1 and 405-2 are passed to the compute component 431 and/or storage locations associated with the compute component 431. The data values on the pair of complementary sense lines 405-1 and 405-2 can be the data value stored in the sense amplifier 406 when the sense amplifier is fired. In this example, the logical operation selection logic signal, Pass, is high to OPEN the pass gates 407-1 and 407-2.

The ISO, TF, TT, FT, and FF control signals can operate to select a logical function to implement based on the data value (“B”) in the sense amplifier 406 and the data value (“A”) in the compute component 431. In particular, the ISO, TF, TT, FT, and FF control signals are configured to select the logical function to implement independent from the data value present on the pair of complementary sense lines 405-1 and 405-2 (although the result of the implemented logical operation can be dependent on the data value present on the pair of complementary sense lines 405-1 and 405-2. For example, the ISO, TF, TT, FT, and FF control signals select the logical operation to implement directly since the data value present on the pair of complementary sense lines 405-1 and 405-2 is not passed through logic to operate the gates of the pass gates 407-1 and 407-2.

Additionally, FIG. 4 shows swap transistors 442 configured to swap the orientation of the pair of complementary sense lines 405-1 and 405-2 between the sense amplifier 406 and the compute component 431. When the swap transistors 442 are OPEN, data values on the pair of complementary sense lines 405-1 and 405-2 on the sense amplifier 406 side of the swap transistors 442 are oppositely-coupled to the pair of complementary sense lines 405-1 and 405-2 on the compute component 431 side of the swap transistors 442, and thereby loaded into the compute component 431.

The logical operation selection logic 413 signal Pass can be activated (e.g., high) to OPEN the pass gates 407-1 and 407-2 (e.g., conducting) when the ISO control signal line is activated and either the TT control signal is activated (e.g., high) with data value on the true sense line is “1” or the FT control signal is activated (e.g., high) with the data value on the complement sense line is “1.”

The data value on the true sense line being a “1” OPENs logic selection transistors 452 and 462. The data value on the complimentary sense line being a “1” OPENs logic selection transistors 454 and 464. If the ISO control signal or either the respective TT/FT control signal or the data value on the corresponding sense line (e.g., sense line to which the gate of the particular logic selection transistor is coupled) is not high, then the pass gates 407-1 and 407-2 will not be OPENed by a particular logic selection transistor.

The logical operation selection logic signal Pass* can be activated (e.g., high) to OPEN the swap transistors 442 (e.g., conducting) when the ISO control signal line is activated and either the TF control signal is activated (e.g., high) with data value on the true sense line is “1,” or the FF control signal is activated (e.g., high) with the data value on the complement sense line is “1.” If either the respective control signal or the data value on the corresponding sense line (e.g., sense line to which the gate of the particular logic selection transistor is coupled) is not high, then the swap transistors 442 will not be OPENed by a particular logic selection transistor.

The Pass* control signal is not necessarily complementary to the Pass control signal. It is possible for the Pass and Pass* control signals to both be activated or both be deactivated at the same time. However, activation of both the Pass and Pass* control signals at the same time shorts the pair of complementary sense lines together, which may be a disruptive configuration to be avoided.

The sensing circuitry illustrated in FIG. 4 is configured to select one of a plurality of logical operations to implement directly from the four logic selection control signals (e.g., logical operation selection is not dependent on the data value present on the pair of complementary sense lines). Some combinations of the logic selection control signals can cause both the pass gates 407-1 and 407-2 and swap transistors 442 to be OPEN at the same time, which shorts the pair of complementary sense lines 405-1 and 405-2 together. According to a number of embodiments of the present disclosure, the logical operations which can be implemented by the sensing circuitry illustrated in FIG. 4 can be the logical operations summarized in the logic tables shown in FIG. 7.

FIG. 5 is a schematic diagram illustrating an example wiring configuration for data replication in accordance with a number of embodiments of the present disclosure. As shown in FIG. 5, a plurality of storage locations 565-1, . . . , 565-N may be provided to store (e.g., latch) a data value. In some embodiments, storage location 565-1 and storage location 565-N are logically or physically adjacent storage locations, and may correspond to an “A” latch 264 illustrated in FIG. 2. The storage locations 565-1, . . . , 565-N may include an input (D), output (Q), and/or write enable pin(s) (WE).

The output (Q) of storage location 565-1 may be coupled to a first input of multiplexer 563, and an output of multiplexer 563 may be coupled to an input (D) of storage location 565-N. In some embodiments, a second input of multiplexer 563 may be configured to receive write data via write data signal line 585, for example, write data received from an additional (e.g., neighboring) latch. The additional latch may be analogous to “B” latch 215 illustrated in FIG. 2 and/or sense amplifier 406 illustrated in FIG. 4. In a number of embodiments, the write data may include resultant data from logic operations.

As shown in FIG. 5, the multiplexer 563 may be configured to receive write control signals via write control signal line 584. The write control signals may include copy, write, and/or erase signals. Although illustrated as a 2:1 multiplexer, multiplexer 563 may include additional pins. For example, multiplexer 563 may be a 4:1 multiplexer, 8:1 multiplexer, etc.

In some embodiments, control storage logic 561 may be provided. The control storage logic 561 may be configured to assert a replicate enable signal, which may be propagated from the output (Q) of the control storage 561 to a first input of AND logic gate 567. In a number of embodiments, the replicate enable signal may be stored at a different latch (not shown in FIG. 5) prior to being asserted by the control storage logic 561. A second input of the AND logic gate 567 may be configured to receive a signal from control signal line 566. The control signal line 566 may be a global control signal line that is coupled to each storage location 565-1, . . . , 565-N. For example, the control signal line 566 may be configured to assert a replicate signal that may be received at one or more of the storage locations 565-1, . . . , 565-N to cause a data replication operation to be performed. In a number of embodiments, a data replication signal may be asserted on control signal line 566 to cause a replicated data value to be transferred from one storage location (e.g., storage location 565-1) to a second storage location (e.g., storage location 565-N).

The output of the AND logic gate 567 may be coupled to a first input of OR logic gate 568. In a number of embodiments, a second input of OR logic gate 568 may be coupled to the write control signal line 584 and may receive write control signals, as described above. In some embodiments, the output of OR logic gate 568 may be coupled to the write enable pin (WE) of storage location 565-N, and the output of multiplexer 563 may be coupled to the input (D) of storage location 565-N.

The components illustrated in FIG. 5 may be used to perform the data replication operations described in FIGS. 6A and 6B. For example, the examples of data replication described in FIGS. 6A and 6B may be performed by asserting a signal from the control storage 561, storage locations 565-1, . . . , 565-N, control signal line 566, and/or signals from multiplexer 563 to cause data to be replicated and/or cause the replicated data to be transferred between the storage locations 565-1, . . . , 565-N. Although not explicitly illustrated in FIGS. 6A and 6B, the AND logic gate 567 and/or the OR logic gate 568 may be provided and coupled to the storage locations 565-1, . . . , 565-N and may be used to facilitate data replication in accordance with a number of embodiments. The components illustrated in FIG. 5 may be configured to generate and/or store a replicate mask (e.g., replicate mask 671 shown in FIGS. 6A and 6B, and as discussed in more detail in connection with FIGS. 6A and 6B).

FIG. 6A is a flow diagram illustrating an example of data replication in accordance with a number of embodiments of the present disclosure. A plurality of storage locations 673-1, . . . , 673-N may have a replicate mask 671 associated therewith. The replicate mask 671 may include a plurality of associated replicate mask bits 672-1, . . . , 673-N. The plurality of storage locations may be analogous to “A” storage location 264 illustrated in FIG. 2 and/or storage locations 565-1, . . . , 565-N illustrated in FIG. 5. As shown in FIG. 6A, data may flow between storage locations of the same type (e.g., storage locations having a same physical location or logical position with respect to respective sensing circuitries and/or respective compute components to which the storage locations are associated. In some embodiments, the storage location may comprise one or more transparent latches. As used herein, transparent latches are latches that are level triggered as opposed to edge triggered. For example, a transparent latch may be configured to transfer data from input to output for an amount of time that a control signal is asserted.

FIG. 6B is a flow diagram illustrating another example of data replication in accordance with a number of embodiments of the present disclosure. A plurality of storage locations 673-1, . . . , 673-N may have a replicate mask 671 associated therewith. The replicate mask 671 may include a plurality of associated replicate mask bits 672-1, . . . , 673-N. The plurality of storage locations may be analogous to “A” storage location 264 illustrated in FIG. 2 and/or storage locations 565-1, . . . , 565-N illustrated in FIG. 5. As shown in FIG. 6A, data may flow between storage locations of the same type (e.g., storage locations having a same physical location or logical position with respect to respective sensing circuitries and/or respective compute components in which the respective storage locations are associated. In some embodiments, the replicate mask 671 may be contained in the “B” storage location, such as “B” storage location 206 illustrated in FIG. 2 and/or may be contained in the “B” storage location or in a neighboring compute component.

In the example of FIG. 6B, replicate mask bits 672-2 and 672-3 are enabled, as indicated by the hatching, and replicate mask bits 672-1 and 672-N are not enabled. If the initial data stored in the plurality of storage locations 673-1, . . . , 673-N is “WXYZ,” a resulting data propagation operation in the leftward direction would yield “WZZZ.” For example, if the initial data value “W” is stored in storage location 673-N, the initial data value “X” is stored in storage location 673-3, the initial data value “Y” is stored in storage location 673-2, and the initial data value “Z” is stored in storage location 673-1, a data replication operation in the leftward direction would yield “WZZZ,” because the replicate mask bits 672-2 and 672-3 cause data value “Z” to be replicated from storage location 673-1 to storage location 673-2 as indicated by the arrow 674-1, and from storage location 673-1 to storage location 673-3, as indicated by the arrow 674-2. In this example, data value “W” is stored at storage location 673-N, because replicate mask bit 672-N is not enabled. That is, in a number of embodiments, data values may not move between storage locations with disabled replicate mask bits, but data values may move between storage locations with enabled replicate masks bits.

FIG. 7 is a logic table illustrating selectable logic operation results implemented by a sensing circuitry shown in FIG. 4 in accordance with a number of embodiments of the present disclosure. The four logic selection control signals (e.g., TF, TT, FT, and FF), in conjunction with a particular data value present on the complementary sense lines, can be used to select one of plural logical operations to implement involving the starting data values stored in the sense amplifier 406 and compute component 431. The four control signals, in conjunction with a particular data value present on the complementary sense lines, controls the continuity of the pass gates 407-1 and 407-2 and swap transistors 442, which in turn affects the data value in the compute component 431 and/or sense amplifier 406 before/after firing. The capability to selectably control continuity of the swap transistors 442 facilitates implementing logical operations involving inverse data values (e.g., inverse operands and/or inverse result), among others.

Logic Table 7-1 illustrated in FIG. 7 shows the starting data value stored in the compute component 431 shown in column A at 744, and the starting data value stored in the sense amplifier 406 shown in column B at 745. The other 3 column headings (756, 770, and 771) in Logic Table 7-1 refer to the continuity of the pass gates 407-1 and 407-2, and the swap transistors 442, which can respectively be controlled to be OPEN or CLOSED depending on the state of the four logic selection control signals (e.g., TF, TT, FT, and FF), in conjunction with a particular data value present on the pair of complementary sense lines 405-1 and 405-2. The “Not Open” column corresponds to the pass gates 407-1 and 407-2 and the swap transistors 442 both being in a non-conducting condition, the “Open True” corresponds to the pass gates 407-1 and 407-2 being in a conducting condition, and the “Open Invert” corresponds to the swap transistors 442 being in a conducting condition. The configuration corresponding to the pass gates 407-1 and 407-2 and the swap transistors 442 both being in a conducting condition is not reflected in Logic Table 7-1 since this results in the sense lines being shorted together.

Via selective control of the continuity of the pass gates 407-1 and 407-2 and the swap transistors 442, each of the three columns of the upper portion of Logic Table 7-1 can be combined with each of the three columns of the lower portion of Logic Table 7-1 to provide 3×3=9 different result combinations, corresponding to nine different logical operations, as indicated by the various connecting paths shown at 775. The nine different selectable logical operations that can be implemented by the sensing circuitry are summarized in Logic Table 7-2 illustrated in FIG. 7, including an XOR logical operation.

The columns of Logic Table 7-2 illustrated in FIG. 7 show a heading 780 that includes the state of logic selection control signals. For example, the state of a first logic selection control signal is provided in row 776, the state of a second logic selection control signal is provided in row 777, the state of a third logic selection control signal is provided in row 778, and the state of a fourth logic selection control signal is provided in row 779. The particular logical operation corresponding to the results is summarized in row 747.

Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combination of the above embodiments, and other embodiments not specifically described herein will be apparent to those of skill in the art upon reviewing the above description. The scope of the one or more embodiments of the present disclosure includes other applications in which the above structures and processes are used. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.

In the foregoing Detailed Description, some features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

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Title Current Assignee Application Date Publication Date
반도체 메모리 장치 삼성전자주식회사 15 June 2009 23 December 2010
System and method for using a memory mapping function to map memory defects DELL PRODUCTS, L.P. 14 August 2008 18 February 2009
半導体信号処理装置 ルネサスエレクトロニクス株式会社 16 September 2008 05 November 2009
半導体記憶装置 HITACHI LTD 13 July 1994 02 February 1996
Digital computer ALLIANT COMPUTER SYSTEMS CORPORATION 17 June 1986 18 March 1987
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