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Patent Analysis of

Apparatuses and methods for random number generation

Updated Time 12 June 2019

Patent Registration Data

Publication Number

US10152304

Application Number

US15/995748

Application Date

01 June 2018

Publication Date

11 December 2018

Current Assignee

MICRON TECHNOLOGY, INC.

Original Assignee (Applicant)

MICRON TECHNOLOGY, INC.

International Classification

G06F7/58,G11C11/4091,G11C11/4096,G11C11/408,G11C7/06

Cooperative Classification

G06F7/588,G11C7/065,G11C11/4096,G11C11/4087,G11C11/4091

Inventor

LA FRATTA, PATRICK A.,LOVITT, JESSE F.,HUSH, GLEN E.,FINKBEINER, TIMOTHY P.

Patent Images

This patent contains figures and images illustrating the invention and its embodiment.

US10152304 Apparatuses random 1 US10152304 Apparatuses random 2 US10152304 Apparatuses random 3
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Abstract

The present disclosure includes apparatuses and methods for random number generation. An example method includes operating a sense amplifier of a memory device to perform sensing a first voltage on a first sense line coupled to the sense amplifier and sensing a second voltage on a complementary second sense line coupled to the sense amplifier. The example method further includes generating a random number by detecting a voltage differential between the first sense line and the complementary second sense line.

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Claims

1. An apparatus, comprising:

a memory device;a sense amplifier on the memory device, the sense amplifier configured to:

sense a residual first voltage on a first sense line coupled to the sense amplifier; and sense a residual second voltage on a complementary second sense line coupled to the sense amplifier; and wherein a random number is generated by detection of a residual voltage differential between the first sense line and the complementary second sense line.

2. The apparatus of claim 1, wherein the memory device is configured to perform an equilibration operation such that the residual first voltage on the first sense line and the residual second voltage on the complementary second sense line are both in an equilibration state.

3. The apparatus of claim 1, wherein the memory device is configured to generate the random number from electronic noise in a first electrical conductor physically connected with the first sense line and a second electrical conductor physically connected with the complementary second sense line.

4. The apparatus of claim 1, wherein the memory device is configured to generate a differential in the residual first voltage and the residual second voltage via detection of unequal residual voltages in the first sense line and the second sense line.

5. The apparatus of claim 1, wherein the memory device is configured to:

perform an equilibration operation that results in the residual first and second voltages being unequal in the first sense line and the second sense line; and wherein thermal noise enables the residual first and second voltages to be unequal in the first sense line and the second sense line.

6. The apparatus of claim 1, wherein the memory device is configured to:

generate a random data unit from detection of the residual voltage differential between the first sense line and the complementary second sense line; and generate the random number utilizing the random data unit.

7. An apparatus, comprising:

an array of memory cells;a sense amplifier coupled to the array, the sense amplifier configured to:

determine a residual voltage differential on a first sense line and a complementary second sense line by the sense amplifier being selectably coupled to the first and the second complementary sense lines; and enable determination of a random data unit based on the determined residual voltage differential.

8. The apparatus of claim 7, wherein the apparatus is configured to move the random data unit from storage in the sense amplifier to storage by a pair of complementary memory cells in a row of the array.

9. The apparatus of claim 7, wherein the apparatus is configured to:

access the random data unit; and generate a random number based on the random data unit.

10. The apparatus of claim 7, wherein the apparatus is configured to:

determine a residual voltage differential on each of respective pairs of complementary sense lines; and generate a vector of data units with a length that corresponds to a number of pairs of complementary sense lines of the array.

11. The apparatus of claim 7, wherein the apparatus further comprises:

a controller, wherein the controller is configured to:

divide a vector of data units that corresponds to a number of pairs of complementary sense lines into a plurality of vector elements; and generate a plurality of random numbers from the plurality of vector elements; and wherein each of the random numbers is a selected plurality of data units in the vector elements.

12. The apparatus of claim 7, wherein the apparatus is configured to:

determine a first residual voltage differential at a first time by a first sense operation performed on the first sense line and the complementary second sense line to yield a first random data unit; and determine a second residual voltage differential at a second time by a second sense operation performed on the first sense line and the complementary second sense line to yield a second random data unit; and wherein the first random data unit is different from the second random data unit due to electronic noise that causes the residual voltage on the first sense line and the complementary second sense line to randomly vary with passage of time.

13. The apparatus of claim 7, wherein the apparatus is configured to:

perform a sense operation on the first sense line and the complementary second sense line to determine a residual voltage differential in a range of 15-45 millivolts; and perform a read operation on a memory cell coupled to the first sense line and the complementary second sense line to determine a voltage differential of a programmed data unit in a range of 50-100 millivolts; and wherein a lowest millivolt value in the residual voltage differential range is greater than a highest millivolt value in a range of inherent offsets for memory cells and sense amplifiers of the array.

14. A system, comprising:

sensing circuitry coupled to an array of memory cells, the sensing circuitry including a sense amplifier coupled to a respective sense line and configured to perform random number generation operations; and a random number component coupled to the array and sensing circuitry; and wherein the random number component is configured to generate a random number from a residual voltage differential sensed by the sense amplifier between a first sense line and a complementary second sense line in the array.

15. The system of claim 14, wherein:

the sensing circuitry further comprises equilibrate circuitry configured to equilibrate complementary programmed memory cells selectably coupled to the first sense line and the complementary second sense line; and the random number component generates the random number from a residual voltage differential of the first sense line and the complementary second sense line.

16. The system of claim 14, wherein the random number component is further configured to:

receive a request for performance of a random number generation operation; and execute coded instructions to initiate the performance of the random number generation operation.

17. The system of claim 14, wherein the system further comprises:

compensate circuitry coupled to the sense amplifier and the respective sense line; and wherein the compensate circuitry is configured to compensate for an effect of an inherent offset in the sense amplifier or the respective sense line on the sensed differential of the residual voltage differential.

18. The system of claim 14, wherein the system further comprises:

a controller selectably coupled to a row of a plurality of memory cells in the array and the sensing circuitry; and wherein the controller is configured to direct generation of random numbers based on residual voltage differentials sensed by a plurality of sense amplifiers on a corresponding plurality of complementary sense lines.

19. The system of claim 14, wherein the system further comprises:

a controller selectably coupled to a row of a plurality of complementary memory cells in the array and the sensing circuitry; and wherein the controller is configured to generate a vector of data units with a length that corresponds to a number of the plurality of complementary memory cells in the row.

20. The system of claim 14, wherein the system further comprises:

a controller selectably coupled to a row of a plurality of complementary memory cells in the array and the sensing circuitry; and wherein the controller is configured to generate a vector of data units with a length that corresponds to a number of random data units generated from the residual voltage differentials sensed by a respective plurality of sense amplifiers.

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Claim Tree

  • 1
    1. An apparatus, comprising:
    • a memory device
    • a sense amplifier on the memory device, the sense amplifier configured to: sense a residual first voltage on a first sense line coupled to the sense amplifier
    • and sense a residual second voltage on a complementary second sense line coupled to the sense amplifier
    • and wherein a random number is generated by detection of a residual voltage differential between the first sense line and the complementary second sense line.
    • 2. The apparatus of claim 1, wherein
      • the memory device is configured to perform an equilibration operation such that the residual first voltage on the first sense line and the residual second voltage on the complementary second sense line are both in an equilibration state.
    • 3. The apparatus of claim 1, wherein
      • the memory device is configured to generate the random number from electronic noise in a first electrical conductor physically connected with the first sense line and a second electrical conductor physically connected with the complementary second sense line.
    • 4. The apparatus of claim 1, wherein
      • the memory device is configured to generate a differential in the residual first voltage and the residual second voltage via detection of unequal residual voltages in the first sense line and the second sense line.
    • 5. The apparatus of claim 1, wherein
      • the memory device is configured to: perform an equilibration operation that results in the residual first and second voltages being unequal in the first sense line and the second sense line; and wherein
    • 6. The apparatus of claim 1, wherein
      • the memory device is configured to: generate a random data unit from detection of the residual voltage differential between the first sense line and the complementary second sense line; and generate the random number utilizing the random data unit.
  • 7
    7. An apparatus, comprising:
    • an array of memory cells
    • a sense amplifier coupled to the array, the sense amplifier configured to: determine a residual voltage differential on a first sense line and a complementary second sense line by the sense amplifier being selectably coupled to the first and the second complementary sense lines
    • and enable determination of a random data unit based on the determined residual voltage differential.
    • 8. The apparatus of claim 7, wherein
      • the apparatus is configured to move the random data unit from storage in the sense amplifier to storage by a pair of complementary memory cells in a row of the array.
    • 9. The apparatus of claim 7, wherein
      • the apparatus is configured to: access the random data unit; and generate a random number based on the random data unit.
    • 10. The apparatus of claim 7, wherein
      • the apparatus is configured to: determine a residual voltage differential on each of respective pairs of complementary sense lines; and generate a vector of data units with a length that corresponds to a number of pairs of complementary sense lines of the array.
    • 11. The apparatus of claim 7, wherein
      • the apparatus further comprises:
    • 12. The apparatus of claim 7, wherein
      • the apparatus is configured to: determine a first residual voltage differential at a first time by a first sense operation performed on the first sense line and the complementary second sense line to yield a first random data unit; and determine a second residual voltage differential at a second time by a second sense operation performed on the first sense line and the complementary second sense line to yield a second random data unit; and wherein
    • 13. The apparatus of claim 7, wherein
      • the apparatus is configured to: perform a sense operation on the first sense line and the complementary second sense line to determine a residual voltage differential in a range of 15-45 millivolts; and perform a read operation on a memory cell coupled to the first sense line and the complementary second sense line to determine a voltage differential of a programmed data unit in a range of 50-100 millivolts; and wherein
  • 14
    14. A system, comprising:
    • sensing circuitry coupled to an array of memory cells, the sensing circuitry including a sense amplifier coupled to a respective sense line and configured to perform random number generation operations
    • and a random number component coupled to the array and sensing circuitry
    • and wherein the random number component is configured to generate a random number from a residual voltage differential sensed by the sense amplifier between a first sense line and a complementary second sense line in the array.
    • 15. The system of claim 14, wherein
      • : the sensing circuitry further comprises
    • 16. The system of claim 14, wherein
      • the random number component is further configured to: receive a request for performance of a random number generation operation; and execute coded instructions to initiate the performance of the random number generation operation.
    • 17. The system of claim 14, wherein
      • the system further comprises:
    • 18. The system of claim 14, wherein
      • the system further comprises:
    • 19. The system of claim 14, wherein
      • the system further comprises:
    • 20. The system of claim 14, wherein
      • the system further comprises:
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Description

TECHNICAL FIELD

The present disclosure relates generally to semiconductor memory and methods, and more particularly, to apparatuses and methods for random number generation.

BACKGROUND

Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic systems. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), among others.

Electronic systems often include a number of processing resources (e.g., one or more processors), which may retrieve and execute instructions and store the results of the executed instructions to a suitable location. A processor can comprise a number of functional units such as arithmetic logic unit (ALU) circuitry, floating point unit (FPU) circuitry, and a combinatorial logic block, for example, which can be used to execute instructions by performing an operation on data (e.g., one or more operands). As used herein, an operation can be, for example, a Boolean operation, such as AND, OR, NOT, NOT, NAND, NOR, and XOR, and/or other operations (e.g., invert, shift, arithmetic, statistics, among many other possible operations). For example, functional unit circuitry may be used to perform the arithmetic operations, such as addition, subtraction, multiplication, and division on operands, via a number of logical operations.

A number of components in an electronic system may be involved in providing instructions to the functional unit circuitry for execution. The instructions may be executed, for instance, by a processing resource such as a controller and host processor. Data (e.g., the operands on which the instructions will be executed) may be stored in a memory array that is accessible by the functional unit circuitry. The instructions and data may be retrieved from the memory array and sequenced and buffered before the functional unit circuitry begins to execute instructions on the data. Furthermore, as different types of operations may be performed in one or multiple clock cycles through the functional unit circuitry, intermediate results of the instructions and data may also be sequenced and buffered.

In many instances, the processing resources (e.g., processor and associated functional unit circuitry) may be external to the memory array, and data is accessed via a bus between the processing resources and the memory array to execute a set of instructions. Processing performance may be improved in a processing in memory device, in which a processor may be implemented internally and near to a memory (e.g., directly on a same chip as the memory array). A processing in memory device may save time by reducing and eliminating external communications and may also conserve power. However, the potential for other functions, such as read and write operations, being performed in addition to processing operations may influence the data processing time of the processing in memory device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a block diagram of an apparatus in the form of a computing system including a memory device in accordance with a number of embodiments of the present disclosure.

FIG. 1B is a block diagram of a bank section of a memory device in accordance with a number of embodiments of the present disclosure.

FIGS. 2A-2B are schematic diagrams illustrating sensing circuitry in accordance with a number of embodiments of the present disclosure.

FIG. 3 is a schematic diagram of a memory device in accordance with a number of embodiments of the present disclosure.

FIGS. 4A-4B illustrate waveform diagrams showing signals on sense lines corresponding to a number of logical operations and random number generation operations in accordance with a number of embodiments of the present disclosure.

FIG. 5 illustrates a timing diagram associated with performing a number of logical operations using sensing circuitry in accordance with a number of embodiments of the present disclosure.

FIG. 6 illustrates a timing diagram associated with performing a number of random number generation operations using sensing circuitry in accordance with a number of embodiments of the present disclosure.

DETAILED DESCRIPTION

The present disclosure includes apparatuses and methods for random number generation (e.g., for use with a memory device having DRAM, among other types of memory). In at least one embodiment, a method includes operating the memory device for random number generation by operating a sense amplifier of a memory device to perform sensing a first voltage on a first sense line coupled to the sense amplifier and sensing a second voltage on a complementary second sense line coupled to the sense amplifier. The example method further includes generating a random number by detecting a voltage differential between the first sense line and the complementary second sense line.

One of the objectives of random number generation may be that an output of a random number generation algorithm is not determined by a programmer and/or is not predictable based on underlying parameters of the algorithm itself. Random numbers have a variety of uses. Examples of applications that may use random number samples can include reducing aggregated error in applications where rounding is necessary, application of probabilistic models to make predictions based thereon, sampling values from probability densities, simulating stochastic processes, such as behavior of materials or financial markets, performing Monte Carlo simulations to approximate difficult to compute values, or adding additional security to passwords and encryption keys, among other applications.

A repeated use of one or more “random numbers” could introduce unwanted correlations and/or predictability that undermine the true randomness of such numbers. To contribute to true randomness, a source of a large number of statistically independent numbers (random numbers) may be utilized, as described herein. The statistical independence of the random numbers may be based upon a voltage differential sensed as a residual voltage at each of a pair of memory cells (e.g., complementary memory cells, as described herein). Residual voltage is intended to mean a voltage in a sense line for a memory cell that is in an unprogrammed logic state. Being in the unprogrammed logic state may mean that neither of the pair of memory cells has been programmed to store a voltage associated with a data value (e.g., both memory cells remaining near 0.0 volts (V)) and/or that the pair of memory cells has been equilibrated to erase a stored data value (e.g., by bringing both of the memory cells and the respective sense lines to VDD/2, where VDD is a supply voltage associated with the array). The randomness of the differential may be based upon the physics of thermal noise conferring randomness to a value of the residual voltage at each of the paired memory cells.

In various embodiments, an apparatus, as described herein, may enable a large number of random numbers of various lengths to be generated. For example, random numbers of various lengths may be generated by splitting a vector of random data units, which may correspond to a length of a row of memory cells, to generate a plurality of vector elements. Different random numbers may be generated with passage of time by, for example, sequentially sampling the residual voltage differential at the paired memory cells such that the thermal noise causes random variance of the residual voltage differential over time.

In some embodiments, random number generation may be performed by a sense operation on an equilibrated first sense line and on an equilibrated second complementary sense line, for example, for a respective pair of memory cell in the unprogrammed logic state and/or the equilibrated state. The random number generation can be performed by determination of a differential between the first residual voltage sensed on the equilibrated first sense line and the second residual voltage sensed on the equilibrated second sense line. In various embodiments, random numbers may be generated by sensing the first residual voltage on the first sense line and sensing the second residual voltage on the second sense line, where the sense lines may be equilibrated.

In some memory devices (e.g., memory devices having a DRAM architecture, as described herein), the same memory array may be used for both random number generation and other logical operations (e.g., DRAM read, write, copy, and/or erase operations, among others). Performance of these two types of operations may utilize shared resources, for example, sense amplifiers and/or equilibrate circuitry in the sensing circuitry described herein. In some embodiments, processing in memory (PIM) logical operations (e.g., computation operations such as Boolean operations, among others) may be performed in the same memory array, for example, by a compute component coupled to the sense amplifier, as described herein.

In some DRAM implementations, the sensing circuitry (e.g., the sense amplifiers and/or compute components therein) may be equilibrated by the equilibrate circuitry following completion of a DRAM and/or PIM operation and/or prior to performance of a random number generation operation. The equilibration may be performed so that the sensing circuitry is prepared to receive different data values for a next DRAM and/or PIM operation and/or to place the complementary sense lines in the memory array in the equilibrated state in preparation for sensing residual voltage on the sense lines by a sense amplifier to generate the random number.

As described in more detail below, the embodiments can allow a host system to allocate a number of locations (e.g., sub-arrays (or “subarrays”)) and portions of subarrays, in one or more DRAM banks to hold (e.g., store) and/or process data. A host system and a controller may perform the address resolution on an entire block of program instructions (e.g., command instructions) and data and direct (e.g., control) allocation, storage, and/or movement (e.g., flow) of data and commands into allocated locations (e.g., subarrays and portions of subarrays) within a destination (e.g., target) bank. Executing some commands, for example, for performing DRAM write and/or read operations and/or for performing random number generation, as described herein, may utilize some of the normal DRAM signaling paths to the DRAM device.

In contrast, executing other commands may utilize signaling paths particular to performing the random number generation, such as the random number component 172 and the compensate circuitry 171 illustrated in FIG. 1A and the corresponding compensate circuitry 271 illustrated in more detail in FIG. 2A. As the reader will appreciate, while a DRAM bit vector operation (e.g., PIM) device is discussed with regard to some examples presented herein, embodiments are not limited to a PIM DRAM implementation.

In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how one or more embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and structural changes may be made without departing from the scope of the present disclosure.

As used herein, designators such as “X”, “Y”, “N”, “M”, etc., particularly with respect to reference numerals in the drawings, indicate that a number of the particular feature so designated can be included. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting. As used herein, the singular forms “a”, “an”, and “the” can include both singular and plural referents, unless the context clearly dictates otherwise. In addition, “a number of”, “at least one”, and “one or more” (e.g., a number of memory arrays) can refer to one or more memory arrays, whereas a “plurality of” is intended to refer to more than one of such things. Furthermore, the words “can” and “may” are used throughout this application in a permissive sense (i.e., having the potential to, being able to), not in a mandatory sense (i.e., must). The term “include,” and derivations thereof, means “including, but not limited to”. The terms “coupled” and “coupling” mean to be directly or indirectly connected physically or for access to and movement (transmission) of commands and/or data, as appropriate to the context. The terms “data”, “data units”, and “data values” are used interchangeably herein and can have the same meaning, as appropriate to the context.

The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number and the remaining digits identify an element or component in the figure. Similar elements or components between different figures may be identified by the use of similar digits. For example, 108 may reference element “08” in FIG. 1A, and a similar element may be referenced as 208 in FIG. 2A. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, the proportion and/or the relative scale of the elements provided in the figures are intended to illustrate certain embodiments of the present disclosure and should not be taken in a limiting sense.

FIG. 1A is a block diagram of an apparatus in the form of a computing system 100 including a memory device 120 in accordance with a number of embodiments of the present disclosure. As used herein, a memory device 120, controller/sequencer 140, random number component 172, memory array 130, sensing circuitry 150, logic 170, and/or compensate component 171 might also be separately considered an “apparatus.”

In previous approaches, data may be transferred from a memory array and sensing circuitry (e.g., via a bus comprising input/output (I/O) lines) to a processing resource such as a processor, microprocessor, and/or compute engine, which may comprise ALU circuitry and/or other functional unit circuitry configured to perform the appropriate operations. However, transferring data from the memory array and sensing circuitry to such processing resource(s) can involve significant time and/or power consumption. Even if the processing resource is located on a same chip as the memory array, significant power can be consumed in moving data out of the array to the compute circuitry, which can involve performing a sense line (which may be referred to herein as a digit line or data line) address access (e.g., firing of a column decode signal) in order to transfer data from sense lines onto I/O lines (e.g., local I/O lines), transferring the data peripheral to the array, which may be transferred to a cache in a host, and providing the data to the peripheral compute circuitry.

Furthermore, the circuitry of the processing resource(s) (e.g., a compute engine) may not conform to pitch rules associated with a memory array. For example, the memory cells of a memory array may have a 4F2 or 6F2 cell size, where “F” is a feature size corresponding to the cells. As such, the devices (e.g., logic gates) associated with ALU circuitry of previous PIM systems may not be capable of being formed on pitch with the memory cells, which can affect chip size and/or memory density, for example. A number of embodiments of the present disclosure can include the control circuitry and/or the sensing circuitry (e.g., including sense amplifiers and/or compute components), as described herein, being formed on pitch with the memory cells of the array and being configured to (e.g., being capable of performing) compute functions (e.g., operations), such as those described herein, on pitch with the memory cells. The sensing circuitry can, in some embodiments, be capable of performing data sensing and compute functions and at least temporary storage (e.g., caching) of data local to the array of memory cells.

In order to appreciate the performance of operations described herein, a discussion of an apparatus for implementing such techniques follows. For example, such an apparatus may be a memory device having PIM capabilities and an associated host, although embodiments are not limited to memory devices having PIM capabilities. As such, in some embodiments, program instructions (e.g., PIM commands) involving a memory device having PIM capabilities can distribute implementation of the PIM commands and data over multiple sensing circuitries that can implement operations and can move and store the PIM commands and data within the memory array (e.g., without having to transfer such back and forth over an A/C and data bus between a host and the memory device). Thus, data for a memory device having PIM capabilities can be accessed and used in less time and/or using less power. For example, a time and power advantage can be realized by increasing the speed, rate, and/or efficiency of data being moved around and stored in a computing system in order to process requested memory array operations. Such operations may include logical operations, such as reads and/or writes, etc., as DRAM operations and/or PIM operations, such as logical Boolean operations, data movement operations, etc., in addition to random number generation operations, among others described herein.

The system 100 illustrated in FIG. 1A can include a host 110 coupled (e.g., connected) to memory device 120, which includes the memory array 130. Host 110 can be a host system such as a personal laptop computer, a desktop computer, a tablet computer, a digital camera, a smart phone, or a memory card reader, among various other types of hosts. Host 110 can include a system motherboard and backplane and can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry). The system 100 can include separate integrated circuits or both the host 110 and the memory device 120 can be on the same integrated circuit. The system 100 can be, for instance, a server system and/or a high performance computing (HPC) system or a portion of either. Although the example shown in FIG. 1A illustrates a system having a Von Neumann architecture, embodiments of the present disclosure can be implemented in non-Von Neumann architectures, which may not include one or more components (e.g., CPU, ALU, etc.) often associated with a Von Neumann architecture.

For clarity, description of the system 100 has been simplified to focus on features with particular relevance to the present disclosure. For example, in various embodiments, the memory array 130 can be a DRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash array, and NOR flash array, for instance. The memory array 130 can include memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as data lines or digit lines). Although a single memory array 130 is shown in FIG. 1A, embodiments are not so limited. For instance, memory device 120 may include a number of memory arrays 130 (e.g., a number of banks of DRAM cells, NAND flash cells, etc.) in addition to a number of subarrays, as described herein.

The memory device 120 can include address circuitry 142 to latch address signals provided over a data bus 156 (e.g., an I/O bus from the host 110) by I/O circuitry 144 (e.g., provided to external ALU circuitry and to DRAM DQs via local I/O lines and global I/O lines). As used herein, DRAM DQs can enable input of data to and output of data from a bank (e.g., from and/or to the controller 140 and/or host 110) via a bus (e.g., data bus 156). During a write operation, a voltage (high=1, low=0) can be applied to a DQ (e.g., a pin). This voltage can be translated into an appropriate signal and stored in a selected memory cell. During a read operation, a data value read from a selected memory cell can appear at the DQ once access is complete and the output is enabled (e.g., by the output enable signal being low). At other times, DQs can be in a high impedance state, such that the DQs do not source or sink current and do not present a signal to the system. This also may reduce DQ contention when two or more devices (e.g., banks) share the data bus.

Status and exception information can be provided from the controller 140 on the memory device 120 to the host 110 through, for example, a high speed interface (HSI) out-of-band (OOB) bus 157. The bus 157 can be used by the host 110 to dispatch commands (e.g., PIM commands) to a plurality of memory devices 120-1, . . . , 120-N (not shown) to store those program instructions within a given bank of a memory device.

Address signals are received through address circuitry 142 and decoded by a row decoder 146 and a column decoder 152 to access the memory array 130. Data can be sensed (read) from memory array 130 by sensing voltage and/or current changes on sense lines (digit lines in FIGS. 2A-2B and 3), for example, using a number of sense amplifiers of the sensing circuitry 150. A sense amplifier can read and latch data values from a page (e.g., a row) of data from the memory array 130. Additional compute components, in some embodiments described herein, can be coupled to the sense amplifiers and can be used in combination with the sense amplifiers to sense, store (e.g., cache and buffer), perform compute functions (e.g., operations) on, and/or move data. The I/O circuitry 144 can be used for bi-directional data communication with host 110 over the data bus 156 (e.g., a 64 bit wide data bus). The write circuitry 148 can be used to write data to the memory array 130.

Controller 140 (e.g., bank control logic and sequencer) can decode signals (e.g., commands) provided by control bus 154 from the host 110. These signals can include chip enable signals, write enable signals, and/or address latch signals that can be used to control operations performed on the memory array 130, including data sense, data store, data movement, data compute (PIM), data read, data write, data erase, and/or random number generation operations, among other operations. Control circuitry having instructions (e.g., stored in hardware, such as an application-specific integrated circuit (ASIC), firmware, and/or software embodiments) can be associated with the controller 140. For example, random number generation, as described herein, can be controlled by a random number component 172 that, in some embodiments, may be associated with the controller 140 (e.g., of a bank). In various embodiments, the controller 140 can be responsible for issuing instructions from the host 110 and accessing the memory array 130. The controller 140 can be a state machine, a sequencer, or some other type of controller. The controller 140 can control shifting data (e.g., right or left) in a row of an array (e.g., memory array 130).

Examples of the sensing circuitry 150 are described further below (e.g., in connection with FIGS. 2A-2B). For instance, in various embodiments, the sensing circuitry 150 can include a number of sense amplifiers and/or a number of compute components. A compute component may serve as an accumulator and can be used to perform operations as directed by a controller 140 and/or a respective subarray controller (not shown) of each subarray (e.g., on data associated with complementary sense lines). In some embodiments, a compute component can be coupled to each sense amplifier (e.g., as shown at 231 and 206, respectively, in FIG. 2B) within the sensing circuitry 150 in each respective sensing component stripe coupled to a subarray (e.g., in sensing component stripes 124-0 and 124-1 coupled respectively to subarrays 125-0 and 125-1 shown in and described in connection with FIG. 1B). However, embodiments are not so limited. For example, in some embodiments, there may not be a 1:1 correlation between the number of sense amplifiers and compute components. For example, there may be more than one sense amplifier per compute component or more than one compute component per sense amplifier, which may vary between subarrays, banks, etc.

In a number of embodiments, the sensing circuitry 150 can be used to perform operations using data stored in memory array 130 as input and participate in movement of the data for reading, writing, logical, copy and/or transfer, and storage operations to a different location in the memory array 130 without transferring the data via a sense line address access (e.g., without firing a column decode signal). As such, various compute functions (PIM operations) can be performed using, and within, the sensing circuitry 150 rather than (or in association with) being performed by processing resources external to the sensing circuitry 150 (e.g., by a processor associated with host 110 and other processing circuitry, such as ALU circuitry, located on device 120, such as on controller 140 or elsewhere). Moreover, random number generation, as described herein, may be performed using the sense amplifier of the sensing circuitry to sense a residual voltage at a pair of complementary memory cells each coupled at corresponding positions on a respective pair of sense lines.

In various previous approaches, data associated with an operand, for instance, would be read from memory via sensing circuitry and provided to external ALU circuitry via I/O lines (e.g., via local I/O lines and global I/O lines). The external ALU circuitry could include a number of registers and would perform compute functions using the operands, and the result would be transferred back to the array via the I/O lines.

In contrast, as described herein, sensing circuitry 150 is configured to perform operations on data stored in memory array 130 and to store the result back to the memory array 130 without enabling a local I/O line and global I/O line coupled to the sensing circuitry 150. The sensing circuitry 150 can be formed on pitch with the memory cells of the array. Additional peripheral sense amplifiers and/or logic 170 (e.g., subarray controllers that each execute instructions for performing a respective operation) can be coupled to the sensing circuitry 150. The sensing circuitry 150 and the peripheral sense amplifier and logic 170 can cooperate in performing operations, according to some embodiments herein.

Logic, as described herein, is intended to mean hardware (e.g., in the form of an application specific integrated circuit (ASIC)) and/or firmware to implement one or more particular functions. One example of logic may include a state machine, as described herein. Another example may include an embedded processing resource. Logic can include instructions (e.g., PIM commands and/or microcode instructions) that can be sent to a memory device having processing capabilities to implement logical operations. As such, the logic may be associated with (e.g., located at and/or connected to) the host 110, the controller 140, and/or the memory array 130 (e.g., at logic 170).

Hence, in a number of embodiments, circuitry external to memory array 130 and sensing circuitry 150 is not needed to perform compute functions, as the sensing circuitry 150 can perform the appropriate operations in order to perform such compute functions (e.g., in a sequence of instructions) without the use of an external processing resource. Therefore, the sensing circuitry 150 may be used to complement or to replace, at least to some extent, such an external processing resource (or at least reduce the bandwidth consumption of transfer of data to and/or from such an external processing resource).

In a number of embodiments, the sensing circuitry 150 may be used to perform operations (e.g., to execute a sequence of instructions) in addition to operations performed by an external processing resource (e.g., host 110). For example, either of the host 110 and the sensing circuitry 150 may be limited to performing only certain operations and/or a certain number of operations.

Enabling a local I/O line and/or global I/O line can include enabling (e.g., turning on, activating) a transistor having a gate coupled to a decode signal (e.g., a column decode signal) and a source/drain coupled to the I/O line. However, embodiments are not limited to not enabling a local I/O line and/or global I/O line. For example, in a number of embodiments, the sensing circuitry 150 can be used to perform operations without enabling column decode lines of the array. However, the local I/O line(s) and/or global I/O line(s) may be enabled in order to transfer a result to a suitable location other than back to the memory array 130 (e.g., to an external register).

FIG. 1B is a block diagram of a bank section 123 of a memory device in accordance with a number of embodiments of the present disclosure. For example, bank section 123 can represent an example section of a number of bank sections of a bank of a memory device (e.g., bank section 0, bank section 1, . . . , bank section M−1). As shown in FIG. 1B, a bank section 123 can include a plurality of memory columns 122 shown horizontally as X (e.g., 4096, 8192, or 16,384 columns, among various possibilities) in an example DRAM bank and bank section. Additionally, the bank section 123 may be divided into subarray 0, subarray 1, . . . , and subarray N−1 (e.g., 32, 64, or 128 subarrays, among various possibilities) shown at 125-0, 125-1, . . . , 125-N−1, respectively, that are separated by amplification regions configured to be coupled to a data path. As such, the subarrays 125-0, 125-1, . . . , 125-N−1 can each have amplification regions 124-0, 124-1, . . . , 124-N−1 that correspond to sensing component stripe 0, sensing component stripe 1, . . . , and sensing component stripe N−1, respectively.

Each column 122 (e.g., each pair of sense or digit lines) is configured to be coupled to sensing circuitry 150, as described in connection with FIG. 1A and in more detail in connection with FIGS. 2A-2B and FIG. 3. As such, each column in a subarray can be coupled individually to a sense amplifier that contributes to a sensing component stripe for that subarray. For example, as shown in FIG. 1B, the bank section 123 can include sensing component stripe 0, sensing component stripe 1, . . . , sensing component stripe N−1 that each have sensing circuitry 150 with sense amplifiers that can, in various embodiments, be used as registers, cache and/or data buffering and that are coupled to each column 122 in the subarrays 125-0, 125-1, . . . , 125-N−1.

Each of the of the subarrays 125-0, 125-1, . . . , 125-N−1 can include a plurality of rows 119 shown vertically as Y (e.g., each subarray may include 256, 512, 1024 rows, among various possibilities) in an example DRAM bank. Embodiments are not limited to the example horizontal and vertical orientation of columns and rows described herein or the example numbers thereof. Each of the plurality of rows 119 can include pairs of complementary memory cells, for example as shown in and described in connection with FIG. 3. Each of the complementary memory cells of the pair can be coupled to one of a respective pair of sense lines at a position of the row on the sense lines. As such, the number of memory cells in a row can correspond to the number of sense lines that intersect that row, which may be double the number of columns, as described herein. For example, there may be 8192, 16,384, or 32,768 memory cells in the 4096, 8192, or 16,384 complementary pairs of memory cells in a row that intersects 4096, 8192, or 16,384 columns, among various possibilities, in an example DRAM bank and bank section.

The portions of the sensing circuitry 150 can be separated between a number of sensing component stripes 124 that are each physically associated with a subarray 125 of memory cells in a bank section 123, as shown in FIG. 1B. The sense amplifiers may sense data values stored in memory cells of the subarrays and/or the sense amplifiers may sense residual voltages on the sense lines. The residual voltages on the sense lines may be sensed following selectably coupled memory cells being equilibrated (e.g., with VDD/2) via the corresponding sense lines. The sense amplifiers may amplify the sensed data value voltages and/or the sensed residual voltages to full rail voltages for conversion of the sensed voltages from a pair of complementary memory cells to a data unit (e.g., a binary 0 or 1 data value) by determination of a voltage differential for either a read or a random number generation operation, among other possible operations. In some embodiments, the sense amplifiers may at least temporarily store (e.g., cache) sensed data units. The compute components may, in some embodiments, perform compute operations on the cached data units in the plurality of sensing component stripes 124. The plurality of sensing component stripes 124 may each be physically associated with a subarray 125 of memory cells in the bank section 123, as shown in FIG. 1B.

As shown in FIG. 1B, the bank section 123 can be associated with controller 140. The controller 140 shown in FIG. 1B can, in various examples, represent at least a portion of the functionality embodied by and contained in the controller 140 shown in FIG. 1A. The controller 140 can direct (e.g., control) input of commands and data 141 to the bank section 123 and/or output (e.g., movement) of data from the bank section 123 (e.g., to the host 110), along with control of random number generation in the bank section 123 by the random number component 172, as described herein. The bank section 123 can include the data bus 156 (e.g., a 64 bit wide data bus) to DRAM DQs, which can correspond to the data bus 156 shown and described in connection with FIGS. 1A and 1B. Each data bus 156 for each bank of subarrays (e.g., 125-0, 125-1, . . . , 125-N−1) can be referred to as a portion of a data bus that contributes to formation of a combined data bus (e.g., for a plurality of banks and/or memory devices). As such, in some embodiments, eight 64 bit wide data bus portions for eight banks can contribute to a 512 bit wide combined data bus. Alternatively or in addition, each bank can individually use the entirety of the 512 bit wide combined data bus, although one bank at a time. Various combinations of using the data bus portions also may be utilized. For example, one bank may use four data bus portions at the same time as four other banks each use one of the remaining four data bus portions, among other possibilities.

FIG. 2A is a schematic diagram illustrating sensing circuitry 250-1 in accordance with a number of embodiments of the present disclosure. FIG. 2A shows a sense amplifier 206 coupled to a respective pair of complementary sense lines 205-1 and 205-2. The sense amplifier 206 shown in FIG. 2A can correspond to a plurality of sense amplifiers in the sensing circuitry 150 shown in FIG. 1A and/or the sensing circuitry 150 associated with the plurality of sensing component stripes 124 shown in FIG. 1B, for example.

As shown and described in connection with FIG. 3, complementary memory cells are coupled to pairs of complementary sense lines 205-1 and 205-2 (e.g., as columns) shown in FIG. 2A. For example, a memory cell can comprise a transistor and a capacitor. The memory cells can be, for example, 1T1C DRAM cells each comprising a storage element (e.g., a capacitor) and an access device (e.g., a transistor), although other configurations can be used (e.g., 2T2C with two transistors and two capacitors per memory cell). In a number of embodiments, the memory cells may be destructive read memory cells (e.g., reading the data stored in the cell destroys the data such that the data originally stored in the cell may be refreshed after being read). The cells of the memory array can be arranged in rows coupled by access lines and columns coupled by pairs of complementary sense lines, for example, DIGIT(n−1)/DIGIT(n−1)_, DIGIT(n)/DIGIT(n)_, DIGIT(n+1)/DIGIT(n+1)_. The individual sense lines corresponding to each pair of complementary data lines can also be referred to as sense lines 205-1 (D) and 205-2 (D_) respectively. Although only three pairs of complementary sense lines (e.g., three columns) are shown in FIG. 3, embodiments of the present disclosure are not so limited. For example, an array of memory cells can include additional columns of memory cells and/or sense lines (e.g., 4,096, 8,192, 16,384, etc.).

Memory cells can be coupled to different sense lines and/or access lines. For example, a first source/drain region of an access transistor of a memory cell can be coupled to a sense line 205-1 (D), a second source/drain region of the access transistor of the memory cell can be coupled to a capacitor of the memory cell, and a gate of the access transistor of the memory cell can be coupled to an access line of the memory array.

As shown in FIG. 2A, the sensing circuitry 250-1 can comprise a sense amplifier 206 corresponding to a respective column of memory cells (e.g., coupled to respective pairs of complementary sense lines). The sense amplifier 206 can comprise, for example, a cross coupled latch, which can be referred to herein as a primary latch. A data storage state can include the sense amplifiers 206 storing a data unit. As used herein, a data unit can be referred to as a bit and/or a digit value.

In a number of examples, the sense amplifier 206 (or a compute component 231 as shown in and described in connection with FIG. 2B) can be in at least one of two states associated with the first mode and the second mode. As used herein, a state of a sense amplifier 206 can describe a transfer of data to or from the sense amplifier 206. The state of the sense amplifier 206 can also be described as whether the sense amplifier 206 is in an equilibration state or is storing a data unit (e.g., a binary 0 or 1 data value). For example, a sense amplifier can be configured to be in an initial state, wherein the initial state is one of an equilibration state and a data storage state.

According to various embodiments, a sense amplifier 206 can comprise a cross coupled latch. However, embodiments of the sense amplifier 206 are not limited to a cross coupled latch. For example, the sense amplifier 206 in FIG. 2A can be current-mode sense amplifier and/or single-ended sense amplifier (e.g., sense amplifier coupled to one data line). Embodiments of the present disclosure also are not limited to a folded data line architecture.

In a number of embodiments, a sense amplifier 206 can comprise a number of transistors formed on pitch with the transistors of a corresponding compute component (e.g., compute component 231 shown and described in connection with FIG. 2B) and/or the memory cells of an array (e.g., memory array 130 shown in FIG. 1A and/or memory cells 302/303 shown in FIG. 3) to which they are coupled, which may conform to a particular feature size (e.g., 4F2, 6F2, etc.). Sense amplifier 206 comprises a latch 215 including four transistors coupled to a pair of complementary sense lines D 205-1 and D_205-2. The latch 215 can be a cross coupled latch. For example, the gates of a pair of transistors, such as n-channel transistors (e.g., NMOS transistors) 227-1 and 227-2 can be cross coupled with the gates of another pair of transistors, such as p-channel transistors (e.g., PMOS transistors) 229-1 and 229-2. As described further herein, the latch 215 comprising transistors 227-1, 227-2, 229-1, and 229-2 can be referred to as a primary latch. However, embodiments are not limited to this example.

The voltages and/or currents on the respective sense lines 205-1 and 205-2 can be provided to the respective latch inputs 233-1 (S1) and 233-2 (S2) of the cross coupled latch 215 (e.g., the input of the primary latch). In this example, the latch input 233-1 is coupled to a first source/drain region of transistors 227-1 and 229-1 as well as to the gates of transistors 227-2 and 229-2. Similarly, the latch input 233-2 can be coupled to a first source/drain region of transistors 227-2 and 229-2 as well as to the gates of transistors 227-1 and 229-1.

In this example, a second source/drain region of transistors 227-1 and 227-2 can be commonly coupled to a negative control signal (RnlF) 228. A second source/drain region of transistors 229-1 and 229-2 can be commonly coupled to an active positive control signal (ACT) 265. The ACT signal 265 can be a supply voltage (e.g., VDD) and the RnlF signal can be a reference voltage (e.g., ground). RnlF signal 228 and ACT signal 265 can function as activating signals that enable the cross coupled latch 215.

The enabled cross coupled latch 215 can operate to amplify a differential voltage between latch input 233-1 (e.g., first common node) and latch input 233-2 (e.g., second common node) such that latch input 233-1 is driven to one of the ACT signal voltage and the RnlF signal voltage (e.g., to one of VDD and ground), and latch input 233-2 is driven to the other of the ACT signal voltage and the RnlF signal voltage. The ACT signal voltage and the RnlF signal voltage may correspond to the full rail voltages for conversion of the sensed voltages from the pair of complementary memory cells to a data unit (e.g., a binary 0 or 1 data value) by determination of the voltage differential for either a read or a random number generation operation, among other possible operations.

The sense amplifier 206 may also include equilibrate circuitry 214 configured to equilibrate sense line 205-1 and sense line 205-2 in association with, for example, preparing the sense amplifier for a logical operation and/or a random number generation operation. In this example, the equilibrate circuitry 214 comprises a transistor 224 having a first source/drain region coupled to a first source/drain region of transistor 225-1 and sense line 205-1. A second source/drain region of transistor 224 can be coupled to a first source/drain region of transistor 225-2 and sense line 205-2. A gate of transistor 224 can be coupled to gates of transistors 225-1 and 225-2.

The second source drain regions of transistors 225-1 and 225-2 can be coupled to an equilibration voltage 238, which can be equal to VDD/2, where VDD is a supply voltage associated with the array. The gates of transistors 224, 225-1, and 225-2 can be coupled to control signal 226 (EQ). As such, activating EQ can enable the transistors 224, 225-1, and 225-2, which can effectively short sense line 205-1 to sense line 205-2. Shorting the sense lines as such may substantially equilibrate the sense lines 205-1 and 205-2 to the equilibration voltage VDD/2. However, as described herein, a small residual voltage differential may remain between the complementary sense lines 205-1 and 205-2, which may be sensed at the complementary memory cells coupled to the complementary sense lines in a row of the array by the corresponding sense amplifier 206. In some embodiments, the residual voltage differential itself and/or variance in direction of the differential with time may result from, or be contributed to by, thermal noise causing random agitation of charge carriers in sense line 205-1 and sense line 205-2.

The sense amplifier 206 may also include compensate circuitry 271. The compensate circuitry 271 shown in FIG. 2A can, in various examples, represent at least a portion of the functionality embodied by and contained in the compensate circuitry 171 shown in FIG. 1A. The compensate circuitry 271 is configured to compensate for an inherent offset in the sense amplifier 206 and/or the respective sense lines 205-1 and 205-2 that may affect the sensed differential of the residual voltage (e.g., a magnitude of the differential).

As described herein, the sense amplifier 206 may be enabled (e.g., fired) to sense and/or store voltage potentials from two complementary memory cells coupled to adjacent sense lines 205-1 and 205-2, which may be on both sides of the sense amplifier 206. An inherent offset may be a resistance and/or a capacitance that is not equal on both sides of the sense amplifier 206. Variance in the resistance and/or capacitance may be caused by variation in construction and/or connection (e.g., within or exceeding manufacturing tolerances) of the sense lines and/or other circuitry of the memory array. An intended unbalanced layout and/or unintended process variations may result in resistance and/or capacitance that varies between both sides of the sense amplifier 206. Such variation may cause, for example, threshold voltages to vary several millivolts from transistor to transistor. For example, threshold voltages for NMOS transistors 227-1 and 227-2 and/or PMOS transistors 229-1 and 229-2 may be affected such that the performance of the sense amplifier 206 may be impaired (e.g., defective). Accordingly, the compensate circuitry 271 may be utilized to at least partially compensate (correct) such effects on the sense amplifier 206.

In the embodiment illustrated in FIG. 2A, the compensate circuitry 271 is split into a first portion 271-1 on the left side of the sense amplifier 206 and a second portion 271-2 on the right side. However, embodiments are not so limited. For example, the compensate circuitry 271 may be configured as a single portion on the left side or the right side of the sense amplifier 206, among other possible locations, to compensate the variation in resistance and/or capacitance.

In embodiments with the split portions of the compensate circuitry, each portion 271-1, 271-2 of the compensate circuitry can include a respective transistor 217-1, 217-2 (e.g., an NMOS transistor) and a respective capacitor 218-1, 218-2. In some embodiments, portion 271-1 can be coupled to sense line 205-1 and latch input 233-1 and portion 271-2 can be coupled to sense line 205-2 and latch input 233-2 of the cross coupled latch 215 of the sense amplifier 206. However, embodiments are not so limited in that the compensate circuitry 271 may be otherwise coupled to the sensing circuitry 250-1.

A compensate signal 290-1, 290-2 may be input to one or both portions of the compensate circuitry 271-1, 271-2. The compensate signals 290-1, 290-2 may be used to tune the sense amplifier 206 by effectively adding more resistance and/or capacitance to one side (e.g., via the respective sense line and/or the respective latch input) or the other side of the sense amplifier 206. Biasing the resistance and/or capacitance of one side may be implemented by applying a particular analog voltage level to either transistor 217-1, 217-2 and/or the respective capacitor 218-1, 218-2. The added resistance and/or capacitance could counteract inherent offsets of the sense amplifier 206, sense lines 205-1 and 205-2, and/or other circuitry connected to the sense amplifier or sense lines. Alternatively or in addition, a sense amplifier gain can be changed by adjusting a DC supply voltage higher or lower to which the sense lines are equilibrated (e.g., VDD/2).

In some embodiments, when all sense amplifiers are determined and/or are assumed to have the same or similar inherent offsets, compensate signals may be connected in common to all the sense amplifiers in a memory array 130. The compensate signals 290-1, 290-2 may be sent from a source external to the memory array 130 (e.g., by the controller 140 and/or the random number component 172 thereof). As such, the compensate signals may be similar to the RnlF signal 228, the ACT signal 265, and/or the EQ signal 226.

FIG. 2B is another schematic diagram illustrating sensing circuitry 250-2 in accordance with a number of embodiments of the present disclosure. FIG. 2B indicates that a number of sense amplifiers 206 can be coupled to respective pairs of complementary sense lines 205-1 and 205-2, and a corresponding number of compute components 231 can be coupled to the sense amplifiers 206 via pass gates 207-1 and 207-2. The sense amplifier 206 and compute component 231 shown in FIG. 2B can correspond to sensing circuitry 150 shown in FIG. 1A and/or the sensing circuitry 150 associated with the plurality of sensing component stripes 124 shown in FIG. 1B, for example. The sensing circuitry 250-2 shown in FIG. 2B includes logical operation selection logic 213, which can be operated as described further below. For purposes of clarity, the configuration shown in FIG. 2B does not include the compensate circuitry 271 illustrated in FIG. 1A. However, in various embodiments, compensate circuitry may be incorporated into the configuration shown in FIG. 2B.

As shown in FIG. 2B, the sensing circuitry 250-2 can comprise a sense amplifier 206, a compute component 231, and logical operation selection logic 213 corresponding to a respective column of memory cells (e.g., coupled to respective pairs of complementary sense lines). The sense amplifiers 206 can be configured, for example, as described with respect to FIG. 2A. The sensing circuitry 250-2 can be operated in both a pre-sensing mode (e.g., sense amplifiers 206 fired before logical operation control signal active) and post-sensing mode (e.g., sense amplifiers 206 fired after logical operation control signal active) with a result of a logical operation performed by the compute component 231 being initially stored in the sense amplifier 206.

As shown in FIG. 2B, the compute component 231 can comprise a latch, which can be referred to herein as a secondary latch 264. The secondary latch 264 can be configured and operated in a manner similar to that described above with respect to the primary latch 215. In some embodiments, a pair of cross coupled p-channel transistors (e.g., PMOS transistors) included in the secondary latch can have their respective sources coupled to a supply voltage 212-2 (e.g., VDD), and the pair of cross coupled n-channel transistors (e.g., NMOS transistors) of the secondary latch can have their respective sources selectively coupled to a reference voltage 212-1 (e.g., ground), such that the secondary latch 264 may be continuously enabled. In a number of embodiments, the secondary latch 264 of the compute component 231 can serve as an accumulator. As such, the compute component 231 can operate as and/or may be referred to herein as an accumulator. The configuration of the compute component 231 is not limited to that shown in FIG. 2B, and various other embodiments are feasible within the scope of the present disclosure.

The gates of the pass gates 207-1 and 207-2 can be controlled by a logical operation selection logic signal, Pass. For example, an output of the logical operation selection logic 213 can be coupled to the gates of the pass gates 207-1 and 207-2.

Data units present on the pair of complementary sense lines 205-1 and 205-2 can be loaded into the compute component 231 via the pass gates 207-1 and 207-2. When the pass gates 207-1 and 207-2 are OPEN, data units on the pair of complementary sense lines 205-1 and 205-2 may be passed to the compute component 231. The data unit on the pair of complementary sense lines 205-1 and 205-2 can be the data unit stored at least temporarily in the sense amplifier 206 when the sense amplifier is enabled (e.g., fired). The logical operation selection logic signal, Pass, is activated to OPEN (e.g., turn on) the pass gates 207-1 and 207-2.

The control signals can operate to select a logical operation to implement based on the data unit (“B”) in the sense amplifier 206 and the data unit (“A”) in the compute component 231 (e.g., as used herein, the data unit stored in a primary latch of a sense amplifier is referred to as a “B” data unit, and the data unit stored in a secondary latch of a compute component is referred to as an “A” data unit). In particular, the control signals may be configured to select the logical operation (e.g., function) to implement independent from the data unit present on the pair of complementary sense lines 205-1 and 205-2, although the result of the implemented logical operation can be dependent on the data unit present on the pair of complementary sense lines 205-1 and 205-2.

Although not shown in FIG. 2B, each column of memory cells can be coupled to a column decode line that can be activated to transfer, via a local I/O line, a data unit from a corresponding sense amplifier 206 and/or compute component 231 to a control component external to the array such as an external processing resource (e.g., host processor and/or other functional unit circuitry). The column decode line can be coupled to a column decoder (e.g., column decoder 152 in FIG. 1A). However, as described herein, data need not be transferred via such I/O lines to perform logical operations. For example, circuitry can be operated in conjunction with sense amplifiers 206 and compute components 231 to perform logical and/or random number generation operations without transferring data to a control component external to the array. As used herein, transferring data can include, for example, moving data from a source location to a destination location without necessarily maintaining a copy of the data at the source location.

In operation, a data unit on a pair of complementary sense lines (e.g., 205-1/205-2) can be loaded into a corresponding compute component 231 (e.g., by operating logical operation selection logic as described above). For example, a data unit can be loaded into a compute component 231 via overwriting of the data unit currently stored in the compute component 231 with the data unit stored in the corresponding sense amplifier 206.

The sensing circuitry 250-2 in FIG. 2B can be operated in several modes to perform logical (e.g., PIM) operations, including a first mode in which a result of the logical operation is initially stored in the sense amplifier 206, and a second mode in which a result of the logical operation is initially stored in the compute component 231. For example, if the sense amplifier 206 is equilibrated and the control signals are activated to provide a conduction path (e.g., electrical continuity) between the sense amplifier 206 and the compute component 231, then a data unit stored in the compute component 231 can be transferred from the compute component 231 to the sense amplifier 206. If the sense amplifier 206 is configured to store a first bit (e.g., first data unit) and the control signals are activated to provide a conduction path between the sense amplifier 206 and the compute component 231, then a second bit (e.g., second data unit) that is stored in the compute component 231 before the activation of the control signals can be replaced by the first bit and the sense amplifier 206 retains the first bit. Furthermore, a number of PIM operations can be performed using the first bit and the second bit using the logical operation selection logic and the result of the operation can be stored in the compute component 231.

As described herein, the sense amplifier 206 can, in some embodiments in conjunction with the compute component 231, be operated to perform various logical operations and/or operations involving random number generation (e.g., using data and/or residual voltages from an array as input). In a number of embodiments, the result of a logical operation and/or operation involving random number generation can be stored back to the array without transferring the data via a data line address access (e.g., without firing a column decode signal such that data is transferred to circuitry external to the array and sensing circuitry via local I/O lines). As such, a number of embodiments of the present disclosure can enable performing various PIM operations (e.g., logical operations, shift operations, mathematical operations, data movement operations using shared I/O lines) and/or operations involving random number generation, etc., using less power than various previous approaches. Additionally, because a number of embodiments can reduce or eliminate moving (e.g., copying, transferring) data across I/O lines in order to perform operations (e.g., between memory and a discrete processor, which may be off pitch), a number of embodiments may enable an increased parallel processing capability as compared to previous approaches.

FIG. 3 is a schematic diagram of a memory device in accordance with a number of embodiments of the present disclosure. In the embodiment illustrated in FIG. 3, the memory array 330 is an array, for example a DRAM array, of 1T1C (one transistor one capacitor) memory cells that can each include an access device 302 (e.g., a transistor) and a storage element 303 (e.g., a capacitor). Some embodiments, however, can, for example, include 2T2C memory cells and/or other array configurations. The memory cells of the memory array 330 can be arranged in rows (as shown at 119 and described in connection with FIG. 1B) coupled by access lines 304-X (Row X), 304-Y (Row Y), etc., and columns coupled by pairs of complementary sense lines DIGIT(n−1)/DIGIT(n−1)_, DIGIT(n)/DIGIT(n)_, and DIGIT(n+1)/DIGIT(n+1)_, etc. The individual sense lines corresponding to each pair of complementary data lines can be referred to as sense lines 305-1 (DIGIT(n)) and 305-2 (DIGIT(n)_) respectively. Although only three pairs of complementary sense lines are shown in FIG. 3, embodiments of the present disclosure are not so limited, and an array of memory cells may include additional columns of memory cells and/or sense lines (e.g., 4,096, 8,192, 16,384, etc.).

As shown in FIG. 3, a gate of a particular memory cell transistor 302 can be coupled to its corresponding access line 304-X, 304-Y, etc., a first source/drain region can be coupled to its corresponding data line (e.g., 305-1 (DIGIT(n), 305-2 (DIGIT(n)_)), and a second source/drain region of a particular memory cell transistor can be coupled to its corresponding capacitor 303.

Memory cells can be coupled to different sense lines and/or access lines. For example, a first source/drain region of a transistor 302-1 can be coupled to sense line 305-1, a second source/drain region of transistor 302-1 can be coupled to capacitor 303-1, and a gate of a transistor 302-1 can be coupled to access line 304-Y. A first source/drain region of transistor 302-2 can be coupled to sense line 305-2, a second source/drain region of transistor 302-2 can be coupled to capacitor 303-2, and a gate of a transistor 302-2 can be coupled to access line 304-X. The cell plate, as shown in FIG. 3, can be coupled to each of capacitors 303-1 and 303-2. The cell plate can be a common node to which a reference voltage (e.g., ground) can be applied in various memory array configurations.

As described herein, the transistors 302 and capacitors 303 can contribute to formation of the pairs of complementary memory cells in a single row of the memory array that are coupled to the complementary sense lines (e.g., sense lines 305-1 and 305-2). The number of data values (e.g., voltages) sensed from the memory cells in logical operations and/or random number generation operations may correspond to the number of columns of memory cells and/or pairs of sense lines (e.g., 4,096, 8,192, 16,384, etc.) that intersect a row, for example, of a subarray 125 shown in and described in connection with FIG. 1B. In various embodiments, each subarray may include 256, 512, 1024 rows, among other possible numbers of rows, and each bank section may be divided into 32, 64, or 128 subarrays, among various possibilities.

The memory array 330 illustrated in FIG. 3 is coupled to sensing circuitry 350 in accordance with a number of embodiments of the present disclosure. In some embodiments, the sensing circuitry 350-1 may include a sense amplifier 306 corresponding to respective columns of memory cells (e.g., coupled to respective pairs of complementary data lines 305-1, 305-2) but does not additionally include a compute component (e.g., 231 shown in FIG. 2B). However, embodiments are not so limited. For example, some embodiments of the sensing circuitry 350-2 (not shown) may include a compute component that can perform compute and/or accumulator functionalities. The sensing circuitry 350 can correspond to sensing circuitry 150 shown in FIG. 1A and/or described in connection with the sensing component stripes 124 in FIG. 1B, for example.

The sense amplifier 306 can correspond to sense amplifier 206 described previously with respect to FIGS. 2A-2B. The sense amplifier 306 can be operated to determine a data value stored in (e.g., a logic state) and/or a residual voltage at a selected memory cell, which may be represented by the voltages present on the complementary sense lines 305-1, 305-2.

FIGS. 4A-4B illustrate waveform diagrams showing signals on sense lines corresponding to a number of logical operations and random number generation operations in accordance with a number of embodiments of the present disclosure. In performance of various logical operations (e.g., read, write, and/or Boolean compute operations, among others) using a memory array (e.g., having DRAM memory cells), a sequence of events for accessing the memory cells of a row can occur as illustrated in the waveform 460 shown in FIG. 4A.

For example, before a row of memory cells is accessed (e.g., fired) for performance of the logical operation, the voltage of sense lines 405-1 and 405-2 may be at essentially the same voltage 461 (e.g., VDD/2). To access the row of memory cells, that row can be selected and/or opened 462 (e.g., fired by execution of a fire row command). The firing 462 of the row may introduce a small voltage differential between the sense lines 405-1 and 405-2 that may be sensed (e.g., at complementary memory cells coupled to the sense lines) by a coupled sense amplifier.

As shown in FIG. 4A, a memory cell coupled to sense line 405-1 can be programmed to hold a positive voltage that can be sensed by operating (firing) 465 the sense amplifier and amplified 466 to a full rail voltage (e.g., VDD) that indicates a logical value (e.g., data unit) of 1 in binary, for example. In contrast, in this example, a complementary memory cell coupled to sense line 405-2 can remain in a low voltage state so as to hold the original voltage 461 (e.g., VDD/2), which can be sensed by operating (firing) 463 the coupled sense amplifier and amplified 464 to a full rail voltage (e.g., ground) indicative of voltage not being elevated at the complementary memory cell. The original small voltage differential will determine the data value (e.g., data unit) sensed at the sense amplifier after the sense amplifier is fired.

At the end of a row cycle (e.g., reading the data values stored by some or all of the memory cells of the row), the sense lines 405-1 and 405-2 can have their voltages equilibrated 467-1, 467-2. The sense lines 405-1 and 405-2 can have their voltages equilibrated by both sense lines having their voltages equilibrated to essentially the same voltage 469 (e.g., VDD/2), as described in connection with the equilibrate circuitry 214 shown in and described in connection with FIG. 2A.

FIG. 4B illustrates a magnified waveform 468 corresponding to the equilibrated portion of the waveform shown at the right side of FIG. 4A. Although an equilibration operation may equalize the voltages of both sense lines to essentially the same voltage 469 when viewed and/or analyzed on a large scale, such as shown in FIG. 4A, variations between the sense lines (e.g., differences in composition, thickness, length, conductance, and/or resistance, among other factors) may contribute to the sense lines not being brought to exactly the same voltage. Moreover, the voltages of the sense lines may vary randomly due to electronic noise (e.g., thermal noise) causing the residual voltage at each of the pair of complementary memory cells after equilibration to randomly vary with passage of time. For example, the random variations of the residual voltage in the complementary sense lines may cause the small scale residual voltage differentials 469 that vary with the passage of time 473 shown in FIG. 4B.

As described herein, prior to programming memory cells and/or following the equilibration operation and prior to firing of a row for a next cycle, the voltage differential between the sense lines is not exactly at 0.0 V. Various sources of entropy may contribute to electronic noise in electrical conductors of the sensing circuitry 150 and/or the memory array 130. A major contribution may be due to thermal noise present on the sense lines 405-1 and 405-2 and/or output of the transistors 227-1, 227-2, 229-1, and 229-2 of the sense amplifiers 206. Such thermal noise may be modeled with the following equation:

vds2_=4γkTΔfgds

where is a mean square of voltage variance per hertz of bandwidth between a drain (d) and a source (s), gds is the reciprocal of the resistance between d and s and is measured in siemens, k is Boltzmann's constant in joules per kelvin, T is the absolute temperature in degrees kelvin, Δf is the bandwidth in hertz over which the noise is measured, and γ is a value chosen to fit a noise measurement to improve accuracy of the noise model.

Due to the random nature of the thermal noise entropy, residual voltage differentials will be non-deterministic and, hence, can be used to produce random data units (e.g., of either 0 or 1 in binary) at the sense amplifier. Because the small scale residual voltage differentials 469 between the complementary sense lines may randomly vary in a positive direction or negative direction at any point in time, sensing and amplifying the residual voltage differentials with a sense amplifier can yield a data unit (e.g., 0 or 1 in binary) that randomly varies (e.g., between 0 or 1) at any point in time. Moreover, combining a plurality of data units determined from residual voltage differentials of a plurality of complementary memory cells in a row may yield a vector of random data units with a length that corresponds to a number of pairs of complementary memory cells sensed by the respective sense amplifiers.

In some embodiments, a sense operation may be performed to determine a residual voltage differential on the first sense line and a complimentary second sense line in a range of 15-45 millivolts, whereas a read operation of a memory cell of a row may be performed to determine a voltage differential of a programmed data unit in a range of 50-100 millivolts. For example, as shown in FIG. 4A, the residual voltage differential may be sensed by the sense amplifier in a lower voltage (potential) range than the potential range used by the sense amplifier for sensing a voltage differential of a programmed data unit. A lowest millivolt value in the residual voltage differential range may be greater than a highest millivolt value in a range of inherent offsets for memory cells, sense lines, and/or sense amplifiers of the DRAM array or may be adjusted accordingly by compensate circuitry (e.g., as shown at 271 and described in connection with FIG. 2A).

FIG. 5 illustrates a timing diagram associated with performing a number of logical operations using sensing circuitry in accordance with a number of embodiments of the present disclosure. In an array memory cells, for example, a DRAM array, a sequence of events, including the row cycle and random number generation operations described in connection with FIGS. 4A-4B, can be directed by a series of fine-tuned operations. The series of operations may be sent to the DRAM array at specific times determined by instructions issued by, for example, a state machine and/or a timing component thereof, as described herein.

FIG. 5 illustrates a timing diagram 575 associated with performance of the various logical operations (e.g., read, write, and/or Boolean compute operations, among others) in the row cycle using circuitry in accordance with that described in connection with the left side of FIG. 4A and elsewhere herein. The timing diagram 575 schematically illustrated in FIG. 5 is shown as an example of a sequence of signals in circuitry for the various logical operations. A time scale horizontally demarcated in signaling unit time points (t0, t1, t2, . . . , t13) of arbitrary length is shown by way of example.

At to, a pair of complementary sense lines may be in an equilibration state 567. At t1, the row of memory cells may be selected and/or opened 562 (e.g., fired) to introduce a small voltage differential between the sense lines, as shown at 462 in FIG. 4A. At t2, a sense amplifier may be fired 563, 565 to determine a voltage differential between the sense lines at a position of complementary memory cells in the row. As shown by comparison of the waveforms 460, 468 in FIGS. 4A-4B, firing of the row at 562 would overwhelm the residual voltage of the sense lines 405-1 and 405-2 so as to prevent the residual voltage differential at complementary memory cells from being sensed by a coupled sense amplifier. The residual voltage differential at the complementary memory cells may remain overwhelmed until bringing the row of memory cells back to the equilibration state 567 starting at to.

FIG. 6 illustrates a timing diagram 680 associated with performing a number of random number generation operations using sensing circuitry in accordance with a number of embodiments of the present disclosure. As just described, performance of the various logical operations in the row cycle may render voltages and differentials thereof resulting from electronic (e.g., thermal) noise negligible when the row is fired.

As such, the present disclosure describes issuing by the state machine and/or the timing component thereof a sequence of instructions to the row that does not include instructions for performance of the row fire operation. This can be accomplished by modifying the sequence of instructions sent to the DRAM array.

Hence, at to a pair of complementary sense lines may be in an equilibration state 667. In contrast to the row cycle described in connection with FIG. 5, at t1 and throughout the row cycle shown in FIG. 6, the row of memory cells may remain unselected and/or unopened 662 (e.g., unfired). At t2, a sense amplifier may be fired 663, 665 to determine a voltage differential between the sense lines at a position of complementary memory cells in the row. In this way, the electronic (thermal) noise may enable the residual voltages of the sense lines and the differential thereof to be sensed by the fired sense amplifier between a first sense line and a complimentary second sense line in the array, for example, following a previous equilibration operation. Executing this modified sequence of instructions may enable generation of a random data value (e.g., 0 or 1 in binary) at t2, as shown in FIG. 6. However, in various embodiments, a random data value may be generated at any of the time points t0, t1, t2, . . . , t10 in the modified row cycle at which the sense amplifier is fired 663, 665 following placing the pair of complementary sense lines in an equilibration state 667 at t11, t12, t13, for example.

Since the modified sequence of instructions may be written such that the modified series of operations for the row cycle may apply to sense amplifiers corresponding to an entire row of memory cells, the same series of operations may be used to produce a number of random data units corresponding to a length of the entire row. Since the length of an element within a vector of random data units may depend only on how that vector is addressed, a hardware, firmware, and/or software application may use this set of random data units as a vector containing up to W/L elements of random data units, where W is the width of the row in the array in data units and L is a desired length of the element in data units.

In some memory array configurations, physical properties (e.g., inherent offsets for sense lines, memory cells, and/or sense amplifiers of a DRAM array) may be such that a residual voltage differential following an equilibration operation may be difficult to determine in order to produce the random data unit upon firing of the sense amplifier. The compensate circuitry 271 shown in and described in connection with FIG. 2A is designed to at least partially overcome such difficulties.

Embodiments described herein provide a method of operating an apparatus that may be in the form of a computing system 100 including a memory device 120 (e.g., as shown in and described in connection with FIGS. 1A-3) for random number generation. As described herein, the method can include operating the memory device for random number generation by operating a sense amplifier (e.g., sense amplifier 206 in FIGS. 2A-2B and/or 306 in FIG. 3) of the memory device to perform sensing a first voltage on a first sense line (e.g., sense line 205-1 shown in FIGS. 2A-2B and at corresponding reference numbers on FIGS. 3 and 4A) coupled to the sense amplifier and sensing a second voltage on a complementary second sense line (e.g., sense line 205-2 shown in FIGS. 2A-2B and at corresponding reference numbers on FIGS. 3 and 4A) coupled to the sense amplifier. The method can include generating a random number by detecting a voltage differential between the first sense line and the complementary second sense line.

In some embodiments, an equilibration operation can be performed such that the first voltage on the first sense line and the second voltage on the complementary second sense line are both in an equilibration state. As such, for example, a sense line 305-1 coupled to a memory cell (e.g., the memory cell shown at 302-1, 303-1 in FIG. 3) and a sense line 305-2 coupled to a paired memory cell (e.g., the memory cell shown at 302-2, 303-2 in FIG. 3) can be placed in the equilibrated state. The equilibration operation can be performed, for example, using the equilibrate circuitry 214 to equilibrate sense line 205-1 and sense line 205-2 shown in and described in connection with FIGS. 2A-2B. Performance of the equilibration operation can bring the voltages of the sense lines and/or memory cells to essentially the same residual voltage (e.g., close to VDD/2 as shown at 469 and described in connection with FIG. 4A).

The method can include sensing a first residual voltage on the first sense line and a second residual voltage on the complementary second sense line to detect the voltage differential to generate the random number. The first residual voltage and the second residual voltage may, as described herein, result from electronic noise (e.g., thermal noise) in an electrical conductor (e.g., sense lines 205-1, 205-2, a sense amplifier 206, and/or a compute component 231 shown in and described in connection with FIGS. 2A-2B). For example, a differential may be generated in the first residual voltage and the second residual voltage by residual voltages being unequal in the first sense line (e.g., sense line 305-1) and the second sense line (e.g., sense line 305-2). Performance of the equilibration operation can result in the residual voltages being unequal in the first sense and the second sense line (e.g., as shown at 469 and described in connection with FIG. 4B). The unequal residual voltages can be due to, or at least contributed to, thermal noise that enables random agitation of charge carriers in the first sense line and the second sense line.

As described herein, a random data unit can be generated from the detection of the voltage differential between the first sense line and the complementary second sense line and a random number can be generated utilizing the random data unit. As described herein, a residual voltage differential can be determined on a first sense line and a complementary second sense line using a sense amplifier selectably coupled to the respective pair of complementary sense lines. The random data unit can, in some embodiments, be generated by performing an equilibration operation on a pair of complementary sense lines of a DRAM array. The random data unit may be determined based on the determined residual voltage differential. In some embodiments, the random data unit may be stored in the sense amplifier that determined residual voltage differential. In some embodiments, the random data unit may be moved for storage in a pair of complementary memory cells of a row of the DRAM array. The random number may be generated, in some embodiments, by a processor (e.g., random number component 172 shown in and described in connection with FIGS. 1A-1B) by accessing the random data unit from the sense amplifier and/or the memory cell in which the random data unit is stored.

As shown at 662 and described in connection with FIG. 6, a random number generation operation may leave a row unselected and/or unopened (e.g., unfired) for a programming operation (e.g., a logical operation as described in connection with FIG. 5) prior to using sense amplifier to perform the sense operation to determine the residual voltage differential for random number generation. Leaving the row unfired for the random number generation operation may include a state machine and/or a timing component thereof issuing a sequence of instructions (e.g., microcode) that differs from instructions issued to direct performance of the logical operation.

Performing the random number generation operation may include determining a residual voltage differential on each of respective pairs of complementary sense lines (e.g., as shown at 305-1 and 305-2 in FIG. 3). For example, as shown in and described in connection with FIG. 3, a single sense amplifier 306 can be selectably coupled to each respective pair of complementary memory cells (e.g., via the sense lines 305-1, 305-2). By performing the sense operation on each of respective pairs of complementary sense lines, a vector of data units may be generated with a length that corresponds to a number of pairs of complementary sense lines of the DRAM array (e.g., the number of pairs of complementary sense lines intersecting a row of the DRAM array).

The vector of data units that corresponds to a number of pairs of complementary sense lines may be divided, for example, by a processor (e.g., random number component 172) into a plurality of vector elements (e.g., W/L elements of random data units). Hence, a plurality of random numbers may be generated from the plurality of vector elements, which may be generated from a single vector of data units. Each of the random numbers may include a selected plurality of data units in the vector elements. For example, all of the random numbers may have the same number of data units (digits) by selecting four (e.g., 2761, 9842, 1068, etc.) as the plurality of data units in the vector elements. In some embodiments, the number of data units (digits) can vary between the vector elements and, thus, the random numbers.

As shown at 469 and 473 and described in connection with FIG. 4B, a first residual voltage differential may be determined at a first time by a first sense operation performed on the first sense line and the complementary second sense line to yield a first random data unit. A second residual voltage differential may be determined at a second time by a second sense operation performed on the first sense line and the complementary second sense line to yield a second random data unit. The first random data unit may be different from the second random data unit due to electronic noise causing the residual voltage on the first sense line and the complementary second sense line to randomly vary with passage of time.

Various apparatus configurations may be used for performance of random number generation operations, as described herein. At least one embodiment of such an apparatus may include a DRAM memory cell array 130 with sensing circuitry 150 coupled to the array (e.g., as shown and described in connection with FIGS. 1A-1B). The sensing circuitry 150 can include a sense amplifier (e.g., as shown at 206 and described in connection with FIGS. 2A-2B and at corresponding reference numbers in FIG. 3) coupled to a respective sense line (e.g., as shown at 205-1 and 205-2 and described in connection with FIGS. 2A-2B and at corresponding reference numbers in FIG. 3). The sensing circuitry 150 can be configured to perform random number generation operations and DRAM logical operations (e.g., read and write operations, and Boolean operations, among others). The sensing circuitry 150 may further include equilibrate circuitry (e.g., as shown at 214 and described in connection with FIGS. 2A-2B) configured to equilibrate complementary programmed memory cells selectably coupled to the complementary sense lines in the array, which also become equilibrated.

A random number component 172 (e.g., a processing resource associated with and/or connected to the controller 140 described in connection with FIGS. 1A-1B) can be coupled to the array and sensing circuitry. The random number component 172 may be configured to generate a random number from a residual voltage differential sensed by the sense amplifier on complementary sense lines, as described herein. The random number component 172 may generate the random number from the residual voltage differential of the equilibrated complementary sense lines. The residual voltage differential may at least partially be enabled by random electronic noise in the respective sense lines, with the random number generation being based on the residual voltage differential.

In some embodiments, the random number component 172 can include logic, for example, hardware (e.g., in the form of ASIC) and/or firmware to implement one or more particular functions. As such, the random number component and/or the logic may be configured to receive a request for a random number generation operation and to execute coded instructions (e.g., microcode to initiate the performance of the random number generation operation). The coded instructions may be included and/or associated with a state machine to control the performance of the random number generation operations and/or the DRAM operation by the sensing circuitry. For example, the controller 140 of a memory device 120 may include control circuitry that, in some embodiments, can include control logic and a state machine (e.g., an atomic state machine). The state machine may include and/or be associated with a timing component. The logic may be configured to, for example, receive requests for performance of random number generation operations and DRAM logical operations and execute coded machine instructions to initiate performance of different sequences and/or timing of operations dependent upon whether the request is for performance of a random number generation operation or a DRAM logical operation, as described with regard to FIGS. 5 and 6. The coded machine instructions can be, for example, microcode instructions.

In some embodiments, the sensing circuitry may further include a compute component (e.g., as shown at 231 and described in connection with FIG. 2B) coupled to a respective sense amplifier 206. The compute component may be configured to utilize the random number generated from the residual voltage differential sensed by the sense amplifier in performance of a logical operation. Such a logical operation may include the DRAM logical operations described herein. Alternatively or in addition, such a logical operation may include the previously described examples of applications that use random number samples, among other possibilities. In various embodiments, the sensing circuitry 250, the compensate component 271, and/or the random number component 172 may be formed on pitch with the memory cells in the array 130.

A plurality of complementary memory cells can be included in a row of a memory cell array (e.g., as shown and described in connection with FIG. 3). The sensing circuitry (e.g., 250, 350) may be selectably coupled to the plurality of complementary memory cells via a plurality of columns (e.g., as shown at 122 and described in connection with FIG. 1B). A column can correspond to a pair of complementary of sense lines coupled to corresponding complementary memory cells (e.g., as shown in FIG. 3). The sensing circuitry can include a respective plurality of sense amplifiers (e.g., 215) and equilibrate circuitry (e.g., 214) coupled to a respective plurality of pairs of complementary of sense lines.

A controller 140 can be selectably coupled to the row of the plurality of memory cells and the sensing circuitry and can be configured to issue a command for generation of random numbers based on the residual voltage differentials sensed by the plurality of sense amplifiers on the plurality of complementary sense lines. In some embodiments, a random number component 172 may be associated with and/or connected to the controller 140. The random number component 172 may be operatively coupled to the sensing circuitry and configured to generate a random number from the residual voltage differential sensed by the sense amplifier at the complementary memory cells. The random number component 172 may be further configured to generate a vector of data units with a length that corresponds to a number of the plurality of complementary memory cells in the row. For example, the random number component 172 may be configured to generate a vector of data units with a length that corresponds to a number of the random the random data units generated from the residual voltage differentials sensed by a respective plurality of sense amplifiers (e.g., where the residual voltage differential sensed by each sense amplifier may be used to generate a single data unit for the vector).

The controller 140 may be further configured to issue a command to generate a plurality of vector elements by division of the vector of data units. For example, the number of the data units in the vector may correspond to a number of the plurality of complementary sense lines that intersect the row and a number of the plurality of vector elements may correspond to the number of the data units in the vector divided by a selected length in data units of each vector element. As described in connection with FIG. 6, the controller 140 (e.g., or a state machine and/or a timing component associated with and/or connected to the controller) may be further configured to issue a command to prevent selection of the row (e.g., as shown at 662 and described in connection with FIG. 6) for a programming operation prior to selectably coupling the sensing circuitry to perform a random number generation operation.

While example embodiments including various combinations and configurations of sensing circuitry, sense amplifiers, compute components, equilibrate circuitry, random number components, control circuitry (e.g., including control logic, a sequencer, a timing component, etc.), and/or compensate circuitry, etc., have been illustrated and described herein, embodiments of the present disclosure are not limited to those combinations explicitly recited herein. Other combinations and configurations of the sensing circuitry, sense amplifiers, compute components, equilibrate circuitry, random number components, control circuitry (e.g., including control logic, a sequencer, a timing component, etc.), and/or compensate circuitry, etc., disclosed herein are expressly included within the scope of this disclosure.

Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combination of the above embodiments, and other embodiments not specifically described herein will be apparent to those of skill in the art upon reviewing the above description. The scope of the one or more embodiments of the present disclosure includes other applications in which the above structures and processes are used. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.

In the foregoing Detailed Description, some features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

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Citation

Patents Cited in This Cited by
Title Current Assignee Application Date Publication Date
반도체 메모리 장치 삼성전자주식회사 15 June 2009 23 December 2010
감소 칩 영역을 가진 반도체 메모리 소자 닛본 덴끼 가부시끼가이샤 29 November 1996 02 August 1999
System for implementing a graphic address remapping table as a virtual register file in system memory ROUND ROCK RESEARCH, LLC 27 February 2001 05 July 2001
Semiconductor memory and method for controlling the same SOCIONEXT INC. 17 January 2001 19 July 2001
반도체 메모리 장치 및 이를 위한 테스트 회로 에스케이하이닉스 주식회사 04 November 2011 14 May 2013
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US10152304 Apparatuses random 1 US10152304 Apparatuses random 2 US10152304 Apparatuses random 3