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Patent Analysis of

Error code calculation on sensing circuitry

Updated Time 12 June 2019

Patent Registration Data

Publication Number

US10152374

Application Number

US15/959978

Application Date

23 April 2018

Publication Date

11 December 2018

Current Assignee

MICRON TECHNOLOGY, INC.

Original Assignee (Applicant)

MICRON TECHNOLOGY, INC.

International Classification

G06F11/10,G06F12/00,G11C7/10,G11C7/06,G11C7/12

Cooperative Classification

G06F11/1068,G06F3/0619,G06F3/0679,G06F11/1048,G06F12/00

Inventor

LEA, PERRY V.,FINKBEINER, TIMOTHY P.

Patent Images

This patent contains figures and images illustrating the invention and its embodiment.

US10152374 Error code calculation sensing 1 US10152374 Error code calculation sensing 2 US10152374 Error code calculation sensing 3
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Abstract

Examples of the present disclosure provide apparatuses and methods for error code calculation. The apparatus can include an array of memory cells that are coupled to sense lines. The apparatus can include a controller configured to control a sensing circuitry, that is coupled to the sense lines, to perform a number of operations without transferring data via an input/output (I/O) lines. The sensing circuitry can be controlled to calculate an error code for data stored in the array of memory cells and compare the error code with an initial error code for the data to determine whether the data has been modified.

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Claims

1. A system comprising:

a host;a memory device coupled to the host, the memory device including:

an array of memory cells that are coupled to sense lines; anda controller configured to control a sensing circuitry, that is coupled to the sense lines, to perform a number of operations without transferring data via an input/output (I/O) line to:

calculate an error code for the data stored in the array of memory cells; and compare the error code with an initial error code for the data to determine whether the data has been modified.

2. The system of claim 1, wherein the host is external to the memory device.

3. The system of claim 1, wherein the host comprises a processor.

4. The system of claim 1, wherein the host comprises one of the group of hosts including a laptop computer, a desktop computer, a digital camera, a smart phone, and a memory card reader.

5. The system of claim 1, wherein the controller is further configured to perform AND operations, OR operations, SHIFT operations, and INVERT operations without transferring the data via an input/output (I/O) line.

6. The system of claim 1, wherein the sensing circuitry comprises a sense amplifier and a compute component for each sensing component coupled to one of the sense lines.

7. The system of claim 6, wherein the sense amplifier further comprises a primary latch and the compute component comprises a secondary latch.

8. The system of claim 1, wherein the data comprises at least one of data and code storage.

9. The system of claim 8, wherein the code storage comprises an operating system.

10. The system of claim 1 wherein the controller is further configured to provide instructions to the sensing circuitry that enable the sensing circuitry to perform the number of operations.

11. The system of claim 10, wherein the controller is configured to inform the host that the data has been modified.

12. The system of claim 10, wherein the controller is configured to repetitively provide the instructions-to the sensing circuitry at a given interval of time.

13. A system comprising:

a host;a memory device coupled to the host, the memory device including:

an array of memory cells that are coupled to sense lines and that store data;a controller configured to:

refresh the data stored in the array of memory cells; and control sensing circuitry;the sensing circuitry coupled to the sense lines and configured to:

store the data in a sense amplifier as part of the refresh; calculate a first error code for the data; and compare the first error code with a second error code for the data to determine whether the data has been modified.

14. The system of claim 13, wherein the host comprises a processor external to the memory device.

15. The system of claim 13, wherein the refresh includes the calculation of the first error code and the comparison of the first error code with the second error code.

16. The system of claim 13, wherein the controller is configured to use the data stored in the sense amplifier for refreshing the data; and

wherein the sensing circuitry is configured to use the data stored in the sense amplifier for comparing the first error code with the second error code.

17. The system of claim 13, wherein the controller is configured to determine whether the data stored in the sense amplifier initiated in memory cells that have a memory address that falls within a memory address range.

18. The system of claim 17, wherein the sensing circuitry is configured to calculate the first error code for the data and compare the first error code with a second error code based on a determination that the data stored in the sense amplifier initiated in memory cells that have the memory address that falls within the memory address range.

19. The system of claim 17 wherein the host is configured to provide the memory address range.

20. The system of claim 13, wherein the sensing circuitry is configured to compare the first error code with the second error code at each refresh of the data.

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Claim Tree

  • 1
    1. A system comprising:
    • a host
    • a memory device coupled to the host, the memory device including: an array of memory cells that are coupled to sense lines
    • anda controller configured to control a sensing circuitry, that is coupled to the sense lines, to perform a number of operations without transferring data via an input/output (I/O) line to: calculate an error code for the data stored in the array of memory cells
    • and compare the error code with an initial error code for the data to determine whether the data has been modified.
    • 2. The system of claim 1, wherein
      • the host is external to the memory device.
    • 3. The system of claim 1, wherein
      • the host comprises
    • 4. The system of claim 1, wherein
      • the host comprises
    • 5. The system of claim 1, wherein
      • the controller is further configured to perform AND operations, OR operations, SHIFT operations, and INVERT operations without transferring the data via an input/output (I/O) line.
    • 6. The system of claim 1, wherein
      • the sensing circuitry comprises
    • 8. The system of claim 1, wherein
      • the data comprises
    • 10. The system of claim 1 wherein
      • the controller is further configured to provide instructions to the sensing circuitry that enable the sensing circuitry to perform the number of operations.
  • 13
    13. A system comprising:
    • a host
    • a memory device coupled to the host, the memory device including: an array of memory cells that are coupled to sense lines and that store data
    • a controller configured to: refresh the data stored in the array of memory cells
    • and control sensing circuitry
    • the sensing circuitry coupled to the sense lines and configured to: store the data in a sense amplifier as part of the refresh
    • calculate a first error code for the data
    • and compare the first error code with a second error code for the data to determine whether the data has been modified.
    • 14. The system of claim 13, wherein
      • the host comprises
    • 15. The system of claim 13, wherein
      • the refresh includes the calculation of the first error code and the comparison of the first error code with the second error code.
    • 16. The system of claim 13, wherein
      • the controller is configured to use the data stored in the sense amplifier for refreshing the data; and wherein
    • 17. The system of claim 13, wherein
      • the controller is configured to determine whether the data stored in the sense amplifier initiated in memory cells that have a memory address that falls within a memory address range.
    • 20. The system of claim 13, wherein
      • the sensing circuitry is configured to compare the first error code with the second error code at each refresh of the data.
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Description

TECHNICAL FIELD

The present disclosure relates generally to semiconductor memory apparatuses and methods, and more particularly, to apparatuses and methods related to calculating error codes on sensing circuitry.

BACKGROUND

Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic systems. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAIVI), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), among others.

Electronic systems often include a number of processing resources (e.g., one or more processors), which may retrieve and execute instructions and store the results of the executed instructions to a suitable location. A processor can comprise a number of functional units (e.g., herein referred to as functional unit circuitry such as arithmetic logic unit (ALU) circuitry, floating point unit (FPU) circuitry, and/or a combinatorial logic block, for example, which can execute instructions to perform logical operations such as AND, OR, NOT, NAND, NOR, and XOR logical operations on data (e.g., one or more operands).

A number of components in an electronic system may be involved in providing instructions to the functional unit circuitry for execution. The instructions may be generated, for instance, by a processing resource such as a controller and/or host processor. Data (e.g., the operands on which the instructions will be executed to perform the logical operations) may be stored in a memory array that is accessible by the functional unit circuitry. The instructions and/or data may be retrieved from the memory array and sequenced and/or buffered before the functional unit circuitry begins to execute instructions on the data. Furthermore, as different types of operations may be executed in one or multiple clock cycles through the functional unit circuitry, intermediate results of the operations and/or data may also be sequenced and/or buffered.

In many instances, the processing resources (e.g., processor and/or associated functional unit circuitry) may be external to the memory array, and data can be accessed (e.g., via a bus between the processing resources and the memory array) to execute instructions. Data can be moved from the memory array to registers external to the memory array via a bus.

The processing resources may be used for security purposes. That is, the processing resource may be used to determine whether a device is has been the target of a security breach.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a block diagram of an apparatus in the form of a computing system including a memory device in accordance with a number of embodiments of the present disclosure.

FIG. 1B is a block diagram of an apparatus in the form of a computing system including a memory device in accordance with a number of embodiments of the present disclosure.

FIG. 2 is a block diagram of a bank of a memory device in accordance with a number of embodiments of the present disclosure.

FIG. 3 is a schematic diagram illustrating sensing circuitry to a memory device in accordance with a number of embodiments of the present disclosure.

FIG. 4 is a logic table illustrating selectable logic operation results implemented by a sensing circuitry shown in FIG. 3 in accordance with a number of embodiments of the present disclosure.

FIGS. 5-8 illustrate a number of embodiments for a high speed interface between a memory device and a host via a channel controller in accordance with the present disclosure.

DETAILED DESCRIPTION

The present disclosure includes apparatuses and methods related to calculating error codes on sensing circuitry. In a number of embodiments, an apparatus comprises an array of memory cells that are coupled to sense lines and that store data. The apparatus also comprises sensing circuitry coupled to the sense lines and configured to execute instructions to calculate an error code for the data and compare the error code with an initial error code for the data to determine whether the data has been modified.

As used herein, an error code is a code that is used to determine whether data stored in the array has been modified in a given time period. Determining whether data stored in an array has been modified can include comparing two different error codes that correspond to what should be the same data stored in the array. For example, a first error code can be calculated at a first time and a second error code can be calculated at a second time. Comparing the first error code with the second error code can include determining whether the data has been modified during the time period beginning at the first time and ending at the second time. The error code can be calculated from the data as will be described below.

The first error code and/or the second error code can be calculated via a plurality of processing resources that are incorporated into the sensing circuitry of a memory array. For example, some memory arrays can be coupled to sensing circuitry comprising a plurality of sensing components each corresponding to one of a respective plurality of sense lines of the array and serving as one of a respective plurality of processing resources (e.g., a plurality of 1-bit processors). In various instances, the plurality of 1-bit processors can operate in parallel on data stored in a memory array. The data can be stored such that each of the data units (e.g., bits) of a particular data element (e.g., word) are stored at successive addresses in the memory space corresponding to a particular processing resource. In this manner, in an array comprising 16K columns, 16K vertically stored data elements could be processed in parallel by the corresponding 16K 1-bit processors.

Embodiments of the present disclosure can provide benefits such as creating an error code and determining whether data has changed in a more efficient manner and/or using less circuitry as compared to previous approaches, among other benefits. In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how one or more embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure. As used herein, the designators “N, ”“X, ”“Y, ” etc., particularly with respect to reference numerals in the drawings, indicates that a number of the particular feature so designated can be included. As used herein, “a number of ” a particular thing can refer to one or more of such things (e.g., a number of memory arrays can refer to one or more memory arrays).

The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, 110 may reference element “10” in FIG. 1A, and a similar element may be referenced as 110 in FIG. 1B. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, as will be appreciated, the proportion and the relative scale of the elements provided in the figures are intended to illustrate certain embodiments of the present invention, and should not be taken in a limiting sense

FIG. 1A is a block diagram of an apparatus in the form of a computing system 100 including a memory device 120 in accordance with a number of embodiments of the present disclosure. As used herein, a memory device 120, memory controller 140, memory array 130, sensing circuitry 150, and logic circuitry 170 might also be separately considered an “apparatus.”

System 100 includes a host 110 coupled (e.g., connected) to memory device 120, which includes a memory array 130. Host 110 can be a host system such as a personal laptop computer, a desktop computer, a digital camera, a smart phone, or a memory card reader, among various other types of hosts. Host 110 can include a system motherboard and/or backplane and can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry). The system 100 can include separate integrated circuits or both the host 110 and the memory device 120 can be on the same integrated circuit. The system 100 can be, for instance, a server system and/or a high performance computing (HPC) system and/or a portion thereof. Although the example shown in FIGS. 1A and 1B illustrates a system having a Von Neumann architecture, embodiments of the present disclosure can be implemented in non-Von Neumann architectures, which may not include one or more components (e.g., CPU, ALU, etc.) often associated with a Von Neumann architecture.

For clarity, the system 100 has been simplified to focus on features with particular relevance to the present disclosure. The memory array 130 can be a DRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash array, and/or NOR flash array, for instance. The array 130 can comprise memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines, which may be referred to herein as data lines or digit lines. Although a single array 130 is shown in FIG. 1, embodiments are not so limited. For instance, memory device 120 may include a number of arrays 130 (e.g., a number of banks of DRAM cells, NAND flash cells, etc.).

The memory device 120 includes address circuitry 142 to latch address signals provided over a bus 156 (e.g., an I/O bus) through I/O circuitry 144. Status and/or exception information can be provided from the controller 140 on the memory device 120 to a channel controller, through a high speed interface (HSI) including an out-of-band (OOB) bus, which in turn can be provided from the channel controller to the host 110. Controller 140 can include a cache 171 for storing data. The cache 171 can include a number of memory cells (e.g., SRAM Cell Array) and decode circuitry (e.g., muxes, gates, and row decoders). Address signals are received through address circuitry 142 and decoded by a row decoder 146 and a column decoder 152 to access the memory array 130. The address signals can also be provided to controller 140. Data can be read from memory array 130 by sensing voltage and/or current changes on the data lines using sensing circuitry 150. The sensing circuitry 150 can read and latch a page (e.g., row) of data from the memory array 130. The I/O circuitry 144 can be used for bi-directional data communication with host 110 over the data bus 156. The write circuitry 148 is used to write data to the memory array 130.

Controller 140, e.g., bank control logic and/or sequencer, decodes signals provided by control bus 154 from the host 110. These signals can include chip enable signals, write enable signals, and address latch signals that are used to control operations performed on the memory array 130, including data read, data write, and data erase operations. In various embodiments, the controller 140 is responsible for executing instructions from the host 110 and sequencing access to the array 130. The memory controller 140 can be a state machine, a sequencer, or some other type of controller. The controller 140 can control shifting data (e.g., right or left) in an array (e.g., memory array 130), as well as a number of instructions that are provided to the sensing circuitry 150 and the logic 170 that enable the sensing circuitry 150 and the logic 170 to calculate error codes by performing logical operations.

Examples of the sensing circuitry 150 can comprise a number of sense amplifiers and a number of corresponding compute components, which may serve as, and be referred to herein as, accumulators and can be used to perform logical operations (e.g., on data associated with complementary data lines).

In a number of embodiments, the sensing circuitry 150 can be used to perform logical operations using data stored in array 130 as inputs and store the results of the logical operations back to the array 130 without transferring data via a sense line address access (e.g., without firing a column decode signal). As such, various compute functions can be performed using, and within, sensing circuitry 150 rather than (or in association with) being performed by processing resources external to the sensing circuitry (e.g., by a processor associated with host 110 and/or other processing circuitry, such as ALU circuitry, located on device 120 (e.g., on controller 140 or elsewhere)).

In various previous approaches, data associated with an operand, for instance, would be read from memory via sensing circuitry and provided to external ALU circuitry via I/O lines (e.g., via local I/O lines and/or global I/O lines). The external ALU circuitry could include a number of registers and would perform compute functions using the operands, and the result would be transferred back to the array via the I/O lines. In contrast, in a number of embodiments of the present disclosure, sensing circuitry 150 is configured to perform logical operations on data stored in memory array 130 and store the result back to the memory array 130 without enabling an I/O line (e.g., a local I/O line) coupled to the sensing circuitry 150. The sensing circuitry 150 can be formed on pitch with the memory cells of the array. Additional logic circuitry 170 can be coupled to the sensing circuitry 150 and can be used to store, e.g., cache and/or buffer, results of operations described herein.

As such, in a number of embodiments, circuitry external to array 130 and sensing circuitry 150 is not needed to perform compute functions as the sensing circuitry 150 can perform the appropriate logical operations to perform such compute functions without the use of an external processing resource. Therefore, the sensing circuitry 150 may be used to compliment and/or to replace, at least to some extent, such an external processing resource (or at least the bandwidth consumption of such an external processing resource).

However, in a number of embodiments, the sensing circuitry 150 may be used to perform logical operations (e.g., to execute instructions) in addition to logical operations performed by an external processing resource (e.g., host 110). For instance, host 110 and/or sensing circuitry 150 may be limited to performing only certain logical operations and/or a certain number of logical operations.

Enabling an I/O line can include enabling (e.g., turning on) a transistor having a gate coupled to a decode signal (e.g., a column decode signal) and a source/drain coupled to the I/O line. However, embodiments are not limited to not enabling an I/O line. For instance, in a number of embodiments, the sensing circuitry (e.g., 150) can be used to perform logical operations without enabling column decode lines of the array; however, the local I/O line(s) may be enabled in order to transfer a result to a suitable location other than back to the array 130 (e.g., to an external register).

In a number of examples, the memory array 130 can store data that can be monitored to determine whether the data has been modified. Data stored in the memory array 130 can include sensitive data. As used herein, sensitive data describes data that is placed into memory and is fixed (e.g., is not swapped out). Fixed data includes data that is not modified for a given time period. Sensitive data can include passwords, documents, and files, among other types of sensitive data. Sensitive data can also include code storage. As used herein, code storage includes static machine executable instructions that can be executed by either a host 110 and/or by the sensing circuitry 150, among other processing resources. Static machine executable instructions references machine executable instructions that do not change. Code storage can include, for example, an operating system or portions of the operating system (OS). Code storage can also include. For example, sensitive data can include network services, a task scheduler, memory management unit, and/or a core, among other portions of the OS.

The host 110 can store instructions in the memory array 130 to provide the ability to determine whether data in the memory array 130 has been modified. The host 110 can also initiate the execution of the stored instructions by instructing the controller 140 to initiate the execution of the stored instructions in the sensing circuitry 150. The host 110 can provide an address range that corresponds to memory cells in the array. The stored instructions can be executed to monitor the memory cells identified by the provided address range to determine whether data in the memory array 140 has been modified. The host 110 can provide the address range to controller 140.

For example, the host 110 can store an OS in memory as part of a boot sequence. The host 110 can provide the address range where the boot sequence and/or the OS system are stored in memory to the controller 140. The host 110 can also store data in memory and provide an address range where the data is stored in the memory to the controller 140.

The host 110 can also indicate to the controller 140 a number of responses that the controller 140 and/or the sensing circuitry 150 can implement in response to a determination that the monitored data has been modified. In a number of examples, the host 110 can implement a response to a determination that the monitored data has been modified. For example, the host 110 can halt the system 100. Halting the system 100 can include ceasing the execution of instructions on the host 110, the controller 140, and/or the sensing circuitry 150.

The controller 140 can receive the memory address range and can retrieve instructions (PIM instructions) from memory array 130 to determine whether data stored in memory cells corresponding to the memory address range has been modified. The controller 140 can provide the PIM instructions to the sensing circuitry 150 to determine whether the stored data has been modified.

The controller 140 can provide the PIM instructions once to the sensing circuitry 150 and/or continuously. For example, the controller 140 can provide the PIM instructions to the sensing circuitry 150 repeatedly at particular intervals of time. For example, a time interval can be a second, among other time intervals, such that the controller 140 can provide the PIM instructions to the sensing circuitry 150 every second.

If it is determined that the sensitive data has been modified, then the controller 140 respond to the determination. For example, the controller 140 can notify the host 110, halt further execution of PIM instructions, launch the execution of a different number of PIM instructions, and/or continue to monitor the sensitive data. The controller 140 can communicate with host 110 via a data collection system. The data collections system can include a high speed interface such as control bus 154, OOB 157, and/or data bus 156. The data collection system can also include memory cells that have an address that does not fall within the memory address range that is monitored. For example, the controller 140 can store a notice that the sensitive data has been modified in memory cells of memory array 130. The host 110 can monitor the memory cells of memory array 130 to determine whether the data has been modified.

The sensing circuitry 150 can receive and execute the instructions provided by the controller 140. The sensing circuitry 150 can calculate an error code to determine whether sensitive data has been modified. An error code can include be a check value created via cyclic redundancy check (CRC) and/or a message digest created via a hash function, among other error codes. The error code can represent the sensitive data such that a change to the sensitive data can result in a change to the error code.

The error code can be created from the sensitive data. That is, the sensitive data can be manipulated to create the error code. In a number of examples, a different error code can be created for different portions of the sensitive data. For example, a first error code can be created for a first portion of the sensitive data and a second error code can be created for a second portion of the sensitive data. The portion of the sensitive data can correlate with the structure of the memory array 130. For example, a portion of the sensitive data can include data stored in memory cells coupled to an access line. Such that, for example, data stored in memory cells coupled to a first access line can be used to create a first error code and data stored in memory cells coupled to a second access line can be used to create a second error code. In a number of examples, a plurality of error codes that are created from sensitive data at a particular time can be combined to create one error code for the sensitive data. For example, the first error code that represents a first portion of the sensitive data and a second error code that represents a second portion of the sensitive data can be can be combined to create an error code that represents the sensitive data.

The error code can be created at a number of different intervals. For example, a first error code of the sensitive data can be created in response to the storing of the sensitive data in the memory array 130 at a first time (e.g., t1). A second error code of the sensitive data can be created in response to a request from the host 110 at a second time (e.g., t2). The created error codes can be stored in the memory array 130 and/or the cache 171, among other possible storage location for the created error codes. The created error codes can be retrieved from the memory array 130 to compare the error codes to recently created error codes. For example, the first error code can be created and stored in the memory array 130. The second error code can be created and stored in the sensing circuitry 150 (e.g., the compute component 231 in FIG. 2). The first error code can be retrieved from the memory array 130 and stored in the sensing circuitry 150 (e.g., the sense amplifier 206 in FIG. 2). The first error code and the second error code can be compared on the sensing circuitry 150.

The error codes can be compared to determine whether the first error code and the second error code are a same error code. That is, the error codes can be compared to determine whether the error codes have changed in the time interval in which the first error code was created and the second error code was created. A change in the error codes can indicate that the sensitive data has been modified. A change to the sensitive data can be an unwanted change created by, for example, malware. A change to the error code can also indicate a malfunction of the system. The system can malfunction in response to, for example, bugs in the system.

The sensing circuitry 150 can calculate an error code and/or compare the error codes by executing a number of AND operations, OR operations, SHIFT operation, and/or INVERT operation, among other logical operations, without transferring data via an input/output (I/O) line. Implementing AND operations, OR operations, SHIFT operations, and/or INVERT operations using the sensing circuitry 150 is described in FIGS. 3 and 4.

The logical operations executed to calculate an error code and/or compare the error codes can be executed on the sensing circuitry 150 without being interrupted. That is, a first number of logical operations can be executed to calculate an error code and/or compare error codes without stopping the execution of first number of logical operations to execute a second number of logical operations to perform different actions not related to the calculation of the error code and/or the comparison of error codes.

The execution of a first number of logical operations to calculate an error code and/or compare error codes can be distributed between an execution of a second number of logical operations. For example, a first group of logical operations from the first number of logical operations can be executed before a first group of logical operations from the second number of logical operations is executed. A second group of logical operations from the first number of logical operation can be executed after the first group of logical operation from the second number of logical operations is executed.

In a number of examples, determining whether data has been modified can include calculating error codes and/or comparing error codes as part of logical operations that perform a different action. For example, error codes can be calculated and/or error codes can be compared as part of a refresh of the array 130.

Performing a refresh of the data stored in memory array 130 can include storing the data in sensing circuitry 150. The memory controller can determine whether memory cells that are refreshed fall within the memory address range provided by the host 110. If the memory cells do not fall within the memory address range, then other memory cells can continue to be refreshed. If memory cells are within the memory address range, then an error code can be created and the error codes can be compared for the data stored in the memory cells that are within the memory address range.

A refresh can include storing data in the sensing circuitry 150. Once the data is stored in the sensing circuitry 150, then an error code can be created for the stored data. The error code can be compared to a previously created error code for the data to determine whether the data has been modified.

Determining whether the data has been modified as part of the refresh can reduce the time needed to refresh the data and determine whether the data has been modified separately because both actions (e.g., refresh, and determine whether the data has been modified) include storing data in the sensing circuitry 150. Storing the data in the sensing circuitry 150 once to refresh the data and to determine whether the data has been modified reduces the number of times the data is stored in the sensing circuitry 150 which in turn reduces the time it takes to refresh the data and to determine whether the data has been modified.

FIG. 1B is a block diagram of an apparatus architecture in the form of a computing system including a plurality of memory devices 120-1, . . . 120-N coupled to a host 110 via a channel controller 143 in accordance with a number of embodiments of the present disclosure. In at least one embodiment the channel controller 143 may be coupled to the plurality of memory devices 120-1, . . . 120-N in an integrated manner in the form of a module 118, e.g., formed on same chip with the plurality of memory devices 120-1, . . . 120-N. In an alternative embodiment, the channel controller 143 may be integrated with the host 110, as illustrated by dashed lines 111, e.g., formed on a separate chip from the plurality of memory devices 120-1, . . . 120-N. The channel controller 143 can be coupled to each of the plurality of memory devices 120-1, . . . 120-N via a control bus (e.g., address and control (A/C) bus) 154 as described in FIG. 1A which in turn can be coupled to the host 110. The channel controller 143 can also be coupled to each of the plurality of memory devices, 120-1, . . . 120-N via a data bus 156 as described in FIG. 1A which in turn can be coupled to the host 110. In addition, the channel controller 143 can be coupled to each of the plurality of memory devices 120-1, . . . 120-N via an OOB bus 157 associated with a high speed interface (HSI) 141, described more in connection with FIGS. 5-8, that is configured to report status, exception and other data information to the channel controller 143 to exchange with the host 110. For example, the channel controller 143 can notify the host 110 that a first error code and a second error code are not the same indicating that data stored in a particular number of memory cells has been modified. The channel controller 143 can notify the host 110 via control bus 154, data bus 156, and/or OOB bus 157.

As shown in FIG. 1B, the channel controller 143 can receive the status and exception information from a high speed interface (HSI) (also referred to herein as a status channel interface) 141 associated with a bank arbiter 145 in each of the plurality of memory devices 120-1, . . . 120-N. In the example of FIG. 1B, each of the plurality of memory devices 120-1, . . . 120-N can include a bank arbiter 145 to sequence control and data with a plurality of banks, e.g., Bank zero (0), Bank one (1), . . . , Bank six (6), Bank seven (7), etc. Each of the plurality of banks, Bank 0, . . . , Bank 7, can include a memory controller 140 and other components, including an array of memory cells 130 and sensing circuitry 150, peripheral logic 170, etc., as described in connection with FIG. 1A.

That is, each of the plurality of banks, e.g., Bank 0, . . . , Bank 7, in the plurality of memory devices 120-1, . . . 120-N can include address circuitry 142 in FIG. 1A to latch address signals provided over a data bus 156 (e.g., an I/O bus) through I/O circuitry 144. Status, exception information, and/or a notification that that data stored in a particular number of memory cells has changed can be provided from the memory controller 140 on the memory device 120 to the channel controller 143, using the OOB bus 157, which in turn can be provided from the plurality of memory devices 120-1, . . . 120-N to the host 110. For each of the plurality of banks, e.g., Bank 0, . . . , Bank 7, address signals can be received through address circuitry 142 in FIG. 1A and decoded by a row decoder 146 and a column decoder 152 in FIG. 1A to access the memory array 130 in FIG. 1A. Data can be read from memory array 130 by sensing voltage and/or current changes on the data lines using sensing circuitry 150 in FIG. 1A. The sensing circuitry 150 can read and latch a page (e.g., row) of data from the memory array 130. The I/O circuitry 144 in FIG. 1A can be used for bi-directional data communication with host 110 over the data bus 156. The write circuitry 148 in FIG. 1A can used to write data to the memory array 130 and the OOB bus 157 can be used to report status, exception and other data information to the channel controller 143.

The channel controller 143 can include one or more local buffers 161 to store an program instructions and can include logic 160 to allocate a plurality of locations, e.g., subarrays, in the arrays of each respective bank to store bank commands, and arguments, (PIM commands) for the various banks associated with to operation of each of the plurality of memory devices 120-1, . . . 120-N. The channel controller 143 can dispatch commands, e.g., PIM commands, to the plurality of memory devices 120-1, . . . 120-N to store those program instructions within a given bank of a memory device.

As described above in connection with FIG. 1A, the memory array 130 can be a DRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash array, and/or NOR flash array, for instance. The array 130 can comprise memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines, which may be referred to herein as data lines or digit lines.

As in FIG. 1A, a memory controller 140, e.g., bank control logic and/or sequencer, associated with any particular bank, Bank 0, . . . , Bank 7, in a given memory device, 120-1, . . . 120-N, can decode signals provided by control bus 154 from the host 110. These signals can include chip enable signals, write enable signals, and address latch signals that are used to control operations performed on the memory array 130, including data read, data write, and data erase operations. In various embodiments, the memory controller 140 is responsible for executing instructions from the host 110. And, as above, the memory controller 140 can be a state machine, a sequencer, or some other type of controller. That is, the controller 140 can control shifting data (e.g., right or left) in an array, e.g., memory array 130.

FIG. 2 is a schematic diagram illustrating sensing circuitry 250 in accordance with a number of embodiments of the present disclosure. The sensing circuitry 250 can correspond to sensing circuitry 150 shown in FIG. 1A. The sense amplifier 206 of sensing circuitry 250 can correspond to sense amplifiers 206 shown in FIG. 2, and the compute component 231 of sensing circuitry 250 can correspond to sensing circuitry, including compute component.

A memory cell comprises a storage element (e.g., capacitor) and an access device (e.g., transistor). For instance, a first memory cell comprises transistor 202-1 and capacitor 203-1, and a second memory cell comprises transistor 202-2 and capacitor 203-2, etc. In this example, the memory array 230 is a DRAM array of 1T1C (one transistor one capacitor) memory cells. In a number of embodiments, the memory cells may be destructive read memory cells (e.g., reading the data stored in the cell destroys the data such that the data originally stored in the cell is refreshed after being read).

The cells of the memory array 230 can be arranged in rows coupled by word lines 204-X (Row X), 204-Y (Row Y), etc., and columns coupled by pairs of complementary sense lines (e.g., data lines DIGIT(n−1)/DIGIT(n−1)_, DIGIT(n)/DIGIT(n)_, DIGIT(n+1)/DIGIT(n+1)_. The individual sense lines corresponding to each pair of complementary sense lines can also be referred to as data lines 205-1 (D) and 205-2 (D_) respectively. Although only one pair of complementary data lines are shown in FIG. 2, embodiments of the present disclosure are not so limited, and an array of memory cells can include additional columns of memory cells and/or data lines (e.g., 4,096, 8,192, 16,384, etc.).

Memory cells can be coupled to different data lines and/or word lines. For example, a first source/drain region of a transistor 202-1 can be coupled to data line 205-1 (D), a second source/drain region of transistor 202-1 can be coupled to capacitor 203-1, and a gate of a transistor 202-1 can be coupled to word line 204-X. A first source/drain region of a transistor 202-2 can be coupled to data line 205-2 (D_), a second source/drain region of transistor 202-2 can be coupled to capacitor 203-2, and a gate of a transistor 202-2 can be coupled to word line 204-Y. The cell plate, as shown in FIG. 2, can be coupled to each of capacitors 203-1 and 203-2. The cell plate can be a common node to which a reference voltage (e.g., ground) can be applied in various memory array configurations.

The memory array 230 is coupled to sensing circuitry 250 in accordance with a number of embodiments of the present disclosure. In this example, the sensing circuitry 250 comprises a sense amplifier 206 and a compute component 231 corresponding to respective columns of memory cells (e.g., coupled to respective pairs of complementary data lines). The sense amplifier 206 can be coupled to the pair of complementary sense lines 205-1 and 205-2. The compute component 231 can be coupled to the sense amplifier 206 via pass gates 207-1 and 207-2. The gates of the pass gates 207-1 and 207-2 can be coupled to logical operation selection logic 213.

The logical operation selection logic 213 can be configured to include pass gate logic for controlling pass gates that couple the pair of complementary sense lines un-transposed between the sense amplifier 206 and the compute component 231 (as shown in FIG. 2) and/or swap gate logic for controlling swap gates that couple the pair of complementary sense lines transposed between the sense amplifier 206 and the compute component 231. The logical operation selection logic 213 can also be coupled to the pair of complementary sense lines 205-1 and 205-2. The logical operation selection logic 213 can be configured to control continuity of pass gates 207-1 and 207-2 based on a selected logical operation, as described in detail below for various configurations of the logical operation selection logic 413.

The sense amplifier 206 can be operated to determine a data value (e.g., logic state) stored in a selected memory cell. The sense amplifier 206 can comprise a cross coupled latch, which can be referred to herein as a primary latch. In the example illustrated in FIG. 2, the circuitry corresponding to sense amplifier 206 comprises a latch 215 including four transistors coupled to a pair of complementary data lines D 205-1 and D205-2. However, embodiments are not limited to this example. The latch 215 can be a cross coupled latch (e.g., gates of a pair of transistors, such as n-channel transistors (e.g., NMOS transistors) 227-1 and 227-2 are cross coupled with the gates of another pair of transistors, such as p-channel transistors (e.g., PMOS transistors) 229-1 and 229-2). The cross coupled latch 215 comprising transistors 227-1, 227-2, 229-1, and 229-2 can be referred to as a primary latch.

In operation, when a memory cell is being sensed (e.g., read), the voltage on one of the data lines 205-1 (D) or 205-2 (D_) will be slightly greater than the voltage on the other one of data lines 205-1 (D) or 205-2 (D_). An ACT signal and the RNL* signal can be driven low to enable (e.g., fire) the sense amplifier 206. The data lines 205-1 (D) or 205-2 (D_) having the lower voltage will turn on one of the PMOS transistor 229-1 or 229-2 to a greater extent than the other of PMOS transistor 229-1 or 229-2, thereby driving high the data line 205-1 (D) or 205-2 (D_) having the higher voltage to a greater extent than the other data line 205-1 (D) or 205-2 (D_) is driven high.

Similarly, the data line 205-1 (D) or 205-2 (D_) having the higher voltage will turn on one of the NMOS transistor 227-1 or 227-2 to a greater extent than the other of the NMOS transistor 227-1 or 227-2, thereby driving low the data line 205-1 (D) or 205-2 (D_) having the lower voltage to a greater extent than the other data line 205-1 (D) or 205-2 (D_) is driven low. As a result, after a short delay, the data line 205-1 (D) or 205-2 (D_) having the slightly greater voltage is driven to the voltage of the supply voltage VCC through source transistor 211, and the other data line 205-1 (D) or 205-2 (D_) is driven to the voltage of the reference voltage (e.g., ground) through the sink transistor 213. Therefore, the cross coupled NMOS transistors 227-1 and 227-2 and PMOS transistors 229-1 and 229-2 serve as a sense amplifier pair, which amplify the differential voltage on the data lines 205-1 (D) and 205-2 (D_) and operate to latch a data value sensed from the selected memory cell. As used herein, the cross coupled latch of sense amplifier 206 may be referred to as a primary latch 215.

Embodiments are not limited to the sense amplifier 206 configuration illustrated in FIG. 2. As an example, the sense amplifier 206 can be current-mode sense amplifier and/or single-ended sense amplifier (e.g., sense amplifier coupled to one data line). Also, embodiments of the present disclosure are not limited to a folded data line architecture such as that shown in FIG. 2.

The sense amplifier 206 can, in conjunction with the compute component 231, be operated to perform various logical operations using data from an array as input. In a number of embodiments, the result of a logical operation can be stored back to the array without transferring the data via a data line address access (e.g., without firing a column decode signal such that data is transferred to circuitry external from the array and sensing circuitry via local I/O lines). As such, a number of embodiments of the present disclosure can enable performing logical operations and compute functions associated therewith using less power than various previous approaches. Additionally, since a number of embodiments eliminate the need to transfer data across I/O lines in order to perform compute functions (e.g., between memory and discrete processor), a number of embodiments can enable an increased parallel processing capability as compared to previous approaches. For example, the sense amplifier 206 can, in conjunction with the compute component 231, be operated to calculate an error code for data stored in an array and to compare the error code with an initial error code for the data to determine whether the data has been modified.

The sense amplifier 206 can further include equilibration circuitry 214, which can be configured to equilibrate the data lines 205-1 (D) and 205-2 (D_). In this example, the equilibration circuitry 214 comprises a transistor 224 coupled between data lines 205-1 (D) and 205-2 (D_). The equilibration circuitry 214 also comprises transistors 225-1 and 225-2 each having a first source/drain region coupled to an equilibration voltage (e.g., VDD/2), where VDD is a supply voltage associated with the array. A second source/drain region of transistor 225-1 can be coupled data line 205-1 (D) and a second source/drain region of transistor 225-2 can be coupled data line 205-2 (D_). Gates of transistors 224, 225-1 and 225-2 can be coupled together, and to an equilibration (EQ) control signal line 226. As such, activating EQ enables the transistors 224, 225-1, and 225-2, which effectively shorts data lines 205-1 (D) and 205-2 (D_) together and to the an equilibration voltage (e.g., VCC/2).

Although FIG. 2 shows sense amplifier 206 comprising the equilibration circuitry 214, embodiments are not so limited, and the equilibration circuitry 214 may be implemented discretely from the sense amplifier 206, implemented in a different configuration than that shown in FIG. 2, or not implemented at all.

As described further below, in a number of embodiments, the sensing circuitry (e.g., sense amplifier 206 and compute component 231) can be operated to perform a selected logical operation and initially store the result in one of the sense amplifier 206 or the compute component 231 without transferring data from the sensing circuitry via an I/O line (e.g., without performing a data line address access via activation of a column decode signal, for instance).

Performance of logical operations (e.g., Boolean logical functions involving data values) is fundamental and commonly used. Boolean logic functions are used in many higher level functions. Consequently, speed and/or power efficiencies that can be realized with improved logical operations, can translate into speed and/or power efficiencies of higher order functionalities.

As shown in FIG. 2, the compute component 231 can also comprise a latch, which can be referred to herein as a secondary latch 264. The secondary latch 264 can be configured and operated in a manner similar to that described above with respect to the primary latch 215, with the exception that the pair of cross coupled p-channel transistors (e.g., PMOS transistors) comprising the secondary latch can have their respective sources coupled to a supply voltage (e.g., VDD), and the pair of cross coupled n-channel transistors (e.g., NMOS transistors) of the secondary latch can have their respective sources selectively coupled to a reference voltage (e.g., ground), such that the secondary latch is continuously enabled. The configuration of the compute component is not limited to that shown in FIG. 2 at 231, and various other embodiments are described further below.

FIG. 3 is a schematic diagram illustrating sensing circuitry capable of implementing an XOR logical operation in accordance with a number of embodiments of the present disclosure. FIG. 3 shows a sense amplifier 306 coupled to a pair of complementary sense lines 305-1 and 305-2, and a compute component 331 coupled to the sense amplifier 306 via pass gates 307-1 and 307-2. The sense amplifier 306 shown in FIG. 3 can correspond to sense amplifier 206 shown in FIG. 2. The compute component 331 shown in FIG. 3 can correspond to sensing circuitry, including compute component, 150 shown in FIG. 1A, for example. The logical operation selection logic 313 shown in FIG. 3 can correspond to logical operation selection logic 413 shown in FIG. 4, for example.

The gates of the pass gates 307-1 and 307-2 can be controlled by a logical operation selection logic signal, Pass. For example, an output of the logical operation selection logic can be coupled to the gates of the pass gates 307-1 and 307-2. The compute component 331 can comprise a loadable shift register configured to shift data values left and right.

The sensing circuitry shown in FIG. 3 also shows a logical operation selection logic 313 coupled to a number of logic selection control input control lines, including ISO, TF, TT, FT, and FF. Selection of a logical operation from a plurality of logical operations is determined from the condition of logic selection control signals on the logic selection control input control lines, as well as the data values present on the pair of complementary sense lines 305-1 and 305-2 when the isolation transistors are enabled via the ISO control signal being asserted.

According to various embodiments, the logical operation selection logic 313 can include four logic selection transistors: logic selection transistor 362 coupled between the gates of the swap transistors 342 and a TF signal control line, logic selection transistor 352 coupled between the gates of the pass gates 307-1 and 307-2 and a TT signal control line, logic selection transistor 354 coupled between the gates of the pass gates 307-1 and 307-2 and a FT signal control line, and logic selection transistor 364 coupled between the gates of the swap transistors 342 and a FF signal control line. Gates of logic selection transistors 362 and 352 are coupled to the true sense line through isolation transistor 350-1 (having a gate coupled to an ISO signal control line). Gates of logic selection transistors 364 and 354 are coupled to the complementary sense line through isolation transistor 350-2 (also having a gate coupled to an ISO signal control line).

Data values present on the pair of complementary sense lines 305-1 and 305-2 can be loaded into the compute component 331 via the pass gates 307-1 and 307-2. The compute component 331 can comprise a loadable shift register. When the pass gates 307-1 and 307-2 are OPEN, data values on the pair of complementary sense lines 305-1 and 305-2 are passed to the compute component 331 and thereby loaded into the loadable shift register. The data values on the pair of complementary sense lines 305-1 and 305-2 can be the data value stored in the sense amplifier 306 when the sense amplifier is fired. The logical operation selection logic signal, Pass, is high to OPEN the pass gates 307-1 and 307-2.

The ISO, TF, TT, FT, and FF control signals can operate to select a logical function to implement based on the data value (“B”) in the sense amplifier 306 and the data value (“A”) in the compute component 331. In particular, the ISO, TF, TT, FT, and FF control signals are configured to select the logical function to implement independent from the data value present on the pair of complementary sense lines 305-1 and 305-2 (although the result of the implemented logical operation can be dependent on the data value present on the pair of complementary sense lines 305-1 and 305-2. That is, the ISO, TF, TT, FT, and FF control signals select the logical operation to implement directly since the data value present on the pair of complementary sense lines 305-1 and 305-2 is not passed through logic to operate the gates of the pass gates 307-1 and 307-2.

Additionally, FIG. 3 shows swap transistors 342 configured to swap the orientation of the pair of complementary sense lines 305-1 and 305-2 between the sense amplifier 313-7 and the compute component 331. When the swap transistors 342 are OPEN, data values on the pair of complementary sense lines 305-1 and 305-2 on the sense amplifier 306 side of the swap transistors 342 are oppositely-coupled to the pair of complementary sense lines 305-1 and 305-2 on the compute component 331 side of the swap transistors 342, and thereby loaded into the loadable shift register of the compute component 331.

The logical operation selection logic signal Pass can be activated (e.g., high) to OPEN the pass gates 307-1 and 307-2 (e.g., conducting) when the ISO control signal line is activated and either the TT control signal is activated (e.g., high) with data value on the true sense line is “1” or the FT control signal is activated (e.g., high) with the data value on the complement sense line is “1.”

The data value on the true sense line being a “1” OPENs logic selection transistors 352 and 362. The data value on the complimentary sense line being a “1” OPENs logic selection transistors 354 and 364. If the ISO control signal or either the respective TT/FT control signal or the data value on the corresponding sense line (e.g., sense line to which the gate of the particular logic selection transistor is coupled) is not high, then the pass gates 307-1 and 307-2 will not be OPENed by a particular logic selection transistor.

The logical operation selection logic signal PassF can be activated (e.g., high) to OPEN the swap transistors 342 (e.g., conducting) when the ISO control signal line is activated and either the TF control signal is activated (e.g., high) with data value on the true sense line is “1,” or the FF control signal is activated (e.g., high) with the data value on the complement sense line is “1.” If either the respective control signal or the data value on the corresponding sense line (e.g., sense line to which the gate of the particular logic selection transistor is coupled) is not high, then the swap transistors 342 will not be OPENed by a particular logic selection transistor.

The Pass* control signal is not necessarily complementary to the Pass control signal. It is possible for the Pass and Pass* control signals to both be activated or both be deactivated at the same time. However, activation of both the Pass and Pass* control signals at the same time shorts the pair of complementary sense lines together, which may be a disruptive configuration to be avoided.

The sensing circuitry illustrated in FIG. 3 is configured to select one of a plurality of logical operations to implement directly from the four logic selection control signals (e.g., logical operation selection is not dependent on the data value present on the pair of complementary sense lines). Some combinations of the logic selection control signals can cause both the pass gates 307-1 and 307-2 and swap transistors 342 to be OPEN at the same time, which shorts the pair of complementary sense lines 305-1 and 305-2 together. According to a number of embodiments of the present disclosure, the logical operations which can be implemented by the sensing circuitry illustrated in FIG. 3 can be the logical operations summarized in the logic tables shown in FIG. 4.

FIG. 4 is a logic table illustrating selectable logic operation results implemented by a sensing circuitry shown in FIG. 3 in accordance with a number of embodiments of the present disclosure. The four logic selection control signals (e.g., TF, TT, FT, and FF), in conjunction with a particular data value present on the complementary sense lines, can be used to select one of plural logical operations to implement involving the starting data values stored in the sense amplifier 806 and compute component 831. The four control signals, in conjunction with a particular data value present on the complementary sense lines, controls the continuity of the pass gates 807-1 and 807-2 and swap transistors 842, which in turn affects the data value in the compute component 831 and/or sense amplifier 806 before/after firing. The capability to selectably control continuity of the swap transistors 842 facilitates implementing logical operations involving inverse data values (e.g., inverse operands and/or inverse result), among others.

Logic Table 4-1 illustrated in FIG. 4 shows the starting data value stored in the compute component 631 shown in column A at 444, and the starting data value stored in the sense amplifier 606 shown in column B at 445. The other 3 column headings in Logic Table 4-1 refer to the continuity of the pass gates 307-1 and 307-2, and the swap transistors 342, which can respectively be controlled to be OPEN or CLOSED depending on the state of the four logic selection control signals (e.g., TF, TT, FT, and FF), in conjunction with a particular data value present on the pair of complementary sense lines 305-1 and 305-2. The “Not Open” column corresponds to the pass gates 307-1 and 307-2 and the swap transistors 342 both being in a non-conducting condition, the “Open True” corresponds to the pass gates 307-1 and 307-2 being in a conducting condition, and the “Open Invert” corresponds to the swap transistors 342 being in a conducting condition. The configuration corresponding to the pass gates 307-1 and 307-2 and the swap transistors 342 both being in a conducting condition is not reflected in Logic Table 4-1 since this results in the sense lines being shorted together.

Via selective control of the continuity of the pass gates 307-1 and 307-2 and the swap transistors 342, each of the three columns of the upper portion of Logic Table 4-1 can be combined with each of the three columns of the lower portion of Logic Table 4-1 to provide 3×3=9 different result combinations, corresponding to nine different logical operations, as indicated by the various connecting paths shown at 475. The nine different selectable logical operations that can be implemented by the sensing circuitry 850 are summarized in Logic Table 4-2 illustrated in FIG. 4, including an XOR logical operation.

The columns of Logic Table 4-2 illustrated in FIG. 4 show a heading 480 that includes the state of logic selection control signals. For example, the state of a first logic selection control signal is provided in row 476, the state of a second logic selection control signal is provided in row 477, the state of a third logic selection control signal is provided in row 478, and the state of a fourth logic selection control signal is provided in row 479. The particular logical operation corresponding to the results is summarized in row 447.

FIG. 5 illustrates an example of an OOB bus (HSI) 557 between channel controller 543 and a bank arbiter of a memory device 520 in the x64DQ one (1) rank configuration. As shown in the example of FIG. 5, one rank enable bit (pin) 547 is provided from the channel controller 543 to the memory device 520. In this example, 16 SQ (status outputs/pins) 549 are received from the memory device 520 for the channel and 4 SQS (status output strobes) 551 may be received.

FIG. 6 illustrates an example of an OOB bus (HSI) 657 between channel controller 643 and a bank arbiter of a memory device 620 in the x64DQ four (4) rank configuration. In this example, each of four (4) separate rank enable bits 647 are shown (0, 1, 2, and 3) on the channel controller 643 independently connected for one channel to four memory devices 620-1, 620-2, . . . , 620-4. In this example, 16 SQ (status outputs) 649 are still received, but now from the four memory devices 620-1, 620-2, . . . , 620-4 for the channel. Likewise, four (4) SQS (status output strobes) 651 are received on the channel for the four memory devices 620-1, 620-2, . . . , 620-4.

In this case, the bandwidth of the status channel is divided just as the bandwidth of a double data rate (DDR) interface is divided, being effectively time domain multiplexed to avoid contention on the OOB 657. Each memory device 620, e.g., 620-1, 620-2, . . . , 620-4, is granted access to the uni-directional status bus 657 in turn as its rank enable input is activated. When x64 mode is selected (fuse option or test option), each memory device 620 may transmit one data packet at an active edge of the rank enable input. Status output bits 649 can be streamed out, 1 bit per clock cycle, synchronized to the SQS strobe pins 651. The first bit may be a preamble bit. In one example, if the preamble bit is a logic 0, the memory device, e.g., 620-1, 620-2, . . . , 620-4, will transmit a 128 bit status message on the 16 DQs on eight (8) successive clocks. At the end of this message the SQ and SQS pins will transition to a tri-state mode, and the interface circuitry will wait for the next active edge on the rank enable input to transmit additional messages. If there are no messages waiting in a memory controller's (e.g., memory controller 640 of a given memory device 620) output queue, the sense of the preamble bit will be logic 1. The SQ and SQS drivers will be turned off on the next successive clock. The memory device will go back to waiting for another active edge on the rank enable input.

FIG. 7 illustrates an example of an OOB bus (HSI) 757 between channel controller 743 and the bank arbiter of a memory device 720 in an x32DQ one (1) rank configuration. In the case of a x32 DQ configuration on the memory 720, the status channel can be split, as shown in FIG. 7, just as the data channel can be split, with half of the status outputs 740 (as well as half of the DQs and DQSs) going to each of the memory devices 720 in the architecture.

In this example, the rank enable inputs 747 for the first rank are all tied together. Thus they will all begin transmitting their status messages on the lower eight (8) SQ pins 749. The protocol is largely the same as in the x64 case, with data being sent following a preamble on successive active clock edges of the SQSs. One deviation from the prior example is that since the data bus is half as wide for each memory device 720, the message length will increase from eight (8) data clocks to sixteen (16), to accommodate the same 128 bit message size.

FIG. 8 illustrates an example of an OOB bus (HSI) 857 between channel controller 843 and the bank arbiter of a memory device 820 in an x16 DQ four (4) rank configuration. In the case of a x16 DQ configuration on the memory 820, the status channel can be divided, as shown in FIG. 8, into four (4) parts with each memory device, e.g., 820-1, 820-5, 820-9 and 820-13, connected to the channel controller 843 via the lowest four (4) bits of a given memory device's SQ bus 849. In the example, the number of clock cycles per message again grows, now to thirty-two (32) to accommodate the same 128 bit message size.

Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combination of the above embodiments, and other embodiments not specifically described herein will be apparent to those of skill in the art upon reviewing the above description. The scope of the one or more embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.

In the foregoing Detailed Description, some features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

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Patents Cited in This Cited by
Title Current Assignee Application Date Publication Date
반도체 메모리 장치 삼성전자주식회사 15 June 2009 23 December 2010
감소 칩 영역을 가진 반도체 메모리 소자 닛본 덴끼 가부시끼가이샤 29 November 1996 02 August 1999
Digital computer ALLIANT COMPUTER SYSTEMS CORPORATION 17 June 1986 18 March 1987
一种处理器体系结构 上海芯豪微电子有限公司 29 January 2010 03 August 2011
반도체 메모리 장치 및 이를 위한 테스트 회로 에스케이하이닉스 주식회사 04 November 2011 14 May 2013
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PatSnap solutions are used by R&D teams, legal and IP professionals, those in business intelligence and strategic planning roles and by research staff at academic institutions globally.

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The widest range of IP search tools makes getting the right answers and asking the right questions easier than ever. One click analysis extracts meaningful information on competitors and technology trends from IP data.
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Gain powerful insights into future technology changes, market shifts and competitor strategies.
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Manage IP-related processes across multiple teams and departments with integrated collaboration and workflow tools.
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