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Patent Analysis of

Apparatuses and methods for performing logical operations using sensing circuitry

Updated Time 12 June 2019

Patent Registration Data

Publication Number

US10153009

Application Number

US15/965733

Application Date

27 April 2018

Publication Date

11 December 2018

Current Assignee

MICRON TECHNOLOGY, INC.

Original Assignee (Applicant)

MICRON TECHNOLOGY, INC.

International Classification

G11C7/00,G06F12/00,G11C15/00,G11C11/4096,G11C11/4093

Cooperative Classification

G11C7/065,G06F12/00,G11C7/1006,G11C7/1051,G11C11/4093

Inventor

MANNING, TROY A.

Patent Images

This patent contains figures and images illustrating the invention and its embodiment.

US10153009 Apparatuses performing 1 US10153009 Apparatuses performing 2 US10153009 Apparatuses performing 3
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Abstract

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.

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Claims

1. A memory device, comprising:

an array of memory cells coupled to sensing circuitry via sense lines; and control circuitry configured to provide control signals to the sensing circuitry to perform compute functions on data stored in the array by performing a logical operation between a first data value stored in a first memory cell and a second data value stored in a second memory cell; and wherein a result of the logical operation is stored in a first latch of the sensing circuitry, and wherein the memory device is configured to perform the logical operation without transferring data from the sense lines onto input/output lines configured to transfer data out of the sensing circuitry.

2. The memory device of claim 1, wherein the memory device comprises column decode circuitry coupled to the sensing circuitry and configured to transfer data into and out of the array via activation of column decode signals.

3. The memory device of claim 2, wherein the input/output lines are configured to transfer data from the sensing circuitry to a processing resource external to the memory device.

4. The memory device of claim 3, wherein the processing resource comprises a host processor.

5. The memory device of claim 1, wherein the sensing circuitry comprises the first latch and a second latch coupled to the first latch via a pair of pass transistors.

6. The memory device of claim 1, wherein the logical operation is a Boolean operation.

7. The memory device of claim 1, wherein the sensing circuitry comprises:

a compute component comprising the first latch; and a sense amplifier comprising a second latch.

8. The memory device of claim 7, wherein the compute component further comprises a pair of transistors configured to receive an invert control signal.

9. The memory device of claim 7, wherein the sense amplifier is coupled to equilibrate circuitry.

10. The memory device of claim 7, wherein the sensing circuitry comprises compute component and sense amplifier pairs coupled to respective columns the array.

11. A method, comprising:

determining data values stored in a number of memory cells of a first row of an array of memory cells, each of the number of memory cells coupled to a respective sense line of a number of sense lines; and performing, in parallel, logical operations using the data values stored in the number of memory cells of the first row as a number of first inputs and data values stored in a number of memory cells of a second row of the array as a number of second inputs, wherein each of the number of memory cells of the second row are coupled to a respective sense line of the number of sense lines; wherein the logical operations are performed in parallel without transferring data from the sense lines onto input/output lines configured to transfer data out of sensing circuitry coupled to the array; wherein each of the number of sense lines is coupled to a respective sense amplifier of a number of sense amplifiers, and each of the number of sense amplifiers is coupled to one of a respective number of compute components;wherein each compute component comprises:

a cross coupled latch; a pair of pass; and a pair of inverting transistors; andwherein performing the logical operations comprises:

transferring the data values stored in the number of memory cells of the first row to the number of cross coupled latches during a first operation phase in which the pass transistors are enabled; determining the data values stored in the number of memory cells of the second row while the pass transistors are disabled; and subsequently enabling only one respective pass transistor of each of the pair of pass transistors such that each cross coupled latch of the number of cross coupled latches stores a respective data value corresponding to a logical operation result of a data value stored in a respective memory cell of the number of memory cells of the first row and a data value stored in a respective memory cell of the number of memory cells of the second row.

12. The method of claim 11, wherein the cross coupled latch comprises a pair of n-channel transistors and a pair of p-channel transistors.

13. The method of claim 12, wherein a first pass transistor of the pair of pass transistors has a first source/drain node coupled to a gate of a second one of the pair of n-channel transistors, and wherein a second pass transistor of the pair of pass transistors has a first source/drain node coupled to a gate of a first one of the pair of n-channel transistors.

14. The method of claim 13, wherein a first inverting transistor of the pair of inverting transistors has a first source/drain node coupled to a second source/drain node of the first pass transistor and has a second source/drain node coupled to a source/drain node of a transistor whose gate is coupled to the gate of the second one of the pair of n-channel transistors, and wherein a second inverting transistor has a first source/drain node coupled to a second source/drain node of the second pass transistor and has a second source/drain node coupled to a source/drain node of a transistor whose gate is coupled to the gate of the first one of the pair of n-channel transistors.

15. A memory device, comprising:

an array of memory cells; and a controller configured to control sensing circuitry coupled to the array to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input; wherein the sensing circuitry is controlled to store a result of the logical operation in at least one of the first memory cell, the second memory cell, and a third memory cell; wherein the sense line comprises a first sense line of a pair of complementary sense lines; andwherein the sensing circuitry comprises:

a sense amplifier coupled to the pair of complementary sense lines; anda compute component coupled to the sense amplifier and comprising:

a cross-coupled latch comprising a pair of first transistors and a pair of second transistors;a first pass transistor having a first source/drain node coupled to:

a gate of a second one of the pair of first transistors; a gate of a second one of the pair of second transistors; and a first source/drain node of a first one of the pair of first transistors, the first pass transistor having a second source/drain node coupled to the sense line; anda second pass transistor having a first source/drain node coupled to:

a gate of a first one of the pair of first transistors; a gate of a first one of the pair of second transistors; and a first source/drain node of the second one of the pair of first transistors, the second pass transistor having a second source/drain node coupled to the second sense line of the pair of complementary sense lines;wherein the compute component further comprises:

a first inverting transistor having a first source/drain node coupled to a second source/drain node of the first pass transistor and having a second source/drain node coupled to a source/drain node of a first transistor whose gate is coupled to the gate of the second one of the pair of first transistors; and a second inverting transistor having a first source/drain node coupled to a second source/drain node of the second pass transistor and having a second source/drain node coupled to a source/drain node of a second transistor whose gate is coupled to the gate of the first one of the pair of first transistors.

16. The memory device of claim 15, wherein:

the second source/drain nodes of the first one and the second one of the pair of first transistors is commonly coupled to receive a negative control signal; and the second source/drain nodes of the first one and the second one of the pair of second transistors is commonly coupled to receive a positive control signal.

17. The memory device of claim 15, wherein the gates of the first and second inverting transistors are commonly coupled to receive an enabling signal.

18. The memory device of claim 15, wherein the pair of first transistors are n-channel transistors and the pair of second transistors are p-channel transistors.

19. The memory device of claim 15, wherein the second source/drain node of the first transistor is coupled to ground, and wherein the second source/drain node of the second transistor is coupled to ground.

20. The memory device of claim 15, wherein the memory cells are dynamic random access memory (DRAM) cells.

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Claim Tree

  • 1
    1. A memory device, comprising:
    • an array of memory cells coupled to sensing circuitry via sense lines
    • and control circuitry configured to provide control signals to the sensing circuitry to perform compute functions on data stored in the array by performing a logical operation between a first data value stored in a first memory cell and a second data value stored in a second memory cell
    • and wherein a result of the logical operation is stored in a first latch of the sensing circuitry, and wherein the memory device is configured to perform the logical operation without transferring data from the sense lines onto input/output lines configured to transfer data out of the sensing circuitry.
    • 2. The memory device of claim 1, wherein
      • the memory device comprises
    • 5. The memory device of claim 1, wherein
      • the sensing circuitry comprises
    • 6. The memory device of claim 1, wherein
      • the logical operation is a Boolean operation.
    • 7. The memory device of claim 1, wherein
      • the sensing circuitry comprises:
  • 11
    11. A method, comprising:
    • determining data values stored in a number of memory cells of a first row of an array of memory cells, each of the number of memory cells coupled to a respective sense line of a number of sense lines
    • and performing, in parallel, logical operations using the data values stored in the number of memory cells of the first row as a number of first inputs and data values stored in a number of memory cells of a second row of the array as a number of second inputs, wherein each of the number of memory cells of the second row are coupled to a respective sense line of the number of sense lines
    • wherein the logical operations are performed in parallel without transferring data from the sense lines onto input/output lines configured to transfer data out of sensing circuitry coupled to the array
    • wherein each of the number of sense lines is coupled to a respective sense amplifier of a number of sense amplifiers, and each of the number of sense amplifiers is coupled to one of a respective number of compute components
    • wherein each compute component comprises: a cross coupled latch
    • a pair of pass
    • and a pair of inverting transistors
    • andwherein performing the logical operations comprises: transferring the data values stored in the number of memory cells of the first row to the number of cross coupled latches during a first operation phase in which the pass transistors are enabled
    • determining the data values stored in the number of memory cells of the second row while the pass transistors are disabled
    • and subsequently enabling only one respective pass transistor of each of the pair of pass transistors such that each cross coupled latch of the number of cross coupled latches stores a respective data value corresponding to a logical operation result of a data value stored in a respective memory cell of the number of memory cells of the first row and a data value stored in a respective memory cell of the number of memory cells of the second row.
    • 12. The method of claim 11, wherein
      • the cross coupled latch comprises
  • 15
    15. A memory device, comprising:
    • an array of memory cells
    • and a controller configured to control sensing circuitry coupled to the array to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input
    • wherein the sensing circuitry is controlled to store a result of the logical operation in at least one of the first memory cell, the second memory cell, and a third memory cell
    • wherein the sense line comprises a first sense line of a pair of complementary sense lines
    • andwherein the sensing circuitry comprises: a sense amplifier coupled to the pair of complementary sense lines
    • anda compute component coupled to the sense amplifier and comprising: a cross-coupled latch comprising a pair of first transistors and a pair of second transistors
    • a first pass transistor having a first source/drain node coupled to: a gate of a second one of the pair of first transistors
    • a gate of a second one of the pair of second transistors
    • and a first source/drain node of a first one of the pair of first transistors, the first pass transistor having a second source/drain node coupled to the sense line
    • anda second pass transistor having a first source/drain node coupled to: a gate of a first one of the pair of first transistors
    • a gate of a first one of the pair of second transistors
    • and a first source/drain node of the second one of the pair of first transistors, the second pass transistor having a second source/drain node coupled to the second sense line of the pair of complementary sense lines
    • wherein the compute component further comprises: a first inverting transistor having a first source/drain node coupled to a second source/drain node of the first pass transistor and having a second source/drain node coupled to a source/drain node of a first transistor whose gate is coupled to the gate of the second one of the pair of first transistors
    • and a second inverting transistor having a first source/drain node coupled to a second source/drain node of the second pass transistor and having a second source/drain node coupled to a source/drain node of a second transistor whose gate is coupled to the gate of the first one of the pair of first transistors.
    • 16. The memory device of claim 15, wherein
      • : the second source/drain nodes of the first one and the second one of the pair of first transistors is commonly coupled to receive a negative control signal; and the second source/drain nodes of the first one and the second one of the pair of second transistors is commonly coupled to receive a positive control signal.
    • 17. The memory device of claim 15, wherein
      • the gates of the first and second inverting transistors are commonly coupled to receive an enabling signal.
    • 18. The memory device of claim 15, wherein
      • the pair of first transistors are n-channel transistors and the pair of second transistors are p-channel transistors.
    • 19. The memory device of claim 15, wherein
      • the second source/drain node of the first transistor is coupled to ground, and wherein
    • 20. The memory device of claim 15, wherein
      • the memory cells are dynamic random access memory (DRAM) cells.
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Description

TECHNICAL FIELD

The present disclosure relates generally to semiconductor memory and methods, and more particularly, to apparatuses and methods related to performing logical operations using sensing circuitry.

BACKGROUND

Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic systems. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), among others.

Electronic systems often include a number of processing resources (e.g., one or more processors), which may retrieve and execute instructions and store the results of the executed instructions to a suitable location. A processor can comprise a number of functional units such as arithmetic logic unit (ALU) circuitry, floating point unit (FPU) circuitry, and/or a combinatorial logic block, for example, which can be used to execute instructions by performing logical operations such as AND, OR, NOT, NAND, NOR, and XOR logical operations on data (e.g., one or more operands). For example, the functional unit circuitry (FUC) may be used to perform arithmetic operations such as addition, subtraction, multiplication, and/or division on operands.

A number of components in an electronic system may be involved in providing instructions to the FUC for execution. The instructions may be generated, for instance, by a processing resource such as a controller and/or host processor. Data (e.g., the operands on which the instructions will be executed) may be stored in a memory array that is accessible by the FUC. The instructions and/or data may be retrieved from the memory array and sequenced and/or buffered before the FUC begins to execute instructions on the data. Furthermore, as different types of operations may be executed in one or multiple clock cycles through the FUC, intermediate results of the instructions and/or data may also be sequenced and/or buffered.

In many instances, the processing resources (e.g., processor and/or associated FUC) may be external to the memory array, and data is accessed via a bus between the processing resources and the memory array to execute a set of instructions. Processing performance may be improved in a processor-in-memory (PIM) device, in which a processor may be implemented internal and/or near to a memory (e.g., directly on a same chip as the memory array), which may conserve time and power in processing. However, such PIM devices may have various drawbacks such as an increased chip size. Moreover, such PIM devices may still consume undesirable amounts of power in association with performing logical operations (e.g., compute functions).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an apparatus in the form of a computing system including a memory system in accordance with a number of embodiments of the present disclosure.

FIG. 2A illustrates a schematic diagram of a portion of a memory array coupled to sensing circuitry in accordance with a number of embodiments of the present disclosure.

FIG. 2B illustrates a timing diagram associated with performing a logical operation using sensing circuitry in accordance with a number of embodiments of the present disclosure.

FIG. 3 illustrates a schematic diagram of a portion of sensing circuitry in accordance with a number of embodiments of the present disclosure.

DETAILED DESCRIPTION

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.

A number of embodiments of the present disclosure can provide improved parallelism and/or reduced power consumption in association with performing compute functions as compared to previous systems such as previous PIM systems and systems having an external processor (e.g., a processing resource located external from a memory array, such as on a separate integrated circuit chip). For instance, a number of embodiments can provide for performing fully complete compute functions such as integer add, subtract, multiply, divide, and CAM (content addressable memory) functions without transferring data out of the memory array and sensing circuitry via a bus (e.g., data bus, address bus, control bus), for instance. Such compute functions can involve performing a number of logical operations (e.g., AND, NOT, NOR, NAND, XOR, etc.). However, embodiments are not limited to these examples. For instance, performing logical operations can include performing a number of non-boolean logic operations such as copy, compare, destroy, etc.

In previous approaches, data may be transferred from the array and sensing circuitry (e.g., via a bus comprising input/output (I/O) lines) to a processing resource such as a processor, microprocessor, and/or compute engine, which may comprise ALU circuitry and/or other functional unit circuitry configured to perform the appropriate logical operations. However, transferring data from a memory array and sensing circuitry to such processing resource(s) can involve significant power consumption. Even if the processing resource is located on a same chip as the memory array, significant power can be consumed in moving data out of the array to the compute circuitry, which can involve performing a sense line address access (e.g., firing of a column decode signal) in order to transfer data from sense lines onto I/O lines, moving the data to the array periphery, and providing the data to the compute function.

Furthermore, the circuitry of the processing resource(s) (e.g., compute engine) may not conform to pitch rules associated with a memory array. For example, the cells of a memory array may have a 4F2 or 6F2 cell size, where “F” is a feature size corresponding to the cells. As such, the devices (e.g., logic gates) associated with ALU circuitry of previous PIM systems may not be capable of being formed on pitch with the memory cells, which can affect chip size and/or memory density, for example.

In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how one or more embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure. As used herein, the designator “N,” particularly with respect to reference numerals in the drawings, indicates that a number of the particular feature so designated can be included. As used herein, “a number of” a particular thing can refer to one or more of such things (e.g., a number of memory arrays can refer to one or more memory arrays).

The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, 130 may reference element “30” in FIG. 1, and a similar element may be referenced as 230 in FIG. 2. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, as will be appreciated, the proportion and the relative scale of the elements provided in the figures are intended to illustrate certain embodiments of the present invention, and should not be taken in a limiting sense.

FIG. 1 is a block diagram of an apparatus in the form of a computing system 100 including a memory device 120 in accordance with a number of embodiments of the present disclosure. As used herein, a memory device 120, a memory array 130, and/or sensing circuitry 150 might also be separately considered an “apparatus.”

System 100 includes a host 110 coupled to memory device 120, which includes a memory array 130. Host 110 can be a host system such as a personal laptop computer, a desktop computer, a digital camera, a mobile telephone, or a memory card reader, among various other types of hosts. Host 102 can include a system motherboard and/or backplane and can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry). The system 100 can include separate integrated circuits or both the host 110 and the memory device 120 can be on the same integrated circuit. The system 100 can be, for instance, a server system and/or a high performance computing (HPC) system and/or a portion thereof. Although the example shown in FIG. 1 illustrates a system having a Von Neumann architecture, embodiments of the present disclosure can be implemented in non-Von Neumann architectures (e.g., a Turing machine), which may not include one or more components (e.g., CPU, ALU, etc.) often associated with a Von Neumann architecture.

For clarity, the system 100 has been simplified to focus on features with particular relevance to the present disclosure. The memory array 130 can be a DRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash array, and/or NOR flash array, for instance. The array 130 can comprise memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as digit lines or data lines). Although a single array 130 is shown in FIG. 1, embodiments are not so limited. For instance, memory device 120 may include a number of arrays 130 (e.g., a number of banks of DRAM cells). An example DRAM array is described in association with FIG. 2.

The memory device 120 includes address circuitry 142 to latch address signals provided over an I/O bus 156 (e.g., a data bus) through I/O circuitry 144. Address signals are received and decoded by a row decoder 146 and a column decoder 152 to access the memory array 130. Data can be read from memory array 130 by sensing voltage and/or current changes on the sense lines using sensing circuitry 150. The sensing circuitry 150 can read and latch a page (e.g., row) of data from the memory array 130. The I/O circuitry 144 can be used for bi-directional data communication with host 110 over the I/O bus 156. The write circuitry 148 is used to write data to the memory array 130.

Control circuitry 140 decodes signals provided by control bus 154 from the host 110. These signals can include chip enable signals, write enable signals, and address latch signals that are used to control operations performed on the memory array 130, including data read, data write, and data erase operations. In various embodiments, the control circuitry 140 is responsible for executing instructions from the host 110. The control circuitry 140 can be a state machine, a sequencer, or some other type of controller.

An example of the sensing circuitry 150 is described further below in association with FIGS. 2 and 3. For instance, in a number of embodiments, the sensing circuitry 150 can comprise a number of sense amplifiers (e.g., sense amplifier 206 shown in FIG. 2 or sense amplifier 306 shown in FIG. 3) and a number of compute components, which may comprise an accumulator (e.g., compute component 231 shown in FIG. 2) and can be used to perform logical operations (e.g., on data associated with complementary sense lines). In a number of embodiments, the sensing circuitry (e.g., 150) can be used to perform logical operations using data stored in array 130 as inputs and store the results of the logical operations back to the array 130 without transferring via a sense line address access (e.g., without firing a column decode signal). As such, various compute functions can be performed within using sensing circuitry 150 rather than being performed by processing resources external to the sensing circuitry (e.g., by a processor associated with host 110 and/or other processing circuitry, such as ALU circuitry, located on device 120 (e.g., on control circuitry 140 or elsewhere)). In various previous approaches, data associated with an operand, for instance, would be read from memory via sensing circuitry and provided to external ALU circuitry via local I/O lines. The external ALU circuitry would perform compute functions using the operands and the result would be transferred back to the array via the local I/O lines. In contrast, in a number of embodiments of the present disclosure, sensing circuitry (e.g., 150) is configured to perform logical operations on data stored in memory (e.g., array 130) and store the result to the memory without enabling a local I/O line coupled to the sensing circuitry.

As such, in a number of embodiments, circuitry external to array 130 and sensing circuitry 150 is not needed to perform compute functions as the sensing circuitry 150 can perform the appropriate logical operations to perform such compute functions without the use of an external processing resource. Therefore, the sensing circuitry 150 may be used compliment and/or to replace, at least to some extent, such an external processing resource (or at least the bandwidth of such an external processing resource). However, in a number of embodiments, the sensing circuitry 150 may be used to perform logical operations (e.g., to execute instructions) in addition to logical operations performed by an external processing resource (e.g., host 110). For instance, host 110 and/or sensing circuitry 150 may be limited to performing only certain logical operations and/or a certain number of logical operations.

FIG. 2 illustrates a schematic diagram of a portion of a memory array 230 coupled to sensing circuitry in accordance with a number of embodiments of the present disclosure. In this example, the memory array 230 is a DRAM array of 1T1C (one transistor one capacitor) memory cells each comprised of an access device 202 (e.g., transistor) and a storage element 203 (e.g., a capacitor). In a number of embodiments, the memory cells are destructive read memory cells (e.g., reading the data stored in the cell destroys the data such that the data originally stored in the cell is refreshed after being read). The cells of array 230 are arranged in rows coupled by word lines 204-0 (Row0), 204-1 (Row1), 204-2, (Row2) 204-3 (Row3), . . . , 204-N (RowN) and columns coupled by sense lines (e.g., digit lines) 205-1 (D) and 205-2 (D_). In this example, each column of cells is associated with a pair of complementary sense lines 205-1 (D) and 205-2 (D_). Although only a single column of memory cells is illustrated in FIG. 2A, embodiments are not so limited. For instance, a particular array may have a number of columns of memory cells and/or sense lines (e.g., 4,096, 8,192, 16,384, etc.). A gate of a particular memory cell transistor 202 is coupled to its corresponding word line 204-0, 204-1, 204-2, 204-3, . . . , 204-N, a first source/drain region is coupled to its corresponding sense line 205-1, and a second source/drain region of a particular memory cell transistor is coupled to its corresponding capacitor 203. Although not illustrated in FIG. 2A, the sense line 205-2 may also be coupled to a column of memory cells.

The array 230 is coupled to sensing circuitry in accordance with a number of embodiments of the present disclosure. In this example, the sensing circuitry comprises a sense amplifier 206 and a compute component 231. The sensing circuitry can be sensing circuitry 150 shown in FIG. 1. The sense amplifier 206 is coupled to the complementary sense lines D, Dcorresponding to a particular column of memory cells. The sense amplifier 206 can be a sense amplifier such as sense amplifier 306 described below in association with FIG. 3. As such, the sense amp 206 can be operated to determine a state (e.g., logic data value) stored in a selected cell. Embodiments are not limited to the example sense amplifier 206. For instance, sensing circuitry in accordance with a number of embodiments described herein can include current-mode sense amplifiers and/or single-ended sense amplifiers (e.g., sense amplifiers coupled to one sense line).

In a number of embodiments, a compute component (e.g., 231) can comprise a number of transistors formed on pitch with the transistors of the sense amp (e.g., 206) and/or the memory cells of the array (e.g., 230), which may conform to a particular feature size (e.g., 4F2, 6F2, etc.). As described further below, the compute component 231 can, in conjunction with the sense amp 206, operate to perform various logical operations using data from array 230 as input and store the result back to the array 230 without transferring the data via a sense line address access (e.g., without firing a column decode signal such that data is transferred to circuitry external from the array and sensing circuitry via local I/O lines). As such, a number of embodiments of the present disclosure can enable performing logical operations and computing functions associated therewith using less power than various previous approaches. Additionally, since a number of embodiments eliminate the need to transfer data across local I/O lines in order to perform compute functions, a number of embodiments can enable an increased parallel processing capability as compared to previous approaches.

In the example illustrated in FIG. 2, the circuitry corresponding to compute component 231 comprises five transistors coupled to each of the sense lines D and D_; however, embodiments are not limited to this example. Transistors 207-1 and 207-2 have a first source/drain region coupled to sense lines D and D_, respectively, and a second source/drain region coupled to a cross coupled latch (e.g., coupled to gates of a pair of cross coupled transistors, such as cross coupled NMOS transistors 208-1 and 208-2 and cross coupled PMOS transistors 209-1 and 209-2. As described further herein, the cross coupled latch comprising transistors 208-1, 208-2, 209-1, and 209-2 can be referred to as a secondary latch (the cross coupled latch corresponding to sense amp 206 can be referred to herein as a primary latch).

The transistors 207-1 and 207-2 can be referred to as pass transistors, which can be enabled via respective signals 211-1 (Passd) and 211-2 (Passdb) in order to pass the voltages or currents on the respective sense lines D and Dto the inputs of the cross coupled latch comprising transistors 208-1, 208-2, 209-1, and 209-2 (e.g., the input of the secondary latch). In this example, the second source/drain region of transistor 207-1 is coupled to a first source/drain region of transistors 208-1 and 209-1 as well as to the gates of transistors 208-2 and 209-2. Similarly, the second source/drain region of transistor 207-2 is coupled to a first source/drain region of transistors 208-2 and 209-2 as well as to the gates of transistors 208-1 and 209-1.

A second source/drain region of transistor 208-1 and 208-2 is commonly coupled to a negative control signal 212-1 (Accumb). A second source/drain region of transistors 209-1 and 209-2 is commonly coupled to a positive control signal 212-2 (Accum). The Accum signal 212-2 can be a supply voltage (e.g., Vcc) and the Accumb signal can be a reference voltage (e.g., ground). Enabling signals 212-1 and 212-2 activates the cross coupled latch comprising transistors 208-1, 208-2, 209-1, and 209-2 corresponding to the secondary latch. The activated sense amp pair operates to amplify a differential voltage between common node 217-1 and common node 217-2 such that node 217-1 is driven to one of the Accum signal voltage and the Accumb signal voltage (e.g., to one of Vcc and ground), and node 217-2 is driven to the other of the Accum signal voltage and the Accumb signal voltage. As described further below, the signals 212-1 and 212-2 are labeled “Accum” and “Accumb” because the secondary latch can serve as an accumulator while being used to perform a logical operation. In a number of embodiments, an accumulator comprises the cross coupled transistors 208-1, 208-2, 209-1, and 209-2 forming the secondary latch as well as the pass transistors 207-1 and 208-2. As described further herein, in a number of embodiments, a compute component comprising an accumulator coupled to a sense amplifier can be configured to perform a logical operation that comprises performing an accumulate operation on a data value represented by a signal (e.g., voltage or current) on at least one of a pair of complementary sense lines.

The compute component 231 also includes inverting transistors 214-1 and 214-2 having a first source/drain region coupled to the respective digit lines D and D_. A second source/drain region of the transistors 214-1 and 214-2 is coupled to a first source/drain region of transistors 216-1 and 216-2, respectively. The gates of transistors 214-1 and 214-2 are coupled to a signal 213 (InvD). The gate of transistor 216-1 is coupled to the common node 217-1 to which the gate of transistor 208-2, the gate of transistor 209-2, and the first source/drain region of transistor 208-1 are also coupled. In a complementary fashion, the gate of transistor 216-2 is coupled to the common node 217-2 to which the gate of transistor 208-1, the gate of transistor 209-1, and the first source/drain region of transistor 208-2 are also coupled. As such, enabling signal InvD serves to invert the data value stored in the secondary latch and drives the inverted value onto sense lines 205-1 and 205-2.

In FIG. 2, the compute component 231 is configured to perform an AND, NAND, and/or a NOT (e.g., invert) operation. The following example will demonstrate how a 3-input NAND operation can be performed using data stored in array 230 as the inputs, and how the result of the NAND operation can be stored in the array via operation of the sensing circuitry (e.g., sense amp 206 and compute component 231). The example involves using the data values (e.g., logic 1 or logic 0) stored in the memory cells coupled to word lines 204-0, 204-1, and 204-2 and commonly coupled to sense line 205-1 as the respective inputs of a NAND operation. The result of the NAND operation will be stored in the memory cell coupled to word line 204-3 and to sense line 205-1 (e.g., by overwriting the previous data value stored in the cell).

A first operation phase of the 3-input NAND operation includes performing a sensing operation on the Row0 memory cell using sense amp 206 to determine its stored data value, which serves as a first input of the NAND operation. The sense amp 206 can operate in a similar manner as sense amp 306 described below in association with FIG. 3. The sensing operation involves enabling Row0 (e.g., to activate the access transistor 202) and results in a voltage (e.g., Vcc) corresponding to a logic 1 or a voltage (e.g., ground) corresponding to a logic 0 being on sense line D (and the other voltage being on complementary sense line D_), such that the sensed data value is stored in the primary latch corresponding to sense amp 206. After the Row0 memory cell is sensed, the Passd and Passdb signals 211-1/211-2 are enabled and the Accumb and Accum signals 212-1/212-2 are enabled, which results in the sensed data value stored in the Row0 memory cell being copied to the secondary latch corresponding to compute component 231. The Passd and Passdb signals are then disabled; however, the Accum and Accumb signals remain enabled (during the second, third, and fourth operation phase as described below). Row0 is then disabled and equilibration occurs. As described below in association with FIG. 3, equilibration can involve shorting the complementary sense lines D and Dtogether at an equilibration voltage, which can be Vcc/2, for instance. Equilibration can occur, for instance, prior to a memory cell sensing operation.

A second phase of the 3-input NAND operation includes performing a sensing operation on the Row1 memory cell using sense amp 206 to determine its stored data value, which serves as a second input of the NAND operation. As such, Row1 is enabled and the sense lines D and D_ are each driven to a different one of Vcc and ground. In this example, a Vcc voltage on sense line D corresponds to a logic 1 stored in a memory cell and a ground voltage on sense line D corresponds to a logic 0; however, embodiments are not limited to this example. After the Row1 memory cell is sensed, the Passd signal 211-1 is enabled while the Passdb signal 211-2 remains disabled (e.g., only Passd is enabled). Recall that the Accumb and Accum signals 212-1/212-2 remain enabled. If the data value stored in the Row1 memory cell is a logic 0, then the accumulated value associated with the secondary latch is asserted low such that the secondary latch stores logic 0. If the data value stored in the Row1 memory cell is not a logic 0, then the secondary latch retains its stored Row0 data value (e.g., a logic 1 or a logic 0). As such, in this example, the secondary latch is serving as a zeroes (0s) accumulator. The Passd signal is then disabled, Row1 is disabled, and equilibration occurs.

A third phase of the 3-input NAND operation includes performing a sensing operation on the Row2 memory cell using sense amp 206 to determine its stored data value, which serves as a third input of the NAND operation. As such, Row2 is enabled and the sense lines D and D_ are each driven to a different one of Vcc and ground. After the Row2 memory cell is sensed, the Passd signal 211-1 is enabled while the Passdb signal 211-2 remains disabled (e.g., only Passd is enabled). Recall that the Accumb and Accum signals 212-1/212-2 remain enabled. If the data value stored in the Row2 memory cell is a logic 0, then the accumulated value associated with the secondary latch is asserted low such that the secondary latch stores logic 0. If the data value stored in the Row2 memory cell is not a logic 0, then the secondary latch retains its previously stored value (e.g., its stored value). As such, the value stored in the secondary latch (e.g., the output of the accumulator) is the AND of the data values stored in the respective Row0, Row1, and Row2 memory cells. The Passd signal is then disabled, Row2 is disabled, and equilibration occurs.

The fourth phase of the 3-input NAND operation includes disabling equilibration such that sense lines D and Dare floating. The InvD signal 213 is then enabled, which results in an inverting of the data value stored the secondary latch (e.g., inverting the accumulated output). As such, if any of the memory cells of Row0 to Row2 stored a logic 0 (e.g., if any of the three inputs of the NAND operation were logic 0), then the sense line Dwill carry a voltage corresponding to logic 0 (e.g., ground voltage) and sense line D will carry a voltage corresponding to logic 1 (e.g., Vcc). If all of the memory cells of Row0 to Row2 stored a logic 1 (e.g., all of the three inputs of the NAND operation were logic 1), then the sense line Dwill carry a voltage corresponding to logic 1 and sense line D will carry a voltage corresponding to logic 0. The primary latch of sense amp 206 is then enabled and the sense line D now contains the NANDed result of the respective input data values from the Row0 to Row2 memory cells. As such, sense line D will be at Vcc if any of the Row0 to Row 2 memory cells stored a logic 0 and sense line D will be at ground if all of the Row0 to Row2 memory cells stored a logic 1. The result of the NAND operation is then stored back to a memory cell of array 230. In this example, the result of the NAND operation can be stored to the Row3 memory cell. Storing the result of the NAND operation to the Row3 memory cell simply involves activating the Row3 access transistor 202 by enabling Row3. The capacitor 203 of the Row3 memory cell will be driven to a voltage corresponding to the data value on the sense line D (e.g., logic 1 or logic 0), which essentially overwrites whatever data value was previously stored in the Row3 memory cell. Embodiments are not so limited. For instance, in a number of embodiments, the result of the logical operation may be written to a memory cell other than a memory cell of Row3. For example, the result can be stored back to one of the memory cells that initially stored the data used as inputs of the operation (e.g., to one of cells of Row0, Row1, and Row2). In a number of embodiments, the result of the logical operation may not be stored back to the array. For instance, after performing the logical operation, the result may be transferred from an accumulator (e.g., the accumulator of compute component 231) to an external device (e.g., via local I/O lines coupled to the sense amp).

Although the above example involved a 3-input NAND operation, embodiments are not so limited. For instance, in a number of embodiments, the number of inputs can be equal to the number of rows (e.g., N) associated with a particular array. That is, the same sensing circuitry described in FIG. 2 can be used to perform an N-input NAND function. Sensing circuitry such as that described in FIG. 2 can also enable performance of numerous logical operations in parallel. For instance, in an array may having 16K columns, 16K logical operations can be performed in parallel, without transferring data from the array and sensing circuitry via a bus and/or without transferring data from the array and sensing circuitry via local I/O lines.

Also, one of ordinary skill in the art will appreciate that the ability to perform NAND logical operations can enable performance of more complex computing functions such as addition, subtraction, and multiplication, among other primary math functions and/or pattern compare functions. For example, a series of NAND operations can be combined to perform a full adder function. As an example, if a full adder requires 12 NAND gates to add two data values along with a carry in and carry out, a total of 384 NAND operations (12×32) could be performed to add two 32 bit numbers. Embodiments of the present disclosure can also be used to perform logical operations that may be non-boolean (e.g., copy, compare, etc.) and/or may be more or less complex than a NAND operation.

Additionally, in a number of embodiments, the inputs to a logical operation performed may not be data values stored in the memory array to which the sensing circuitry (e.g., 150) is coupled. For instance, a number of inputs to a logical operation can be sensed by a sense amplifier (e.g., 206) without activating a row of the array (e.g., 230). As an example, the number of inputs can be received by the sense amp 206 via I/O lines coupled thereto (e.g., I/O lines 334-1 and 334-2 shown in FIG. 3). Such inputs may be provided to the sense amp 206 (e.g., via the appropriate I/O lines) from a source external to the array 230 such as from a host processor (e.g., host 110) and/or external controller, for instance. As another example, in association with performing a logical operation, the inputs to a particular sense amp (e.g., 206) and its corresponding compute component (e.g., 231) may be received from a different sense amp/compute component pair. For instance, a data value (e.g., logical result) stored in a first accumulator coupled to a first column of cells may be transferred to a different (e.g., neighboring) sense amp/compute component pair associated with a different column of cells, which may or may not be located in the same array as the first column.

Embodiments of the present disclosure are not limited to the particular sensing circuitry configuration illustrated in FIG. 2. For instance, different compute component circuitry can be used to perform logical operations in accordance with a number of embodiments described herein. Although not illustrated in FIG. 2, in a number of embodiments, control circuitry can be coupled to array 230, sense amp 206, and/or compute component 231. Such control circuitry may be implemented on a same chip as the array and sensing circuitry and/or on an external processing resource such as an external processor, for instance, and can control enabling/disabling various signals corresponding to the array and sensing circuitry in order to perform logical operations as described herein.

FIG. 2B illustrates a timing diagram 285 associated with performing a logical operation using sensing circuitry in accordance with a number of embodiments of the present disclosure. As an example, timing diagram 285 can illustrate a phase of a 3-input NAND operation such as that described above. The timing diagram 285 illustrates voltage signals associated with performing a first phase of a logical operation. As described further below, performing the logical operation phase illustrated in FIG. 2B can involve consuming significantly less energy (e.g., about half) than previous processing approaches, which may involve providing a full swing between voltage rails (e.g., between a supply voltage and ground) to perform a compute function.

In the example illustrated in FIG. 2B, the voltage rails corresponding to complementary logic values (e.g., “1” and “0”) are a supply voltage 274 (VDD) and a ground voltage 272 (Gnd). Prior to performing a logical operation, equilibration can occur such that the complementary sense lines D and Dare shorted together at an equilibration voltage 225 (VDD/2). Equilibration is described further below in association with FIG. 3.

At time t1, the equilibration signal 226 is deactivated, and then a row is activated (e.g., the row corresponding to a memory cell whose data value is to be sensed). Signal 204 represents the voltage signal applied to the selected row. When row signal 204 reaches the threshold voltage (Vt) of the access transistor (e.g., 202) corresponding to the selected cell, the access transistor turns on and couples the sense line D to the selected memory cell (e.g., to the capacitor 203 if the cell is a 1T1C DRAM cell), which creates a differential voltage signal between the sense lines D and D(e.g., as indicated by signals 205-1 and 205-2, respectively) between times t2 and t3. The voltage of the selected cell is represented by signal 203. Due to conservation of energy, creating the differential signal between D and D(e.g., by coupling the cell to D) does not consume energy, since the energy associated with activating/deactivating the row signal 204 can be amortized over the plurality of memory cells coupled to the row.

At time t3, the sense amp fires (e.g., the positive control signal 231 (e.g., PSA 331 shown in FIG. 3) goes high, and the negative control signal 228 (e.g., RNL_ 328) goes low), which amplifies the differential signal. The primary energy consumption occurs in charging the sense line D 205-1 from VDD/2 to VDD.

At time t4, the pass transistor 207-1 and/or 207-2 is activated, depending on the particular logic operation. Since timing diagram 285 is describing a first phase of a NAND operation, both pass transistors 207-1 and 207-2 are activated (as described above, in subsequent phases of a NAND operation only one of the pass transistors (e.g., 207-1) is activated during accumulate operations). At time t5, the accumulator control signals 212-1 (Accumb) and 212-2 (Accum) are activated. As described above, in subsequent phases of a NAND operation, the accumulator control signals 212-1 and 212-2 would already be activated. As such, in this example, activating the control signals 212-1 and 212-2 activates the accumulator. If the accumulator was previously activated, then activating passd 211 results in accumulating the data value corresponding to the voltage signal 205-1.

At time t6, the pass transistors 207-1 and 207-2 are deactivated; however, since the accumulator control signals 212-1 and 212-2 remain activated, an accumulated result is stored (e.g., latched) in the accumulator. At time t7, the row signal 204 is deactivated, and the array sense amps are deactivated at time t8 (e.g., sense amp control signals 228 and 231 are deactivated).

At time t9, the sense lines D and Dare equilibrated (e.g., equilibration signal 226 is activated), as illustrated by sense line voltage signals 205-1 and 205-2 moving from their respective rail values to the equilibration voltage 225 (VDD/2). The equilibration consumes little energy due to the law of conservation of energy.

The example logic operation phase described in association with FIG. 2 involves accumulating a data value (e.g., a data value sensed from a memory cell and/or a data value corresponding to a voltage or current of a sense line). Due to conservation of energy, the energy consumed in performing the logic operation phase is approximately equal to the energy consumed during charging of the capacitance of the sense line D or Dfrom VDD/2 to VDD, which begins at time t3 (e.g., when the sense amp is fired). As such, a logical operation is performed that consumes approximately the energy used to charge a sense line (e.g., digit line) from VDD/2 to VDD. In contrast, various previous processing approaches consume at least an amount of energy used to charge a sense line from rail to rail (e.g., from ground to VDD.

FIG. 3 illustrates a schematic diagram of a portion of sensing circuitry in accordance with a number of embodiments of the present disclosure. In this example, the portion of sensing circuitry comprises a sense amplifier 306. In a number of embodiments, one sense amplifier 306 (e.g., “sense amp”) is provided for each column of memory cells in an array (e.g., array 130). The sense amp 306 can be sense amp of a DRAM array, for instance. In this example, sense amp 306 is coupled to a pair of complementary sense lines 305-1 (“D”) and 305-2 (“D_”). As such, the sense amp 306 is coupled to all of the memory cells in a respective column through sense lines D and D_.

The sense amplifier 306 includes a pair of cross coupled n-channel transistors (e.g., NMOS transistors) 327-1 and 327-2 having their respective sources coupled to a negative control signal 328 (RNL_) and their drains coupled to sense lines D and D_, respectively. The sense amplifier 306 also includes a pair of cross coupled p-channel transistors (e.g., PMOS transistors) 329-1 and 329-2 having their respective sources coupled to a positive control signal 331 (PSA) and their drains coupled to sense lines D and D_, respectively.

The sense amp 306 includes a pair of isolation transistors 321-1 and 321-2 coupled to sense lines D and D_, respectively. The isolation transistors 321-1 and 321-2 are coupled to a control signal 322 (ISO) that, when enabled, activates (e.g., turns on) the transistors 321-1 and 321-2 to connect the sense amp 306 to a column of memory cells. Although not illustrated in FIG. 3, the sense amp 306 may be coupled to a first and a second memory array and can include another pair of isolation transistors coupled to a complementary control signal (e.g., ISO_), which is disabled when ISO is enabled such that the sense amp 306 is isolated from a first array when sense amp 306 is coupled to a second array, and vice versa.

The sense amp 306 also includes circuitry configured to equilibrate the sense lines D and D_. In this example, the equilibration circuitry comprises a transistor 324 having a first source/drain region coupled to an equilibration voltage 325 (dvc2), which can be equal to Vcc/2, where Vcc is a supply voltage associated with the array. A second source/drain region of transistor 324 is coupled to a common first source/drain region of a pair of transistors 323-1 and 323-2. The second source drain regions of transistors 323-1 and 323-2 are coupled to sense lines D and D_, respectively. The gates of transistors 324, 323-1, and 323-2 are coupled to control signal 326 (EQ). As such, enabling EQ activates the transistors 324, 323-1, and 323-2, which effectively shorts sense line D to sense line Dsuch that the sense lines D and Dare equilibrated to equilibration voltage dvc2.

The sense amp 306 also includes transistors 332-1 and 332-2 whose gates are coupled to a signal 333 (COLDEC). Signal 333 may be referred to as a column decode signal or a column select signal. The sense lines D and Dare connected to respective local I/O lines 334-1 (IO) and 334-2 (IO_) responsive to enabling signal 333 (e.g., to perform an operation such as a sense line access in association with a read operation). As such, signal 333 can be enabled to transfer a signal corresponding to the state (e.g., a logic data value such as logic 0 or logic 1) of the memory cell being accessed out of the array on the I/O lines 334-1 and 334-2.

In operation, when a memory cell is being sensed (e.g., read), the voltage on one of the sense lines D, Dwill be slightly greater than the voltage on the other one of sense lines D, D_. The PSA signal is then driven high and the RNL_ signal is driven low to enable the sense amplifier 306. The sense line D, D_ having the lower voltage will turn on one of the PMOS transistor 329-1, 329-2 to a greater extent than the other of PMOS transistor 329-1, 329-2, thereby driving high the sense line D, Dhaving the higher voltage to a greater extent than the other sense line D, Dis driven high. Similarly, the sense line D, Dhaving the higher voltage will turn on one of the NMOS transistor 327-1, 327-2 to a greater extent than the other of the NMOS transistor 327-1, 327-2, thereby driving low the sense line D, Dhaving the lower voltage to a greater extent than the other sense line D, Dis driven low. As a result, after a short delay, the sense line D, Dhaving the slightly greater voltage is driven to the voltage of the PSA signal (which can be the supply voltage Vcc), and the other sense line D, Dis driven to the voltage of the RNL_ signal (which can be a reference potential such as a ground potential). Therefore, the cross coupled NMOS transistors 327-1, 327-2 and PMOS transistors 329-1, 329-2 serve as a sense amp pair, which amplify the differential voltage on the sense lines D and Dand serve to latch a data value sensed from the selected memory cell. As used herein, the cross coupled latch of sense amp 306 may be referred to as a primary latch. In contrast, and as described above in connection with FIG. 2, a cross coupled latch associated with a compute component (e.g., compute component 231 shown in FIG. 2) may be referred to as a secondary latch.

CONCLUSION

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.

Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combination of the above embodiments, and other embodiments not specifically described herein will be apparent to those of skill in the art upon reviewing the above description. The scope of the one or more embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.

In the foregoing Detailed Description, some features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

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Citation

Patents Cited in This Cited by
Title Current Assignee Application Date Publication Date
半導体信号処理装置 ルネサスエレクトロニクス株式会社 16 September 2008 05 November 2009
並列演算処理装置 ルネサスエレクトロニクス株式会社 31 January 2006 16 August 2007
반도체 메모리 장치 삼성전자주식회사 15 June 2009 23 December 2010
반도체 메모리 장치 및 이를 위한 테스트 회로 에스케이하이닉스 주식회사 04 November 2011 14 May 2013
감소 칩 영역을 가진 반도체 메모리 소자 닛본 덴끼 가부시끼가이샤 29 November 1996 02 August 1999
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