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Patent Analysis of

In-memory computational device with bit line processors

Updated Time 12 June 2019

Patent Registration Data

Publication Number

US10153042

Application Number

US15/650935

Application Date

16 July 2017

Publication Date

11 December 2018

Current Assignee

GSI TECHNOLOGY INC.

Original Assignee (Applicant)

GSI TECHNOLOGY INC.

International Classification

G11C7/10,G11C15/04,G11C7/18,G11C8/10,G06F9/30

Cooperative Classification

G11C15/04,G06F9/3016,G11C7/1006,G11C7/18,G11C8/10

Inventor

EHRMAN, ELI,AKERIB, AVIDAN

Patent Images

This patent contains figures and images illustrating the invention and its embodiment.

US10153042 In-memory computational bit 1 US10153042 In-memory computational bit 2 US10153042 In-memory computational bit 3
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Abstract

A computing device includes bit line processors, multiplexers and a decoder. Each bit line processor includes a bit line of memory cells and each cell stores one bit of a data word. A column of bit line processors stores the bits of the data word. Each multiplexer connects a bit line processor in a first row of bit line processors to a bit line processor in a second row of bit line processors. The decoder activates at least two word lines of the bit line processor of the first row and a word line in the bit line processor in the second row and enables a bit line voltage associated with a result of a logical operation performed by the bit line processor in the first row to be written into the cell in the bit line processor in the second row.

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Claims

1. A computing device comprising:

a plurality of bit line processors, each bit line processor comprising a bit line having a cell column of memory cells connected thereto, each said cell in said cell column to store one bit of a data word, a column of said bit line processors to store the bits of said data word and a row of said bit line processors to store a plurality of words; at least one multiplexer to connect a bit line processor in a first row of bit line processors to a bit line processor in a second row of bit line processors; and a decoder to activate at least two word lines of cells of said bit line processor of said first row and a word line connected to a cell in said bit line processor in said second row to write a bit line voltage associated with a result of a logical operation performed by said bit line processor in said first row into said cell in said bit line processor in said second row.

2. A computing device according to claim 1 further comprising a controller to provide said decoder with an instruction set for decoding in said decoder.

3. A computing device according to claim 2 wherein said instruction set is of a small size.

4. A computing device according to claim 3 wherein said instruction set from said controller comprises a maximum size of 64 bits.

5. A computing device according to claim 1 wherein said decoder decompresses said compressed data.

6. A computing device according to claim 1 wherein said memory cells comprise at least one of non-volatile and non-destructive cells.

7. A computing device according to claim 1 wherein said memory cells comprise volatile memory cells.

8. A computing device comprising:

a storage memory array storing data words in columns therein; a plurality of bit line processors organized into sections, each bit line processor comprising a bit line having a cell column of memory cells connected thereto, each said cell in said cell column to store one bit of a data word; and a decoder to activate multiple word lines of said storage memory array for reading multiple rows of data therein and to activate multiple sections of bit line processors, for writing each word line of said multiple word lines into a different section of said bit line processors and each bit of said word line into a different bit line processor.

9. A method of performing in-memory computations in a memory array comprising a plurality of sections having memory cells arranged in rows and column, the method comprising:

having a plurality of bit line processors, each bit line processor comprising a bit line having a cell column of memory cells connected thereto, each said cell in said cell column to store one bit of a data word, a column of said bit line processors to store the bits of said data word and a row of said bit line processors to store a plurality of words; connecting a bit line processor in a first row of bit line processors to a bit line processor in a second row of bit line processors; and activating at least two word lines of cells of said bit line processor of said first row and a word line connected to a cell in said bit line processor in said second row to write a bit line voltage associated with a result of a logical operation performed by said bit line processor in said first row into said cell in said bit line processor in said second row.

10. A method according to claim 9 further comprising decoding an instruction set from a controller into an instruction set comprising a plurality of read and write commands.

11. A method according to claim 10 wherein said instruction set is of a small size.

12. A method according to claim 11 wherein said instruction set from said controller comprises a maximum size of 64 bits.

13. A method according to claim 10 wherein said decoding comprises decompressing compressed data.

14. A method according to claim 9 wherein said memory cells comprise at least one of non-volatile and non-destructive cells.

15. A method according to claim 9 wherein said memory cells comprise volatile memory cells.

16. A method comprising:

storing data words in columns in a memory array; having a plurality of bit line processors organized into sections, each bit line processor comprising a bit line having a cell column of memory cells connected thereto, each said cell in said cell column to store one bit of a data word; activating multiple word lines of said storage memory array for reading multiple rows of data therein; and activating multiple sections of bit line processors for writing each word line of said multiple word lines into a different section of said bit line processors and each bit of said word line into a different bit line processor.

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Claim Tree

  • 1
    1. A computing device comprising:
    • a plurality of bit line processors, each bit line processor comprising a bit line having a cell column of memory cells connected thereto, each said cell in said cell column to store one bit of a data word, a column of said bit line processors to store the bits of said data word and a row of said bit line processors to store a plurality of words
    • at least one multiplexer to connect a bit line processor in a first row of bit line processors to a bit line processor in a second row of bit line processors
    • and a decoder to activate at least two word lines of cells of said bit line processor of said first row and a word line connected to a cell in said bit line processor in said second row to write a bit line voltage associated with a result of a logical operation performed by said bit line processor in said first row into said cell in said bit line processor in said second row.
    • 2. A computing device according to claim 1 further comprising
      • a controller to provide said decoder with an instruction set for decoding in said decoder.
    • 5. A computing device according to claim 1 wherein
      • said decoder decompresses said compressed data.
    • 6. A computing device according to claim 1 wherein
      • said memory cells comprise
    • 7. A computing device according to claim 1 wherein
      • said memory cells comprise
  • 8
    8. A computing device comprising:
    • a storage memory array storing data words in columns therein
    • a plurality of bit line processors organized into sections, each bit line processor comprising a bit line having a cell column of memory cells connected thereto, each said cell in said cell column to store one bit of a data word
    • and a decoder to activate multiple word lines of said storage memory array for reading multiple rows of data therein and to activate multiple sections of bit line processors, for writing each word line of said multiple word lines into a different section of said bit line processors and each bit of said word line into a different bit line processor.
  • 9
    9. A method of performing in-memory computations in a memory array comprising
    • a plurality of sections having memory cells arranged in rows and column, the method comprising: having a plurality of bit line processors, each bit line processor comprising a bit line having a cell column of memory cells connected thereto, each said cell in said cell column to store one bit of a data word, a column of said bit line processors to store the bits of said data word and a row of said bit line processors to store a plurality of words
    • connecting a bit line processor in a first row of bit line processors to a bit line processor in a second row of bit line processors
    • and activating at least two word lines of cells of said bit line processor of said first row and a word line connected to a cell in said bit line processor in said second row to write a bit line voltage associated with a result of a logical operation performed by said bit line processor in said first row into said cell in said bit line processor in said second row.
    • 10. A method according to claim 9 further comprising
      • decoding an instruction set from a controller into an instruction set comprising a plurality of read and write commands.
    • 14. A method according to claim 9 wherein
      • said memory cells comprise
    • 15. A method according to claim 9 wherein
      • said memory cells comprise
  • 16
    16. A method comprising:
    • storing data words in columns in a memory array
    • having a plurality of bit line processors organized into sections, each bit line processor comprising a bit line having a cell column of memory cells connected thereto, each said cell in said cell column to store one bit of a data word
    • activating multiple word lines of said storage memory array for reading multiple rows of data therein
    • and activating multiple sections of bit line processors for writing each word line of said multiple word lines into a different section of said bit line processors and each bit of said word line into a different bit line processor.
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Description

FIELD OF THE INVENTION

The present invention relates to computing devices in general, and more particularly to a device and a method used for search and/or computational operations.

BACKGROUND OF THE INVENTION

Memory arrays, which store large amounts of data, are known in the art. Over the years, manufacturers and designers have worked to make the arrays physically smaller but the amount of data stored therein larger.

Computing devices typically have one or more memory array to store data and a central processing unit (CPU) and other hardware to process the data. The CPU is typically connected to the memory array via a bus. Unfortunately, while CPU speeds have increased tremendously in recent years, the bus speeds have not increased at an equal pace. Accordingly, the bus connection acts as a bottleneck to increased speed of operation.

U.S. Pat. No. 8,238,173 to Akerib et al. and assigned to the common assignee of the present invention discloses a processor which may perform in-memory computations. The processor includes a memory array to store data, and an activation unit to activate at least two cells in a column of the memory array at generally the same time to generate a Boolean function output of the data of the at least two cells. The Boolean function output may then be stored inside the memory array for further processing, including to generate new Boolean function outputs. This operation may be repeated numerous times until the desired results are achieved. The results may then be output for further use. Also disclosed therein is a content addressable memory (CAM) unit, including a ternary CAM (T-CAM) unit which may be implemented using the principles of operation of the in-memory processor.

SUMMARY OF THE PRESENT INVENTION

There is provided, in accordance with a preferred embodiment of the present invention, a computing device including a plurality of bit line processors, at least one multiplexer and a decoder. Each bit line processor includes a bit line having a cell column of memory cells connected thereto. Each cell in the cell column stores one bit of a data word and a column of bit line processors stores the bits of the data word. A row of bit line processors stores a plurality of words. Each multiplexer connects a bit line processor in a first row of bit line processors to a bit line processor in a second row of bit line processors. The decoder activates at least two word lines of cells of the bit line processor of the first row and a word line connected to a cell in the bit line processor in the second row such that a bit line voltage associated with a result of a logical operation performed by the bit line processor in the first row is written into the cell in the bit line processor in the second row.

Moreover, in accordance with a preferred embodiment of the present invention, the computing device further includes a controller to provide the decoder with an instruction set for decoding in the decoder.

Further, in accordance with a preferred embodiment of the present invention, the instruction set is of a small size. For example, the instruction set includes a maximum size of 64 bits.

Still further, in accordance with a preferred embodiment of the present invention, the decoder decompresses the compressed data.

Additionally, in accordance with a preferred embodiment of the present invention, the memory cells include non-destructive cells or volatile memory cells.

There is also provided, in accordance with a preferred embodiment of the present invention, a computing device including a storage memory array storing data words in columns therein, a plurality of bit line processors organized into sections, and a decoder. Each bit line processor includes a bit line having a cell column of memory cells connected thereto and each cell in the cell column stores one bit of a data word. The decoder activates multiple word lines of the storage memory array for reading multiple rows of data therein and multiple sections of bit line processors, for writing the multiple word lines, each word line into a different section of the bit line processors and each bit of the word line into a different bit line processor.

There is also provided, in accordance with a preferred embodiment of the present invention, a method of performing in-memory computations in a memory array including a plurality of sections having memory cells arranged in rows and column. The method includes having a plurality of bit line processors, each bit line processor including a bit line having a cell column of memory cells connected thereto, each the cell in the cell column to store one bit of a data word, a column of the bit line processors to store the bits of the data word and a row of the bit line processors to store a plurality of words, connecting a bit line processor in a first row of bit line processors to a bit line processor in a second row of bit line processors, and activating at least two word lines of cells of the bit line processor of the first row and a word line connected to a cell in the bit line processor in the second row to write a bit line voltage associated with a result of a logical operation performed by the bit line processor in the first row into the cell in the bit line processor in the second row.

Moreover, in accordance with a preferred embodiment of the present invention, the method further includes decoding an instruction set from a controller into an instruction set including a plurality of read and write commands.

Further, in accordance with a preferred embodiment of the present invention, the instruction set is of a small size. For example, the instruction set from the controller includes a maximum size of 64 bits.

Still further, in accordance with a preferred embodiment of the present invention, the decoding includes decompressing compressed data.

There is also provided, in accordance with a preferred embodiment of the present invention, a method including storing data words in columns in a memory array, having a plurality of bit line processors organized into sections, each bit line processor including a bit line having a cell column of memory cells connected thereto, each the cell in the cell column to store one bit of a data word, and activating multiple word lines of the storage memory array for reading multiple rows of data therein and multiple sections of bit line processors, for writing the multiple word lines, each word line into a different section of the bit line processors and each bit of the word line into a different bit line processor.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings in which:

FIG. 1 schematically illustrates an exemplary in-memory computational device, according to an embodiment of the present invention;

FIG. 2 schematically illustrates a section of an MLB in FIG. 1 including two exemplary MLB data sections interconnected by a multiplexer, according to an embodiment of the present invention;

FIG. 3 schematically illustrates an exemplary arrangement of memory cells in rows and columns in a decoder shown in FIG. 1, according to an embodiment of the present invention;

FIG. 4 schematically illustrates an exemplary in-memory computational device suitable for big data processing, according to an embodiment of the present invention;

FIG. 5 schematically illustrates an exemplary in-memory computational device providing separate bit-line processors; and

FIG. 6 schematically illustrates a memory array divided into a storage memory array above an associative memory array, according to an embodiment of the present invention.

It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, and components have not been described in detail so as not to obscure the present invention.

Applicants have realized that the performance of devices which use in-memory computations may be vastly improved by dividing the device's memory into blocks of memory cells which may be individually accessed and which in parallel may carry out different operations. Applicants have additionally realized that performance may be further improved by using the results of the operations carried out in a memory logic block (MLB), as a block of memory cells will be referred to hereinafter, in other MLBs to perform other operations, without first having to output the result of each operation and rewriting them into memory for use by the other MLBs Only when the desired final result is obtained is the data output from memory.

Applicants have realized that an in-memory computational device which can perform in-memory computations as described above may require a decoder which can decode controller instruction sets in known size formats (8 bit, 16 bit, 32 bit, 64 bit, etc.) into an instruction set of hundreds and even thousands of bits with which to access, in parallel, the numerous number of rows of cells in the MLBs. In effect, the decoder should be able to decode the “small size” controller instructions which may represent compressed code into decompressed “large size” read/write instructions to activate the MLB cells.

It may be appreciated that an in-memory computational device as described above, which may execute a multiplicity of different operations in parallel, may operate as a MIMD (multiple instructions, multiple data) machine. It may be further appreciated that the in-memory computational device may also operate as an SIMD (single instruction, multiple data) machine, the selection to operate as a MIMD or a SIMD defined in the controller instructions.

It may also be appreciated that an in-memory computational device as described above may find numerous applications in diverse field which may require search and/or compute operations. These may include database and storage applications including distributed storage and cloud storage, signal processing including image and audio processing, biometrics, data compression, communications network switching, caching applications, among many others, some of which may include CAM and T-CAM operations.

Reference is made to FIG. 1 which schematically illustrates an exemplary in-memory computational device 100, according to an embodiment of the present invention. Device 100 may include a memory logic block (MLB) 102, a decoder 104, a code storage unit 106, a controller 108, and a data line buffer 110.

MLB 102 may include a plurality of MLB data sections 114, shown in the figure as MLB DATA SECTION 0 to MLB DATA SECTION K, and a plurality of multiplexer units (MUX) 116, each multiplexer unit interconnecting two MLB data sections 114 located one above the other. MLB 102 may include any number of MLB data sections 114, the number generally limited by physical constraints associated with chip design, or by electrical constraints associated with the operation of sensing circuitry and/or driver circuitry, among other possible constraints. Applicants have determined that between 16 to 64 MLB data sections 114 may be used satisfactorily in MLB 102, although operation with lesser or greater numbers of MLB data sections may still be satisfactory.

Reference is now also made to FIG. 2, which schematically illustrates a section of MLB 102 including two exemplary MLB data sections 114 (designated 114A and 114B respectively in the figure) interconnected by MUX 116, according to an embodiment of the present invention. As may be appreciated from the figure, MLB data sections 114A and 114B each include a plurality of memory cells 150 arranged in M rows and N columns. The number of cells in each row and in each column, as previously described with reference to MLB 102, may generally be limited by physical constraints associated with chip design, or by electrical constraints which may be associated with sensing circuitry, precharge circuitry and/or driver circuitry operation, among other possible constraints. Applicants have determined that 16 memory cells may be used satisfactorily in each MLB data section 114, although operation with lesser or greater numbers of cells may still be satisfactory.

The architecture of MLB 102, including MLB data section 114A and 114B, may resemble that of a NOR-type memory array (for NOR Boolean operations), or alternatively, that of a NAND-type memory array (for NAND Boolean operations). It is well known that NOR functions may be combined to generate the same results as NAND functions, and the inverse. Therefore, with reference to the present invention, Applicants understand that the skilled person practicing the invention may use either type of architecture.

Cells 150 may each be identified by the word “CELL” followed by the row and column in which it is located in the MLB data section. For example, cells 150 in the first row and located in the 1 to Nth column are designated CELL 11, CELL 12 CELL 13 to CELL 1N respectively. Similarly cells 150 located in the second row and third row, as shown, are designated CELL 21, CELL 22, CELL 23, to CELL 2N, and CELL 31, CELL 32, CELL 33, to CELL 3N, respectively. Cells 150 in the Mth row are designated CELL M1, CELL M2, CELL M3, to CELL MN respectively.

Each cell 150 in a row may be connected to a read word line 158 (RE) and a write word line 160 (WE) through which each cell in the row may be activated for reading and writing respectively. Each cell 150 in a column may be connected to a bit line 156.

Cells 150 may include volatile memory cells or non-destructive (non-volatile) memory cells, or a combination of both. The volatile memory cells may be implemented using SRAM or DRAM technologies or other volatile memory technologies. The non-destructive cells may be implemented using non-volatile memory (NVM) technologies such as ReRAM, MRAM, STT-RAM, T-RAM, PC-RAM, nvSRAM, SONOS, Z-RAM, FeRAM, NRAM, among other NVM technologies and memristor technologies known in the art, or which may be under development, or yet to be developed, and may also include flash memory technologies (e.g. floating gate, etc.).

MUX 116 may connect bit line 156 in a column of an MLB data section 114 with bit lines 156 of one or more columns in the MLB data section above or below. In one embodiment, MUX 116 may connect bit line 156 in one column to a bit line in one of three columns in the section above or below, although it may be appreciated that the number of bit line connections varies with the design of MUX 116, and may include less than or more than three connection. The columns to which bit line 156 may connect through MUX 116 may include that directly above, or below, the bit line, and the adjacent column on each side. For example, MUX 116 may connect cell column 162 in MLB data section 114A with cell columns 164, 166, and 168. Through MUX 116, a voltage charge (data) on bit line 156 in cell column 162 may be transferred to bit line 156 in any one of columns 164, 166, 168, or the inverse.

It may be appreciated that MUXs 116 may be used to transfer data between MBL data sections 114 within a same MBL or different MBLs (in devices with multiple MBLs shown in FIG. 4), or both, without having to output the data from memory and rewriting into memory. That is, by activating one or more MUXs 116, the data result of an operation performed in a column, may be transferred from the column in one MLB data section to one or more columns in other MLB data sections in the same MLB or other MLBs. As an example, to write the result of a NAND or NOR operation performed in column 168 in MLB data section 114B to cell CELL 32 (column 162) in MLB data section 114A, MUX 116 connects (responsive to a command) bit line 156 in column 162 to bit line 156 in column 168 so that the two bit lines are now at substantially the same potential (a logical “0” or “1”). Write word line 160 connecting to CELL 32 in MLB data section 114A is activated (write enabled) and the data on bit line 156 is written into CELL 32. The data written into C32 CELL 32 in MLB data section 114A 114A may be used to perform a Boolean operation in column 168.

MUXs 116 may also be used to distribute data arriving from a host connected to device 100 through data line buffer 110 to memory cells 150. Additionally, MUXs 116 may be used to direct output data results through MLB data sections 114 to data line buffer 110, and therefrom to the host.

Decoder 104 may receive instructions sets in known size formats (e.g. 8 bit, 16 bit, 32 bit, 64 bit) from controller 108 and may decode the instructions into an instruction set of hundreds or thousands, and possibly tens of thousands, read and write instructions, and MUX 116 operation instructions. The instructions generated by decoder 104 may be applied, in parallel, to the rows of cells 150, and to MUXs 116, in MLB 102.

Decoder 104 may be implemented in a NOR-type memory array, or alternatively a NAND-type memory array, and may be able to perform in-memory computations including generation and combination of NOR and NAND Boolean functions. Decoder 104 may additionally use results of operations without having to output the results and rewrite them into the decoder. The output results may be the instructions to MLB 102. In some embodiments, the architecture of decoder 104 may resemble that of an MLB 102, and may be divided into sections resembling a MLB data section 114. Multiplexers may be included, but may not be necessary, and may depend on the number of rows of cells in the decoder.

Reference is now also made to FIG. 3 which schematically illustrates an exemplary arrangement of memory cells 150 in rows 170 and columns 172 in decoder 104, according to an embodiment of the present invention.

Decoder read and write instructions and MUX control signals are output from the decoder through bit lines 174 in each column, one bit line for every read word line 158, one for every write word line 160, and one for every MUX control line 117, in MLB 102. Therefore, a minimum number of columns 172 required may be determined by the following equation:

COL=2*CM*K+K*L;

where COL=number of columns 172, CM=number of cells in an MLB data section 114 (multiplied by 2, one bit line for read word line 158, and one bit line for write word line 160), K=number of MLB data sections in MLB 102, and L=number of multiplexed columns per bit line. Other columns 172 may be required to provide for additional bit lines 174 as may be required for other operations, for example, for MLB 102 data input/output through data line buffer 110, which may require a multiplexer to connect the buffer to the first MLB data section (i.e. K*L may be replaced by (K+1)*L).

For example, assuming that MLB 102 has 64 MLB data sections 102 and each MLB data section has 16 cells 150 in each column, each MUX 116 connects multiplexes 3 columns to every column, then:

COL=2*16*64+64*3=2115;

that is, at least 2115 columns 172 are required in decoder 104 to connect to MLB 102, and 2018 if a multiplexer is to be used to connect data line buffer 110 to MLB data section 0.

As may be appreciated from the figure, cell rows 170 and columns 172 in decoder 104 may be oriented perpendicularly to cell rows 176 and columns 178 in MLB 102 to facilitate the connection between the bit line outputs from the decoder with the input lines (read word lines 158, write word lines 160, and MUX control lines 117). This may be potentially advantageous in the design of the layout of the chip of device 100 as decoder 104 may be placed at substantially a right angle (90°) to MLB 102, possibly reducing space requirements.

The instructions from controller 108 may activate read and write lines (not shown) connecting cells 150 in rows 170. Responsive to the activation of the read and write lines, similarly to MLB 102, Boolean operations may be performed in columns 172 and the results stored in cells 150 of other columns 172 for performing other Boolean operations. Only the desired final result, which may be the instruction set for MLB 102, may be output.

A number of rows 170 in decoder 104 may correspond to, but not be limited to, the width of the bus of controller 108, but may be more or less. For example, if the width of the bus is 64 bits, then the number of rows 170 may also be 64 rows, although it may also be 32 rows. Alternatively, if the width of the bus is 32 bits, the number of rows 170 may be 64 rows. Whichever may be the case, decoder 104 may include suitable firmware including appropriate buffering as may be required to transfer the controller instructions into the decoder.

As previously mentioned, decoder 104 may be able to perform in-memory computations including generation of NAND and/or NOR Boolean functions, and may use results of operations without having to output the results and rewrite them into the decoder. The instruction sets from controller 108 may represent compressed data stored in code storage unit 106, and may be delivered to the decoder every clock cycle. The compressed data may include low level instructions which may specify how to perform Boolean operations, including NAND and/or NOR operations, the order of performing the operations, in which MLB data section to execute the operations, which MLB data section results are combined in which cycle, which MLB data section results are to be multiplexed, among other instructions for performing in-memory computations in MLB 102 to generate the desired output results.

It may be appreciated that decoder 104 decompresses the compressed data received from code storage unit 106 through controller 108 every clock cycle, converting the controller instruction sets of relatively small size into a much larger instruction set of decoded read/write instructions and MUX control instructions which are delivered in parallel to MLB 102. Each decoded instruction set may be delivered to MLB 102 in every clock cycle. It may be appreciated that a decoder which may receive small size controller instructions every clock cycle and may also output large set decoded instructions every clock cycle may be potentially advantageous as relatively little memory is required. For example, in the art, a function that requires 100 cycles to complete would require memory space to store approximately 20K signals (assuming approximately 2000 word lines in the MLB) The decoder of the present invention solves this problem as the required memory space may be that required to perform the computational operations to decompress the compressed code data.

Reference is now made to FIG. 4 which schematically illustrates an exemplary in-memory computational device 200, according to an embodiment of the present invention. Device 200 includes an MLB block 202 including a plurality of MLBs 102, a decoder block 204, code storage unit 106, controller 108, and data lines buffer 210. Device 200 may be functionally similar to device 100 shown in FIG. 1 and may also be suitable for performing big data search and computational operations in MLB block 202. Decoder 204 and data lines buffer 210 are functionally similar to decoder 104 and data line buffer 110 shown in FIG. 1 but may be scaled in size to enable manipulation and processing of the big data.

From the above discussion, it may be further appreciated that a small MIMD machine may be implemented in device 100 where many different operations may be carried out in parallel in MLB 102 by simultaneously providing different read and write instructions to the plurality of MLB data sections 114 (and by activating MUXs 116 accordingly so that the results of column operations in one MLB data section may be used in the operations of other MLB data sections. A larger MIMD machine may be implemented in device 200 by providing the different read and write instructions to the plurality of MLBs 102 and activating the MUXs accordingly. Furthermore, a small MIMD machine may be implemented in device 100 by simultaneously providing the same read and write instructions to the plurality of MLB data sections 114, and activating MUXs 116 accordingly. A large SIMD machine may be implemented in device 200 by providing the same read and write instructions to a plurality of MLBs 102 and activating MUXs 116 accordingly.

Applicants have realized that the architecture described hereinabove may be utilized to provide multiple “bit-line” processors, where each bit line in each section may implement a separate bit line processor. This is shown in FIG. 5, to which reference is now made.

FIG. 5 shows how data may be stored and processed in the in-memory computational device of FIG. 1. A data word is typically 16 or 32 bits long. In accordance with a preferred embodiment of the present invention, each bit of a word to be processed may be stored in a separate section 114. Furthermore, in accordance with a preferred embodiment of the present invention, the bits of a single word are typically stored in an aligned column of sections 114, one on top of another.

FIG. 5 shows 6 exemplary 2-bit words to be stored, A, B, Q, R, X and Y. Bits A1 and B1 may be stored in section 114A, along bit line 156 while bits A2 and B2 may be stored in section 114B along bit line 158. Bits Q1 and R1 may be stored in section 114A along bit line 170 while bits Q2 and R2 may be stored in section 114B along bit line 172. Bits X1 and y1 may be stored in section 114A along bit line 174 while bits X2 and Y2 may be stored in section 114B along bit line 176.

Typically, for an M bit word, there may be M sections, each storing a different bit of the word. Each section may have a significant number N, such as 2048, of bit lines and thus, of bit line processors. Each section may provide a row of bit line processors. Thus, N M-bit words may be processed in parallel, where each bit may be processed by separate bit line processors, in parallel.

A typical cell column, such as cell column 150, may store the input data to be processed in the first few cells of the column. In FIG. 5, the bits of words A, Q and X are stored in the first cells of the columns while the bits of words B, R and Y are stored in the second cells of the columns. In accordance with a preferred embodiment of the present invention, the remaining cells in each column (there may be 20-30 cells in a column) may be left as temporary storage for use during the processing operation.

The multiplexers may connect the rows of bit line processors and the decoder may activate the appropriate cells in each bit line processor. As described hereinabove, a row of cells in the memory array are connected by word lines and thus, the decoder may activate the relevant word lines of cells of bit line processors for reading and the relevant word line in a different set of bit line processors for writing.

Applicant has realized that, since each section operates on a row of the same bit of different data words, data may be copied to and from each section in parallel. Reference is now made to FIG. 6, which illustrates a memory array 660 divided into a storage memory array 610 above an associative memory array 640, which may implement MLB blocks 102 or 202. Data to be processed may be copied from memory array 660 into associative memory array 640 and the resultant data may be provided as output or may be copied back into memory array 660. It will be appreciated that the flow of data may be fast since the two sections share the same global bit lines.

In accordance with a preferred embodiment of the present invention, data words may be stored in storage memory array 610 in columns, similar to the storage style in associative memory array 640, as described hereinabove. Furthermore, as discussed hereinabove, each bit of a data word may be copied into a different section. Thus, in accordance with a preferred embodiment of the present invention, each row of storage memory array 610, which may store the same bit of a large set of data words, may be copied into a single row of a section.

Applicant has realized, that, since a row of storage memory array 610 is copied into a section of associative memory array 640, and since the copy to one section does not affect the copy to a different section, multiple rows may be copied from storage memory array 610 to associative memory array 640 at one time. Thus, copying data from storage memory array 610 to associative memory array 640 may be more efficient than in the prior art.

Any appropriate decoder, such as decoder 204, may be utilized to perform the copy from storage memory array 610 to associative memory array 640. In this embodiment, decoder 204 may activate the relevant word lines of storage memory array 610 where the bits to be copied are stored and the relevant word lines of the sections in associative memory array 640 where the bits are to be processed. An appropriate controller, such as controller 108 may provide the appropriate voltages on the receiving bit lines, as described in more detail hereinabove with respect to FIG. 4.

While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.

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Citation

Patents Cited in This Cited by
Title Current Assignee Application Date Publication Date
Transfer of non-associated information on flash memory devices MONTEREY RESEARCH, LLC 30 April 2007 17 March 2009
High performance gain cell architecture INTERNATIONAL BUSINESS MACHINES CORPORATION 26 June 2003 18 January 2005
Dynamic multi-Vcc scheme for SRAM cell stability control INTEL CORPORATION 27 September 2004 18 July 2006
Semiconductor memory device for high speed data access HYNIX SEMICONDUCTOR, INC. 25 June 2004 08 August 2006
Semiconductor memory device with reduced data access time HYNIX SEMICONDUCTOR INC. 28 October 2003 30 August 2005
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US10153042 In-memory computational bit 1 US10153042 In-memory computational bit 2 US10153042 In-memory computational bit 3