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Patent Analysis of

Metal oxide layered structure and methods of forming the same

Updated Time 12 June 2019

Patent Registration Data

Publication Number

US10153175

Application Number

US14/697380

Application Date

27 April 2015

Publication Date

11 December 2018

Current Assignee

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Original Assignee (Applicant)

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

International Classification

H01L23/498,H01L21/768,H01L21/321,H01L23/00,H01L25/10

Cooperative Classification

H01L21/321,H01L21/56,H01L21/563,H01L21/76832,H01L21/76834

Inventor

LIN, JING-CHENG,HUANG, CHENG-LIN

Patent Images

This patent contains figures and images illustrating the invention and its embodiment.

US10153175 Metal oxide layered structure 1 US10153175 Metal oxide layered structure 2 US10153175 Metal oxide layered structure 3
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Abstract

Some embodiment structures and methods are described. A structure includes an integrated circuit die at least laterally encapsulated by an encapsulant, and a redistribution structure on the integrated circuit die and encapsulant. The redistribution structure is electrically coupled to the integrated circuit die. The redistribution structure includes a first dielectric layer on at least the encapsulant, a metallization pattern on the first dielectric layer, a metal oxide layered structure on the metallization pattern, and a second dielectric layer on the first dielectric layer and the metallization pattern. The metal oxide layered structure includes a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, and a thickness of the metal oxide layered structure is at least 50 Å. The second dielectric layer is a photo-sensitive material. The metal oxide layered structure is disposed between the metallization pattern and the second dielectric layer.

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Claims

1. A structure comprising:

an integrated circuit die at least laterally encapsulated by an encapsulant; anda redistribution structure on the integrated circuit die and encapsulant, the redistribution structure being electrically coupled to the integrated circuit die, the redistribution structure comprising:

a first dielectric layer on at least the encapsulant, a metallization pattern on the first dielectric layer, a metal oxide layered structure on the metallization pattern, the metal oxide layered structure comprising a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, a thickness of the metal oxide layered structure being at least 50 Å, and a second dielectric layer on the first dielectric layer and the metallization pattern, the second dielectric layer being a photo-sensitive material, the metal oxide layered structure being disposed between the metallization pattern and the second dielectric layer.

2. The structure of claim 1, wherein the metal oxide layered structure consists essentially of the metal oxide layer, the metal oxide layer directly adjoining the metallization pattern.

3. The structure of claim 1, wherein the metal oxide layered structure further comprises a native oxide layer, the native oxide layer directly adjoining the metallization pattern, the metal oxide layer directly adjoining the native oxide layer.

4. The structure of claim 1, wherein the metal oxide layered structure further comprises a native oxide layer, the metal oxide layer directly adjoining the metallization pattern, the native oxide layer directly adjoining the metal oxide layer.

5. The structure of claim 1, wherein the thickness is not more than 200 Å.

6. The structure of claim 1, wherein the thickness is not more than 100 Å.

7. The structure of claim 1, wherein a thickness of the metal oxide layer is in a range from 50 Å to 200 Å.

8. The structure of claim 1, wherein a thickness of the metal oxide layer is in a range from 50 Å to 100 Å.

9. A structure comprising:

an integrated circuit die; an encapsulant at least laterally encapsulating the integrated circuit die; a first dielectric layer on the encapsulant and an active side of the integrated circuit die; a metallization pattern on the first dielectric layer, the metallization pattern being electrically coupled to the active side of the integrated circuit die; an adhesion layer on the metallization pattern, the adhesion layer comprising a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, a thickness of the adhesion layer being at least 50 Å; and a second dielectric layer on the first dielectric layer and the adhesion layer, the second dielectric layer being a photo-sensitive material.

10. The structure of claim 9, wherein the metal oxide layer directly adjoins the metallization pattern.

11. The structure of claim 9, wherein the adhesion layer further comprises a native oxide layer, the native oxide layer directly adjoining the metallization pattern, the metal oxide layer directly adjoining the native oxide layer.

12. The structure of claim 9, wherein the thickness is not more than 200 Å.

13. The structure of claim 9, wherein the thickness is not more than 100 Å.

14. The structure of claim 9, wherein a thickness of the metal oxide layer is in a range from 50 Å to 200 Å.

15. The structure of claim 9, wherein a thickness of the metal oxide layer is in a range from 50 Å to 100 Å.

16. A structure comprising:

an encapsulant; a semiconductor die within the encapsulant; a through via extending from a first side of the encapsulant to a second side of the encapsulant opposite the first side; a first redistribution layer adjacent to the first side and in electrical connection with the through via, the first redistribution layer comprising a first metal oxide layer with a first thickness of at least 50 {acute over (Å)}, the first metal oxide layer comprising a first metal oxide with a first ratio of first metal atoms to oxygen atoms that is substantially 1:1; and a second redistribution layer adjacent to the second side and in electrical connection with the through via, the second redistribution layer comprising a second metal oxide layer with a second thickness of at least 50 {acute over (Å)}, the second metal oxide layer comprising a second metal oxide with a second ratio of second metal atoms to oxygen atoms that is substantially 1:1.

17. The structure of claim 16, further comprising a package in electrical connection with the through via through the first redistribution layer.

18. The structure of claim 17, wherein the package is a memory package.

19. The structure of claim 16, wherein the first thickness is no greater than 100 {acute over (Å)}.

20. The structure of claim 16, wherein the first thickness is no greater than 200 {acute over (Å)}.

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Claim Tree

  • 1
    1. A structure comprising:
    • an integrated circuit die at least laterally encapsulated by an encapsulant
    • anda redistribution structure on the integrated circuit die and encapsulant, the redistribution structure being electrically coupled to the integrated circuit die, the redistribution structure comprising: a first dielectric layer on at least the encapsulant, a metallization pattern on the first dielectric layer, a metal oxide layered structure on the metallization pattern, the metal oxide layered structure comprising a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, a thickness of the metal oxide layered structure being at least 50 Å, and a second dielectric layer on the first dielectric layer and the metallization pattern, the second dielectric layer being a photo-sensitive material, the metal oxide layered structure being disposed between the metallization pattern and the second dielectric layer.
    • 2. The structure of claim 1, wherein
      • the metal oxide layered structure consists essentially of the metal oxide layer, the metal oxide layer directly adjoining the metallization pattern.
    • 3. The structure of claim 1, wherein
      • the metal oxide layered structure further comprises
    • 4. The structure of claim 1, wherein
      • the metal oxide layered structure further comprises
    • 5. The structure of claim 1, wherein
      • the thickness is not more than 200 Å.
    • 6. The structure of claim 1, wherein
      • the thickness is not more than 100 Å.
    • 7. The structure of claim 1, wherein
      • a thickness of the metal oxide layer is in a range from 50 Å to 200 Å.
    • 8. The structure of claim 1, wherein
      • a thickness of the metal oxide layer is in a range from 50 Å to 100 Å.
  • 9
    9. A structure comprising:
    • an integrated circuit die
    • an encapsulant at least laterally encapsulating the integrated circuit die
    • a first dielectric layer on the encapsulant and an active side of the integrated circuit die
    • a metallization pattern on the first dielectric layer, the metallization pattern being electrically coupled to the active side of the integrated circuit die
    • an adhesion layer on the metallization pattern, the adhesion layer comprising a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, a thickness of the adhesion layer being at least 50 Å
    • and a second dielectric layer on the first dielectric layer and the adhesion layer, the second dielectric layer being a photo-sensitive material.
    • 10. The structure of claim 9, wherein
      • the metal oxide layer directly adjoins the metallization pattern.
    • 11. The structure of claim 9, wherein
      • the adhesion layer further comprises
    • 12. The structure of claim 9, wherein
      • the thickness is not more than 200 Å.
    • 13. The structure of claim 9, wherein
      • the thickness is not more than 100 Å.
    • 14. The structure of claim 9, wherein
      • a thickness of the metal oxide layer is in a range from 50 Å to 200 Å.
    • 15. The structure of claim 9, wherein
      • a thickness of the metal oxide layer is in a range from 50 Å to 100 Å.
  • 16
    16. A structure comprising:
    • an encapsulant
    • a semiconductor die within the encapsulant
    • a through via extending from a first side of the encapsulant to a second side of the encapsulant opposite the first side
    • a first redistribution layer adjacent to the first side and in electrical connection with the through via, the first redistribution layer comprising a first metal oxide layer with a first thickness of at least 50 {acute over (Å)}, the first metal oxide layer comprising a first metal oxide with a first ratio of first metal atoms to oxygen atoms that is substantially 1:1
    • and a second redistribution layer adjacent to the second side and in electrical connection with the through via, the second redistribution layer comprising a second metal oxide layer with a second thickness of at least 50 {acute over (Å)}, the second metal oxide layer comprising a second metal oxide with a second ratio of second metal atoms to oxygen atoms that is substantially 1:1.
    • 17. The structure of claim 16, further comprising
      • a package in electrical connection with the through via through the first redistribution layer.
    • 19. The structure of claim 16, wherein
      • the first thickness is no greater than 100 {acute over (Å)}.
    • 20. The structure of claim 16, wherein
      • the first thickness is no greater than 200 {acute over (Å)}.
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Description

BACKGROUND

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. Dozens or hundreds of integrated circuits are typically manufactured on a single semiconductor wafer. The individual dies are singulated by sawing the integrated circuits along a scribe line. The individual dies are then packaged separately, in multi-chip modules, or in other types of packaging, for example.

The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. These smaller electronic components such as integrated circuit dies may also require smaller packages that utilize less area than packages of the past, in some applications.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIGS. 1 through 3 are cross sectional views of general aspects of intermediate steps during processing in accordance with some embodiments.

FIGS. 4A and 4B are a first example metal oxide layered structure and a method of forming the metal oxide layered structure in accordance with some embodiments.

FIGS. 5A and 5B are a second example metal oxide layered structure and a method of forming the metal oxide layered structure in accordance with some embodiments.

FIGS. 6A and 6B are a third example metal oxide layered structure and a method of forming the metal oxide layered structure in accordance with some embodiments.

FIGS. 7A and 7B are a fourth example metal oxide layered structure and a method of forming the metal oxide layered structure in accordance with some embodiments.

FIGS. 8A and 8B are a fifth example metal oxide layered structure and a method of forming the metal oxide layered structure in accordance with some embodiments.

FIGS. 9 through 23 are cross sectional views of intermediate steps during a process for forming a chip-on-package (CoP) and/or a package-on-package (PoP) structure in accordance with some embodiments.

FIG. 24 is a CoP structure in accordance with some embodiments.

FIG. 25 is a first PoP structure in accordance with some embodiments.

FIG. 26 is a second PoP structure in accordance with some embodiments.

FIG. 27 is a third PoP structure in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,”“below,”“lower,”“above,”“upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Similarly, terms such as “front side” and “back side” may be used herein to more easily identify various components, and may identify that those components are, for example, on opposing sides of another component. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Embodiments discussed herein may be discussed in a specific context, namely a fan-out or fan-in wafer-level package, such as used in a chip-on-package (CoP) and/or package-on-package (PoP) structure. Other embodiments contemplate other applications, such as different package types or different configurations that would be readily apparent to a person of ordinary skill in the art upon reading this disclosure. It should be noted that embodiments discussed herein may not necessarily illustrate every component or feature that may be present in a structure. For example, multiples of a component may be omitted from a figure, such as when discussion of one of the component may be sufficient to convey aspects of the embodiment. Further, method embodiments discussed herein may be discussed as being performed in a particular order; however, other method embodiments may be performed in any logical order.

FIGS. 1 through 3 illustrate cross sectional views of general aspects of intermediate steps during processing in accordance with some embodiments. FIG. 1 illustrates a first dielectric layer 30, a metallization pattern 32 on the first dielectric layer 30, and a native oxide 34 on the metallization pattern 32. In some embodiments, the first dielectric layer 30 is formed of a polymer, which may be a photo-sensitive material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. The first dielectric layer 30 may be formed by any acceptable deposition process, such as spin coating, laminating, the like, or a combination thereof, on any supporting substrate, some examples of which are described in the context of subsequent figures.

As an example to form metallization pattern 32, a seed layer (not shown) is formed on the first dielectric layer 30. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD), sputtering, or the like. A photo resist is then formed and patterned on the seed layer. The photo resist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photo resist corresponds to the metallization pattern 32. The patterning forms openings through the photo resist to expose the seed layer. A metal is formed in the openings of the photo resist and on the exposed portions of the seed layer. The metal may be formed by plating, such as electroplating or electroless plating, or the like. The metal may be copper, nickel, cobalt, titanium, tungsten, aluminum, or the like. Then, the photo resist and portions of the seed layer on which the metal is not formed are removed. The photo resist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photo resist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and metal form the metallization pattern 32.

The native oxide 34 can be formed by the metal of the metallization pattern 32 reacting with oxygen in an ambient environment. For example, the native oxide 34 can be formed by a reaction between the metal and water, hydrogen peroxide, or the like when the metal is cleaned after an etching. Further, the native oxide 34 can be formed by a reaction between the metal and oxygen in air when the metal is exposed to air. The native oxide 34 can be formed by many ways.

In FIG. 2, a metal oxide layered structure 36 is formed on the metallization pattern 32. The metal oxide layered structure 36 can, in some embodiments, include the native oxide 34, or in other embodiment, the native oxide 34 can be removed. Examples and further details of various metal oxide layered structures 36 are illustrated and discussed with respect to FIGS. 4A-B, 5A-B, 6A-B, 7A-B, and 8A-B. The metal oxide layered structure 36 includes a layer of a metal oxide consisting essentially of atoms of a metal, such as atoms of the metal of the metallization pattern 32, and atoms of oxygen at a ratio of substantially 1:1 (solely for convenience, hereinafter such ratio is indicated as “Mx:O=1:1”). A ratio of substantially 1:1 can include ratios of 0.8:1 to 1.2:1, such as 0.9:1 to 1.1:1. For example, in some embodiments where the metallization pattern 32 is copper, the metal oxide layered structure 36 includes a layer of cupric oxide (CuO), and a ratio of copper atoms to oxygen atoms in that layer is substantially 1:1. One of ordinary skill in the art will readily understand that other incidental atoms, such as of nitrogen and/or carbon, may be included in a layer of a metal oxide consisting essentially of atoms of a metal and atoms of oxygen at a ratio of substantially 1:1 as a result of processing, for example.

In FIG. 3, a second dielectric layer 38 is formed on the metal oxide layered structure 36 and the first dielectric layer 30. In some embodiments, the second dielectric layer 38 is formed of a polymer, which may be a photo-sensitive material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. As used herein, a photo-sensitive material includes a developed material that was photo-sensitive before developing. The second dielectric layer 38 may be formed by any acceptable deposition process, such as spin coating, laminating, the like, or a combination thereof.

FIGS. 4A and 4B illustrate a first example metal oxide layered structure 36A and a method of forming the metal oxide layered structure 36A in accordance with some embodiments. FIG. 4A illustrates the metallization pattern 32, which in step 200 of FIG. 4B is formed as discussed with respect to FIG. 1. As discussed further in FIG. 1, a native oxide 34 may be formed on the metallization pattern 32. In step 202 of FIG. 4B, the native oxide 34 is removed. The removal may be by an acceptable cleaning process, such as a nitrogen (N2) plasma process. In step 204 of FIG. 4B, a metal oxide layer 40 having Mx:O=1:1 is formed directly on the metallization pattern 32. The metal oxide layer 40 can be formed by treating the metallization pattern 32 with an oxygen-containing plasma, such as a plasma comprising oxygen (O2), ozone (O3), water (H2O), the like, or a combination thereof. The oxygen-containing plasma can comprise additional plasma species, such as nitrogen (N2), hydrogen (H2), argon (Ar), the like, or a combination thereof. As an example, the metallization pattern 32 can be copper, and the metal oxide layer 40 can be cupric oxide (CuO). As illustrated, the metal oxide layered structure 36A consists of the metal oxide layer 40 having Mx:O=1:1. In step 206 of FIG. 4B, the second dielectric layer 38 is formed on the metal oxide layered structure 36A, as discussed with respect to FIG. 3.

FIGS. 5A and 5B illustrate a second example metal oxide layered structure 36B and a method of forming the metal oxide layered structure 36B in accordance with some embodiments. FIG. 5A illustrates the metallization pattern 32, which in step 210 of FIG. 5B is formed as discussed with respect to FIG. 1. As discussed further in FIG. 1, a native oxide 34 may be formed on the metallization pattern 32. In step 212 of FIG. 5B, the native oxide 34 is removed. The removal may be by an acceptable cleaning process, such as a nitrogen (N2) plasma process. In step 214 of FIG. 5B, a metal oxide layer 42 having Mx:O=1:1 is formed directly on the metallization pattern 32. The metal oxide layer 42 can be formed by treating the metallization pattern 32 with an oxygen-containing plasma, such as a plasma comprising oxygen (O2), ozone (O3), water (H2O), the like, or a combination thereof. The oxygen-containing plasma can comprise additional plasma species, such as nitrogen (N2), hydrogen (H2), argon (Ar), the like, or a combination thereof. In step 216 of FIG. 5B, a native oxide 44 is formed on the metal oxide layer 42. The native oxide 44 may be formed by exposing the metallization pattern 32 and metal oxide layer 42 to an ambient that contains oxygen, such as during a cleaning process that uses water or by exposing the structure to air. As an example, the metallization pattern 32 can be copper; the metal oxide layer 42 can be cupric oxide (CuO); and the native oxide 44 can be cuprous oxide (Cu2O). As illustrated, the metal oxide layered structure 36B consists of the metal oxide layer 42 having Mx:O=1:1 and the native oxide 44. In step 218 of FIG. 5B, the second dielectric layer 38 is formed on the metal oxide layered structure 36B, as discussed with respect to FIG. 3.

FIGS. 6A and 6B illustrate a third example metal oxide layered structure 36C and a method of forming the metal oxide layered structure 36C in accordance with some embodiments. FIG. 6A illustrates the metallization pattern 32, which in step 220 of FIG. 6B is formed as discussed with respect to FIG. 1. As discussed further in FIG. 1, and in step 222 of FIG. 6B, a native oxide 46 is formed directly on the metallization pattern 32. In step 224 of FIG. 6B, a metal oxide layer 48 having Mx:O=1:1 is formed directly on the native oxide 46. The metal oxide layer 48 can be formed by treating the native oxide 46 and metallization pattern 32 with an oxygen-containing plasma, such as a plasma comprising oxygen (O2), ozone (O3), water (H2O), the like, or a combination thereof. The oxygen-containing plasma can comprise additional plasma species, such as nitrogen (N2), hydrogen (H2), argon (Ar), the like, or a combination thereof. As an example, the metallization pattern 32 can be copper; the native oxide 46 can be cuprous oxide (Cu2O); and the metal oxide layer 48 can be cupric oxide (CuO). As illustrated, the metal oxide layered structure 36C consists of the native oxide 46 and the metal oxide layer 48 having Mx:O=1:1. In step 226 of FIG. 6B, the second dielectric layer 38 is formed on the metal oxide layered structure 36C, as discussed with respect to FIG. 3.

FIGS. 7A and 7B illustrate a fourth example metal oxide layered structure 36D and method of forming the metal oxide layered structure 36D in accordance with some embodiments. FIG. 7A illustrates the metallization pattern 32, which in step 230 of FIG. 7B is formed as discussed with respect to FIG. 1. As discussed further in FIG. 1, a native oxide 34 may be formed on the metallization pattern 32. In step 232 of FIG. 7B, the native oxide 34 is removed. The removal may be by an acceptable cleaning process, such as a nitrogen (N2) plasma process. In step 234 of FIG. 7B, a metal oxide layer 50 having Mx:O=1:1 is formed directly on the metallization pattern 32. The metal oxide layer 50 can be formed by treating the metallization pattern 32 with an oxygen-containing plasma, such as a plasma comprising oxygen (O2), ozone (O3), water (H2O), the like, or a combination thereof. The oxygen-containing plasma can comprise additional plasma species, such as nitrogen (N2), hydrogen (H2), argon (Ar), the like, or a combination thereof. In step 236 of FIG. 7B, a native oxide 52 is formed on the metal oxide layer 50. The native oxide 52 may be formed by exposing the metallization pattern 32 and metal oxide layer 50 to an ambient that contains oxygen, such as during a cleaning process that uses water or by exposing the structure to air. In step 238 of FIG. 7B, a metal oxide layer 54 having Mx:O=1:1 is formed directly on the native oxide 52. The metal oxide layer 54 can be formed by treating the native oxide 52, metal oxide layer 50, and metallization pattern 32 with an oxygen-containing plasma, such as a plasma comprising oxygen (O2), ozone (O3), water (H2O), the like, or a combination thereof. The oxygen-containing plasma can comprise additional plasma species, such as nitrogen (N2), hydrogen (H2), argon (Ar), the like, or a combination thereof. As an example, the metallization pattern 32 can be copper; the metal oxide layer 50 can be cupric oxide (CuO); the native oxide 52 can be cuprous oxide (Cu2O); and the metal oxide layer 54 can be cupric oxide (CuO). As illustrated, the metal oxide layered structure 36D consists of the metal oxide layer 50 having Mx:O=1:1, the native oxide 52, and the metal oxide layer 54 having Mx:O=1:1. In step 240 of FIG. 7B, the second dielectric layer 38 is formed on the metal oxide layered structure 36D, as discussed with respect to FIG. 3.

FIGS. 8A and 8B illustrate a fifth example metal oxide layered structure 36E and a method of forming the metal oxide layered structure 36E in accordance with some embodiments. FIG. 8A illustrates the metallization pattern 32, which in step 250 of FIG. 8B is formed as discussed with respect to FIG. 1. As discussed further in FIG. 1, and in step 252 of FIG. 8B, a native oxide 56 is formed directly on the metallization pattern 32. In step 254 of FIG. 8B, a metal oxide layer 58 having Mx:O=1:1 is formed directly on the native oxide 56. The metal oxide layer 58 can be formed by treating the native oxide 56 and metallization pattern 32 with an oxygen-containing plasma, such as a plasma comprising oxygen (O2), ozone (O3), water (H2O), the like, or a combination thereof. The oxygen-containing plasma can comprise additional plasma species, such as nitrogen (N2), hydrogen (H2), argon (Ar), the like, or a combination thereof. In step 256 of FIG. 8B, a native oxide 60 is formed on the metal oxide layer 58. The native oxide 60 may be formed by exposing the metallization pattern 32 and metal oxide layer 58 to an ambient that contains oxygen, such as during a cleaning process that uses water or by exposing the structure to air. As an example, the metallization pattern 32 can be copper; the native oxide 56 can be cuprous oxide (Cu2O); the metal oxide layer 58 can be cupric oxide (CuO); and the native oxide 60 can be cuprous oxide (Cu2O). As illustrated, the metal oxide layered structure 36E consists of the native oxide 56, the metal oxide layer 58 having Mx:O=1:1, and the native oxide 60. In step 258 of FIG. 8B, the second dielectric layer 38 is formed on the metal oxide layered structure 36E, as discussed with respect to FIG. 3.

A metal oxide layered structure 36, such as metal oxide layered structures 36A, 36B, 36C, 36D, and 36E, can promote adhesion between the underlying metallization and the overlying dielectric layer, which can be a photo-sensitive material, as discussed above. Hence, the metal oxide layered structure 36 can be referred to as an adhesion structure. In some embodiments, a thickness of the metal oxide layered structure 36 is greater than or equal to about 50 Å, such as in a range from about 50 Å to about 200 Å, and more particularly in a range from about 50 Å to about 100 Å. For example, a thickness of a metal oxide layer having Mx:O=1:1 of a metal oxide layered structure 36, such as the metal oxide layer 40 of the metal oxide layered structure 36A, is greater than or equal to about 50 Å, such as in a range from about 50 Å to about 200 Å, and more particularly in a range from about 50 Å to about 100 Å. It has been found that a thickness of a metal oxide layered structure 36 greater than or equal to about 50 Å increases adhesion.

It should be noted that although specific examples have been provided using copper, cupric oxide, and cuprous oxide, other metals and oxides may be used. One of ordinary skill in the art will readily understand various oxides that may be formed when a different metal, such as nickel, cobalt, titanium, tungsten, aluminum, or the like, are used.

FIGS. 9 through 23 illustrate cross sectional views of intermediate steps during a process for forming a chip-on-package (CoP) and/or a package-on-package (PoP) structure in accordance with some embodiments. FIG. 9 illustrates a carrier substrate 100 and a release layer 102 formed on the carrier substrate 100. The carrier substrate 100 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 100 may be a wafer, such that multiple packages can be formed on the carrier substrate 100 simultaneously. The release layer 102 may be formed of a polymer-based material, which may be removed along with the carrier substrate 100 from the overlying structures that will be formed in subsequent steps. In some embodiments, the release layer 102 is an epoxy-based thermal-release material, which loses its adhesive property when heated, such as a Light-to-Heat-Conversion (LTHC) release coating. In other embodiments, the release layer 102 may be an ultra-violet (UV) glue, which loses its adhesive property when exposed to UV lights. The release layer 102 may be dispensed as a liquid and cured, may be a laminate film laminated onto the carrier substrate 100, or may be the like. The top surface of the release layer 102 may be leveled and may have a high degree of co-planarity.

In FIGS. 9 through 11, a back side redistribution structure 114 is formed. The back side redistribution structure comprises dielectric layers 104 and 110 and a metallization pattern 106. As illustrated in FIG. 9, the dielectric layer 104 is formed on the release layer 102. The bottom surface of the dielectric layer 104 may be in contact with the top surface of the release layer 102. In some embodiments, the dielectric layer 104 is formed of a polymer, which may be a photo-sensitive material such as PBO, polyimide, BCB, or the like. The dielectric layer 104 may be formed by any acceptable deposition process, such as spin coating, laminating, the like, or a combination thereof.

In FIG. 10, the metallization pattern 106 is formed on the dielectric layer 104. As an example to form metallization pattern 106, a seed layer (not shown) is formed over the dielectric layer 104. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD, sputtering, or the like. A photo resist is then formed and patterned on the seed layer. The photo resist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photo resist corresponds to the metallization pattern 106. The patterning forms openings through the photo resist to expose the seed layer. A metal is formed in the openings of the photo resist and on the exposed portions of the seed layer. The metal may be formed by plating, such as electroplating or electroless plating, or the like. The metal may be copper, nickel, cobalt, titanium, tungsten, aluminum, or the like. Then, the photo resist and portions of the seed layer on which the metal is not formed are removed. The photo resist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photo resist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and metal form the metallization pattern 106.

A metal oxide layered structure 108 is then formed on exposed surfaces of the metallization pattern 106. The metal oxide layered structure 108 can have any of the structures illustrated in FIGS. 4A, 5A, 6A, 7A, and 8A of the like, and can be formed by any of the methods outlined in FIGS. 4B, 5B, 6B, 7B, and 8B or the like.

In FIG. 11, the dielectric layer 110 is formed on the metallization pattern 106 and the dielectric layer 104. In some embodiments, the dielectric layer 110 is formed of a polymer, which may be a photo-sensitive material such as PBO, polyimide, BCB, or the like. The dielectric layer 110 may be formed by spin coating, lamination, the like, or a combination thereof. The dielectric layer 110 is then patterned to form openings to expose portions 112 of the metal oxide layered structure 108 on the metallization pattern 106. When the dielectric layer 110 is a photo-sensitive material, the patterning may be by exposing the dielectric layer 110 to light using a lithography mask and subsequently developing the dielectric layer 110. Other patterning techniques, such as etching, can be used.

As illustrated, the back side redistribution structure 114 includes two dielectric layers 104 and 110 and one metallization pattern 106. In other embodiments, the back side redistribution structure 114 can comprise any number of dielectric layers, metallization patterns, and vias. One or more additional metallization pattern and dielectric layer may be formed in the back side redistribution structure 114 by repeating the processes for forming a metallization pattern 106 and dielectric layer 110. Vias may be formed during the formation of a metallization pattern by forming the seed layer and metal of the metallization pattern in the openings of the underlying dielectric layer. The vias may therefore interconnect and electrically couple the various metallization patterns.

In FIG. 12, through vias 116 are formed. As an example to form the through vias 116, the exposed portions 112 of the metal oxide layered structure 108 are removed to expose portions of the metallization pattern 106, and then, a seed layer (not shown) is formed on the dielectric layer 110 and the exposed portions of the metallization pattern 106. The exposed portions 112 of the metal oxide layered structure 108 may be removed by a sputter etch or the like. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD, sputtering, or the like. The exposed portions 112 of the metal oxide layered structure 108 can be removed in a same processing chamber in which the seed layer is formed. A photo resist is then formed and patterned on the seed layer. The photo resist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photo resist corresponds to the through vias 116. The patterning forms openings through the photo resist to expose the seed layer. A metal is formed in the openings of the photo resist and on the exposed portions of the seed layer. The metal may be formed by plating, such as electroplating or electroless plating, or the like. The metal may be copper, titanium, tungsten, aluminum, or the like. Then, the photo resist and portions of the seed layer on which the metal is not formed are removed. The photo resist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photo resist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and metal form through vias 116. Because the portions 112 of the metal oxide layered structure 108 were removed from the metallization pattern 106, direct metal-metal interfaces 118 are formed between the through vias 116 and the metallization pattern 106.

Further in FIG. 12, an integrated circuit die 119 is adhered to the dielectric layer 110 by an adhesive 120. As illustrated, one integrated circuit die 119 is adhered in a package structure, and in other embodiments, more integrated circuit dies may be adhered in a package structure. Before being adhered to the dielectric layer 110, the integrated circuit die 119 may be processed according to applicable manufacturing processes to form an integrated circuit in the integrated circuit die 119. For example, the integrated circuit die 119 comprises a semiconductor substrate 122. The semiconductor substrate 122 can be a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, multi-layered or gradient substrates, or the like. The semiconductor material of the semiconductor substrate 122 may be doped or undoped and may include an elemental semiconductor, such as silicon or germanium; a compound or allow semiconductor including SiGe, SiC, GaAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or the like; or a combination thereof. Devices, such as transistors, diodes, capacitors, resistors, etc., may be formed in and/or on the semiconductor substrate 122 and may be interconnected by interconnect structures 124 formed by, for example, metallization patterns in one or more dielectric layers on the semiconductor substrate 122 to form an integrated circuit.

The integrated circuit die 119 further comprises pads 126, such as aluminum pads, to which external connections are made. The pads 126 are on what may be referred to as an active side of the integrated circuit die 119. A passivation film 128 is on the integrated circuit die 119 and on portions of the pads 126. Openings are through the passivation film 128 to the pads 126. Die connectors 130, such as conductive pillars (for example, comprising a metal such as copper), are in the openings through passivation film 128 and are mechanically and electrically coupled to the respective pads 126. The die connectors 130 may be formed by, for example, plating or the like. The die connectors 130 electrically couple the integrated circuit of the integrate circuit die 119.

A dielectric material 132 is on the active side of the integrated circuit die 119, such as on the passivation film 128 and the die connectors 130. The dielectric material 132 laterally encapsulates the die connectors 130, and the dielectric material 132 is laterally co-terminus with the integrated circuit die 119. The dielectric material 132 may be a polymer such as PBO, polyimide, BCB, or the like; a nitride such as silicon nitride or the like; an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; the like, or a combination thereof, and may be formed, for example, by spin coating, lamination, CVD, or the like.

Adhesive 120 is on a back side of the integrated circuit die 119 and adheres the integrated circuit die 119 to the back side redistribution structure 114, such as the dielectric layer 110 in the illustration. The adhesive 120 may be any suitable adhesive, epoxy, or the like. The adhesive 120 may be applied to a back side of the integrated circuit die 119, such as to a back side of the respective semiconductor wafer. The integrated circuit die 119 may be singulated, such as by sawing or dicing, and adhered to the dielectric layer 110 by the adhesive 120 using, for example, a pick-and-place tool.

In FIG. 13, an encapsulant 134 is formed on the various components. The encapsulant 134 may be a molding compound, epoxy, or the like, and may be applied by compression molding, transfer molding, or the like. After curing, the encapsulant 134 can undergo a grinding process to expose the through vias 116 and die connectors 130. Top surfaces of the through vias 116, die connectors 130, and encapsulant 134 are co-planar after the grinding process. In some embodiments, the grinding may be omitted, for example, if through vias 116 and die connectors 130 are already exposed.

In FIGS. 14 through 20, a front side redistribution structure 166 is formed. As will be illustrated in FIG. 20, the front side redistribution structure 166 comprises dielectric layers 136, 142, 152, and 162 and metallization patterns 138, 146, and 156.

In FIG. 14, the dielectric layer 136 is formed on the encapsulant 134, through vias 116, and die connectors 130. In some embodiments, the dielectric layer 136 is formed of a polymer, which may be a photo-sensitive material such as PBO, polyimide, BCB, or the like. The dielectric layer 136 may be formed by spin coating, lamination, the like, or a combination thereof. The dielectric layer 136 is then patterned to form openings to expose portions of the through vias 116 and die connectors 130. When the dielectric layer 136 is a photo-sensitive material, the patterning may be by exposing the dielectric layer 136 to light using a lithography mask and subsequently developing the dielectric layer 136. Other patterning techniques, such as etching, can be used.

In FIG. 15, metallization pattern 138 with vias is formed on the dielectric layer 136. As an example to form metallization pattern 138, a seed layer (not shown) is formed over the dielectric layer 136 and in openings through the dielectric layer 136. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photo resist is then formed and patterned on the seed layer. The photo resist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photo resist corresponds to the metallization pattern 138. The patterning forms openings through the photo resist to expose the seed layer. A metal is formed in the openings of the photo resist and on the exposed portions of the seed layer. The metal may be formed by plating, such as electroplating or electroless plating, or the like. The metal may comprise a metal, like copper, nickel, cobalt, titanium, tungsten, aluminum, or the like. Then, the photo resist and portions of the seed layer on which the metal is not formed are removed. The photo resist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photo resist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and metal form the metallization pattern 138 and vias. The vias are formed in openings through the dielectric layer 136 to, e.g., the through vias 116 and/or the die connectors 130.

A metal oxide layered structure 140 is then formed on exposed surfaces of the metallization pattern 138. The metal oxide layered structure 140 can have any of the structures illustrated in FIGS. 4A, 5A, 6A, 7A, and 8A or the like, and can be formed by any of the methods outlined in FIGS. 4B, 5B, 6B, 7B, and 8B or the like.

In FIG. 16, the dielectric layer 142 is formed on the metallization pattern 138 and the dielectric layer 136. In some embodiments, the dielectric layer 142 is formed of a polymer, which may be a photo-sensitive material such as PBO, polyimide, BCB, or the like. The dielectric layer 142 may be formed by spin coating, lamination, the like, or a combination thereof. The dielectric layer 142 is then patterned to form openings to expose portions 144 of the metal oxide layered structure 140 on the metallization pattern 138. When the dielectric layer 142 is a photo-sensitive material, the patterning may be by exposing the dielectric layer 142 to light using a lithography mask and subsequently developing the dielectric layer 142. Other patterning techniques, such as etching, can be used.

In FIG. 17, metallization pattern 146 with vias is formed on the dielectric layer 142. As an example to form metallization pattern 146, the exposed portions 144 of the metal oxide layered structure 140 are removed to expose portions of the metallization pattern 138, and then, a seed layer (not shown) is formed on the dielectric layer 142 and the exposed portions of the metallization pattern 138. The exposed portions 144 of the metal oxide layered structure 140 may be removed by a sputter etch or the like. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD, sputtering, or the like. The exposed portions 144 of the metal oxide layered structure 140 can be removed in a same processing chamber in which the seed layer is formed. A photo resist is then formed and patterned on the seed layer. The photo resist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photo resist corresponds to the metallization pattern 146. The patterning forms openings through the photo resist to expose the seed layer. A metal is formed in the openings of the photo resist and on the exposed portions of the seed layer. The metal may be formed by plating, such as electroplating or electroless plating, or the like. The metal may be copper, nickel, cobalt, titanium, tungsten, aluminum, or the like. Then, the photo resist and portions of the seed layer on which the metal is not formed are removed. The photo resist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photo resist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and metal form the metallization pattern 146 and vias. The vias are formed in openings through the dielectric layer 142 to, e.g., portions of the metallization pattern 138. Because the portions 144 of the metal oxide layered structure 140 were removed from the metallization pattern 138, direct metal-metal interfaces 148 are formed between the vias of the metallization pattern 146 and the metallization pattern 138.

A metal oxide layered structure 150 is then formed on exposed surfaces of the metallization pattern 146. The metal oxide layered structure 150 can have any of the structures illustrated in FIGS. 4A, 5A, 6A, 7A, and 8A or the like, and can be formed by any of the methods outlined in FIGS. 4B, 5B, 6B, 7B, and 8B or the like.

In FIG. 18, the dielectric layer 152 is formed on the metallization pattern 146 and the dielectric layer 142. In some embodiments, the dielectric layer 152 is formed of a polymer, which may be a photo-sensitive material such as PBO, polyimide, BCB, or the like. The dielectric layer 152 may be formed by spin coating, lamination, the like, or a combination thereof. The dielectric layer 152 is then patterned to form openings to expose portions 154 of the metal oxide layered structure 150 on the metallization pattern 146. When the dielectric layer 152 is a photo-sensitive material, the patterning may be by exposing the dielectric layer 152 to light using a lithography mask and subsequently developing the dielectric layer 152. Other patterning techniques, such as etching, can be used.

In FIG. 19, metallization pattern 156 with vias is formed on the dielectric layer 152. As an example to form metallization pattern 156, the exposed portions 154 of the metal oxide layered structure 150 are removed to expose portions of the metallization pattern 146, and then, a seed layer (not shown) is formed on the dielectric layer 152 and the exposed portions of the metallization pattern 146. The exposed portions 154 of the metal oxide layered structure 150 may be removed by a sputter etch or the like. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD, sputtering, or the like. The exposed portions 154 of the metal oxide layered structure 150 can be removed in a same processing chamber in which the seed layer is formed. A photo resist is then formed and patterned on the seed layer. The photo resist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photo resist corresponds to the metallization pattern 156. The patterning forms openings through the photo resist to expose the seed layer. A metal is formed in the openings of the photo resist and on the exposed portions of the seed layer. The metal may be formed by plating, such as electroplating or electroless plating, or the like. The metal may be copper, nickel, cobalt, titanium, tungsten, aluminum, or the like. Then, the photo resist and portions of the seed layer on which the metal is not formed are removed. The photo resist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photo resist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and metal form the metallization pattern 156 and vias. The vias are formed in openings through the dielectric layer 152 to, e.g., portions of the metallization pattern 146. Because the portions 154 of the metal oxide layered structure 150 were removed from the metallization pattern 146, direct metal-metal interfaces 158 are formed between the vias of the metallization pattern 156 and the metallization pattern 146.

A metal oxide layered structure 160 is then formed on exposed surfaces of the metallization pattern 156. The metal oxide layered structure 160 can have any of the structures illustrated in FIGS. 4A, 5A, 6A, 7A, and 8A or the like, and can be formed by any of the methods outlined in FIGS. 4B, 5B, 6B, 7B, and 8B or the like.

In FIG. 20, the dielectric layer 162 is formed on the metallization pattern 156 and the dielectric layer 152. In some embodiments, the dielectric layer 162 is formed of a polymer, which may be a photo-sensitive material such as PBO, polyimide, BCB, or the like. The dielectric layer 162 may be formed by spin coating, lamination, the like, or a combination thereof. The dielectric layer 162 is then patterned to form openings to expose portions 164 of the metal oxide layered structure 160 on the metallization pattern 156. When the dielectric layer 162 is a photo-sensitive material, the patterning may be by exposing the dielectric layer 162 to light using a lithography mask and subsequently developing the dielectric layer 162. Other patterning techniques, such as etching, can be used.

The front side redistribution structure 166 is shown as an example. More or fewer dielectric layers and metallization patterns may be formed in the front side redistribution structure 166. If fewer dielectric layers and metallization patterns are to be formed, steps and process discussed above may be omitted. If more dielectric layers and metallization patterns are to be formed, steps and processes discussed above may be repeated. One having ordinary skill in the art will readily understand which steps and processes would be omitted or repeated.

In FIG. 21, pads 168, which may be referred to as Under Bump Metallurgies (UBMs), are formed on an exterior side of the front side redistribution structure 166. In the illustrated embodiment, pads 168 are formed through openings through the dielectric layer 162 to the metallization pattern 156. As an example to form the pads 168, the exposed portions 164 of the metal oxide layered structure 160 are removed to expose portions of the metallization pattern 156, and then, a seed layer (not shown) is formed on the dielectric layer 162 and the exposed portions of the metallization pattern 156. The exposed portions 164 of the metal oxide layered structure 160 may be removed by a sputter etch or the like. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD, sputtering, or the like. The exposed portions 164 of the metal oxide layered structure 160 can be removed in a same processing chamber in which the seed layer is formed. A photo resist is then formed and patterned on the seed layer. The photo resist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photo resist corresponds to the pads 168. The patterning forms openings through the photo resist to expose the seed layer. A metal is formed in the openings of the photo resist and on the exposed portions of the seed layer. The metal may be formed by plating, such as electroplating or electroless plating, or the like. The metal may be copper, titanium, tungsten, aluminum, or the like. Then, the photo resist and portions of the seed layer on which the metal is not formed are removed. The photo resist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photo resist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and metal form the pads 168. The pads 168 are formed in openings through the dielectric layer 162 to, e.g., portions of the metallization pattern 156. Because the portions 164 of the metal oxide layered structure 160 were removed from the metallization pattern 156, direct metal-metal interfaces 170 are formed between the pads 168 and the metallization pattern 156.

In FIG. 22, external electrical connectors 172, such as solder balls, like ball grid array (BGA) balls, are formed on the pads 168. The external electrical connectors 172 may include a low-temperature reflowable material such as solder, which may be lead-free or lead-containing. The external electrical connectors 172 may be formed by using an appropriate ball drop process. In some embodiments, the pads 168 can be omitted, and the external electrical connectors 172 can be formed directly on the metallization pattern 156 through the openings through the dielectric layer 162.

In FIG. 23, a carrier substrate de-bonding is performed to detach (de-bond) the carrier substrate 100 from the back side redistribution structure 114, e.g., dielectric layer 104. In accordance with some embodiments, the de-bonding includes projecting a light such as a laser light or an UV light on the release layer 102 so that the release layer 102 decomposes under the heat of the light and the carrier substrate 100 can be removed. The structure is then flipped over and placed on a tape 174. Openings are formed through the dielectric layer 104 to expose portions of the metallization pattern 106. The openings may be formed, for example, using laser drilling, etching, or the like.

Although not specifically illustrated, one of ordinary skill in the art will readily understand that typically the structures formed in FIGS. 9 through 23 are also simultaneously formed in other regions of the carrier substrate 100, which may be a wafer. Accordingly, a singluation process is performed, such as by sawing, to singulate a single package 180 from other packages that may have been formed simultaneously with the package 180.

As illustrated in FIGS. 24 through 27, the package 180 can be incorporated into a variety of chip-on-package (CoP) and package-on-package (PoP) structures. FIGS. 24 through 27 are example structures, and the package 180 can be incorporated in any package structure. In FIGS. 24 through 27, the package 180 is attached to a substrate 182. The external electrical connectors 172 are electrically and mechanically coupled to pads 184 on the substrate 182. The substrate 182 can be, for example, a printed circuit board (PCB) or the like.

In FIG. 24, an integrated circuit die 300 (or chip) is attached to the back side redistribution structure 114 of the package 180 by external electrical connectors 302. The integrated circuit die 300 can be any integrated circuit die, such as a logic die, analog die, memory die, or the like. The integrated circuit die 300 is electrically and mechanically coupled to the back side redistribution structure 114 by external electrical connectors 302 attached to the metallization pattern 106 through openings through the dielectric layer 104. The external electrical connectors 302 can include low-temperature reflowable material, such as solder, such as a lead-free solder, and in additional embodiments, the external electrical connectors 302 can include metal pillars. In some embodiments, the external electrical connectors 302 are controlled collapse chip connection (C4) bumps, microbumps, or the like. In some embodiments, the external electrical connectors 302 can be reflowed to attach the integrated circuit die 300 to the package 180. An underfill material 304 can also be dispensed between the integrated circuit die 300 and the backside redistribution structure 114 of the package 180 and around the external electrical connectors 302.

In FIG. 25, a package component 310 is attached to the back side redistribution structure 114 of the package 180 by external electrical connectors 312. The package component 310 in this example includes an integrated circuit die flip-chip attached to an interposer. The integrated circuit die can be any integrated circuit die, such as a logic die, analog die, memory die, or the like. The package component 310 is electrically and mechanically coupled to the back side redistribution structure 114 by external electrical connectors 312 attached to the metallization pattern 106 through openings through the dielectric layer 104. The external electrical connectors 312 can include low-temperature reflowable material, such as solder, such as a lead-free solder, and in additional embodiments, the external electrical connectors 312 can include metal pillars. In some embodiments, the external electrical connectors 312 are C4 bumps, microbumps, or the like. In some embodiments, the external electrical connectors 312 can be reflowed to attach the package component 310 to the package 180.

In FIG. 26, a package 320 is attached to the back side redistribution structure 114 of the package 180 by external electrical connectors 322. The package 320 comprises a substrate, two stacked integrated circuit dies on the substrate, wire bonds electrically coupling the integrated circuit dies to the substrate, and an encapsulant encapsulating the stacked integrated circuit dies and the wire bonds. In an example, the integrated circuit dies of the package 320 are memory dies, such as dynamic random access memory (DRAM) dies. The package 320 is electrically and mechanically coupled to the back side redistribution structure 114 by external electrical connectors 322 attached to the metallization pattern 106 through openings through the dielectric layer 104. In some embodiments, the external electrical connectors 322 can include low-temperature reflowable material, such as solder, such as a lead-free solder, and in additional embodiments, the external electrical connectors 322 can include metal pillars. In some embodiments, the external electrical connectors 322 are C4 bumps, microbumps, or the like. In some embodiments, the external electrical connectors 322 can be reflowed to attach the package 320 to the metallization pattern 106. The integrated circuit dies of the package 320 are electrically and communicatively coupled to the integrated circuit die 119 through, for example, the wire bonds and substrate in the package 320, the external electrical connectors 322, the back side redistribution structure 114, through vias 116, and the front side redistribution structure 166.

In FIG. 27, a package 330 is attached to the back side redistribution structure 114 of the package 180 by external electrical connectors 332. The package 330 can be similar to the package 180 and can be formed by similar processes. For example, in comparison to the package 180, generally, the package 330 omits a back side redistribution structure and through vias. In an example, the integrated circuit die of the package 330 can be a logic die, analog die, memory die such as a dynamic random access memory (DRAM) die, or the like. The package 330 is electrically and mechanically coupled to the back side redistribution structure 114 by external electrical connectors 332 attached to the metallization pattern 106 through openings through the dielectric layer 104. In some embodiments, the external electrical connectors 332 can include low-temperature reflowable material, such as solder, such as a lead-free solder, and in additional embodiments, the external electrical connectors 332 can include metal pillars. In some embodiments, the external electrical connectors 332 are C4 bumps, microbumps, or the like. In some embodiments, the external electrical connectors 332 can be reflowed to attach the package 330 to the metallization pattern 106. The integrated circuit die of the package 330 are electrically and communicatively coupled to the integrated circuit die 119 through, for example, the a front side redistribution structure of the package 330, the external electrical connectors 332, the back side redistribution structure 114, through vias 116, and the front side redistribution structure 166.

Embodiments may achieve some advantages. For example, by providing a metal oxide layered structure on a metallization pattern and between the metallization pattern and a dielectric layer, such as a photo-sensitive dielectric material, adhesion may be improved. This improved adhesion may reduce a risk of delamination between the metallization pattern and the dielectric layer.

An embodiment is a structure. The structure includes an integrated circuit die at least laterally encapsulated by an encapsulant, and a redistribution structure on the integrated circuit die and encapsulant. The redistribution structure is electrically coupled to the integrated circuit die. The redistribution structure includes a first dielectric layer on at least the encapsulant, a metallization pattern on the first dielectric layer, a metal oxide layered structure on the metallization pattern, and a second dielectric layer on the first dielectric layer and the metallization pattern. The metal oxide layered structure includes a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, and a thickness of the metal oxide layered structure is at least 50 Å. The second dielectric layer is a photo-sensitive material. The metal oxide layered structure is disposed between the metallization pattern and the second dielectric layer.

Another embodiment is a structure. The structure comprises an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a first dielectric layer on the encapsulant and an active side of the integrated circuit die, a metallization pattern on the first dielectric layer, an adhesion layer on the metallization pattern, and a second dielectric layer on the first dielectric layer and the adhesion layer. The metallization pattern is electrically coupled to the active side of the integrated circuit die. The adhesion layer comprises a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, and a thickness of the adhesion layer is at least 50 Å. The second dielectric layer is a photo-sensitive material.

A further embodiment is a method. The method comprises encapsulating an integrated circuit die with an encapsulant; forming a dielectric layer over the encapsulant and the integrated circuit die; forming a metallization pattern over the dielectric layer; treating the metallization pattern with an oxygen-containing plasma, the treating forming a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1 over the metallization pattern, a thickness of the metal oxide layer being at least 50 Å; and forming a photo-sensitive material over the metal oxide layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

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Citation

Patents Cited in This Cited by
Title Current Assignee Application Date Publication Date
Semiconductor package including a semiconductor device, and method of manufacturing the same SAMSUNG ELECTRONICS CO., LTD. 03 February 2005 29 December 2005
セラミック焼結体の製造方法および積層型セラミック電子部品の製造方法 MURATA MFG CO LTD 25 April 2001 08 November 2002
Manufacturing method of semiconductor device and semiconductor device TOSHIBA MEMORY CORPORATION 29 July 2010 03 February 2011
Warpage Reduction and Adhesion Improvement of Semiconductor Die Package TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 08 March 2013 11 September 2014
Electrical conductor system of a semiconductor device and manufacturing method thereof MICRON TECHNOLOGY, INC. 17 April 2000 31 December 2008
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US10153175 Metal oxide layered structure 1 US10153175 Metal oxide layered structure 2 US10153175 Metal oxide layered structure 3