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Patent Analysis of

Semiconductor integrated circuit

Updated Time 12 June 2019

Patent Registration Data

Publication Number

US10153272

Application Number

US14/989288

Application Date

06 January 2016

Publication Date

11 December 2018

Current Assignee

SK HYNIX INC.

Original Assignee (Applicant)

SK HYNIX INC.

International Classification

H02H9/00,H02H9/04,H01L27/02,H01L27/06

Cooperative Classification

H01L27/0281,H01L27/0266,H02H9/046,H01L27/0629,H01L27/0288

Inventor

KIM, JONG SU

Patent Images

This patent contains figures and images illustrating the invention and its embodiment.

US10153272 Semiconductor integrated circuit 1 US10153272 Semiconductor integrated circuit 2 US10153272 Semiconductor integrated circuit 3
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Abstract

A first power line configured to receive a first voltage, a second power line configured to receive a second voltage which is lower than the first voltage, a first clamping unit configured to be connected to the first power line, a second clamping unit configured to be connected between the first clamping unit and the second power line, and a discharging unit configured to, when an abnormal voltage introduced through the first power line or the second power line is applied, discharge the abnormal voltage by coupling with the first clamping unit or the second clamping unit are included.

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Claims

1. A semiconductor integrated circuit comprising:

a first power line configured to receive a first voltage; a second power line configured to receive a second voltage which is lower than the first voltage; a first clamping unit configured to be connected to the first power line; a second clamping unit configured to be connected between the first clamping unit and the second power line, and to offset current linkage generated in the first clamping unit when abnormal noise is introduced into the first or second power line; and a discharging unit configured to be connected between the first power line and the second power line.

2. The semiconductor integrated circuit according to claim 1, wherein the first clamping unit and the second clamping unit are configured with mutually opposite types of MOS transistors, respectively.

3. The semiconductor integrated circuit according to claim 1, wherein:

the first clamping unit is configured with a PMOS transistor the gate and source of which are connected to the first power line; and the second clamping unit is configured with an NMOS transistor the gate and source of which are connected to the second power line.

4. The semiconductor integrated circuit according to claim 1, wherein the discharging unit includes a capacitor.

5. The semiconductor integrated circuit according to claim 1, wherein a resistor is additionally connected between the first clamping unit and the second clamping unit.

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Claim Tree

  • 1
    1. A semiconductor integrated circuit comprising:
    • a first power line configured to receive a first voltage
    • a second power line configured to receive a second voltage which is lower than the first voltage
    • a first clamping unit configured to be connected to the first power line
    • a second clamping unit configured to be connected between the first clamping unit and the second power line, and to offset current linkage generated in the first clamping unit when abnormal noise is introduced into the first or second power line
    • and a discharging unit configured to be connected between the first power line and the second power line.
    • 2. The semiconductor integrated circuit according to claim 1, wherein
      • the first clamping unit and the second clamping unit are configured with mutually opposite types of MOS transistors, respectively.
    • 3. The semiconductor integrated circuit according to claim 1, wherein
      • : the first clamping unit is configured with a PMOS transistor the gate and source of which are connected to the first power line; and the second clamping unit is configured with an NMOS transistor the gate and source of which are connected to the second power line.
    • 4. The semiconductor integrated circuit according to claim 1, wherein
      • the discharging unit includes a capacitor.
    • 5. The semiconductor integrated circuit according to claim 1, wherein
      • a resistor is additionally connected between the first clamping unit and the second clamping unit.
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Description

BACKGROUND

1. Technical Field

The various embodiments generally relate to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit including an electrical overstress protection circuit.

2. Related Art

An electrical overstress (EOS) phenomenon is a phenomenon in which, when a power voltage for a semiconductor integrated circuit is applied, an abnormal excessive voltage (or a spark voltage) is applied to temporarily cause an electrical discharge.

Such an EOS phenomenon may cause a circuit component failure, a circuit board failure, a triggering system failure, and the like. Also, such an EOS phenomenon may continue for a few microseconds to a few seconds.

When the EOS phenomenon is generated in an electronic circuit, a high power voltage can be applied to a line (e.g. a power line), to which a voltage is applied, for a few microseconds or more, so that thermal damage of the power line is more serious than the case of a normal electrostatic discharge (ESD) in which static electricity is transferred for a few pico-seconds.

That is to say, power lines and plugs connected to the power lines can be heated or melted by an excessive voltage applied for a long time. Therefore, demand for a protection circuit capable of effectively discharging a voltage when an excessive voltage is applied has increased.

In addition, together with such an excessive voltage, excessive power noise can be introduced, such power noise also has a problem of causing current leakage in a semiconductor integrated circuit.

SUMMARY

In an embodiment of the present invention, a semiconductor integrated circuit includes: a first power line configured to receive a first voltage; a second power line configured to receive a second voltage which is lower than the first voltage; a first clamping unit configured to be connected to the first power line; a second clamping unit configured to be connected between the first clamping unit and the second power line; and a discharging unit configured to, when an abnormal voltage introduced through the first power line or the second power line is applied, discharge the abnormal voltage by coupling with the first clamping unit or the second clamping unit.

In an embodiment of the present invention, a semiconductor integrated circuit includes: a first power line configured to receive a first voltage; a second power line configured to receive a second voltage which is lower than the first voltage; a first protection circuit unit configured to be connected between the first and second power lines and to discharge an abnormal voltage introduced into the first power line; and a second protection circuit unit configured to be connected between the first and second power lines and to discharge an abnormal voltage introduced into the second power line, wherein the first and second protection circuit units comprises: a first clamping unit configured to be connected to the first power line; a second clamping unit configured to be connected between the first clamping unit and the second power line; and a discharging unit configured to be connected between the first and second power lines, wherein: the discharging unit of the first protection circuit unit is configured to be driven by coupling with one selected from the first and second clamping units; and the discharging unit of the second protection circuit unit is configured to be driven by coupling with the other of the first and second clamping units.

In an embodiment of the present invention, a semiconductor integrated circuit includes: a first power line configured to receive a first voltage; a second power line configured to receive a second voltage which is lower than the first voltage; a first clamping unit configured to be connected to the first power line; a second clamping unit configured to be connected between the first clamping unit and the second power line, and to offset current linkage generated in the first clamping unit when abnormal noise is introduced into the first or second power line; and a discharging unit configured to be connected between the first power line and the second power line.

In an embodiment of the present invention, a semiconductor integrated circuit includes: a first power line configured to receive a first voltage; a second power line configured to receive a second voltage which is different than the first voltage; a first clamping unit configured to be connected to the first power line; a second clamping unit configured to be connected between the first clamping unit and the second power line; and a discharging unit configured to, when an abnormal voltage introduced through the first power line or the second power line is applied, discharge the abnormal voltage by coupling with the first clamping unit or the second clamping unit.

BRIEF DESCRIPTION OF THE DRAWINGS

Features, aspects, and embodiments are described in conjunction with the attached drawings, in which:

FIG. 1 is a circuit diagram illustrating a semiconductor integrated circuit according to an embodiment of the present invention; and

FIGS. 2 to 5 are circuit diagrams illustrating semiconductor integrated circuits according to other embodiments of the present invention.

DETAILED DESCRIPTION

Hereinafter, a semiconductor integrated circuit according to the present invention will be described below with reference to the accompanying drawings through various embodiments.

Referring to FIG. 1, a protection circuit 100 for preventing electrical overstress (EOS) can include a first clamping unit 110, a second clamping unit 120, and a discharging unit 130, which are located between first and second power lines P1 and P2 having mutually different electric potentials.

The first power line P1 can be a line to which a power voltage is applied, and the second power line P2 can be a line to which a ground voltage is applied.

The first clamping unit 110 can be configured with an NMOS transistor, the gate and drain of which are connected to the first power line P1.

The second clamping unit 120 may be connected between the first clamping unit 110 and the second power line P2. The second clamping unit 120 can be an NMOS transistor, the gate and source of which are connected to the second power line P2.

The second clamping unit 120 may be configured with the same type of transistor as the first clamping unit 110, wherein the first and second clamping units 110 and 120 can be connected to operate mutually different directional diodes.

The discharging unit 130 may be connected between the first and second power lines P1 and P2, and may be configured to discharge the voltage of the first power line P1 according to the voltage of a connection node n1 between the first clamping unit 110 and the second clamping unit 120. According to an embodiment, the discharging unit 130 can be, for example, a PMOS transistor.

The protection circuit 100 having the configuration described above operates such that, when an excessive voltage VPP is temporarily applied from the first power line P1, the first clamping unit 110 is turned on, and the connection node n1 is transitioned to a negative level “−(VPP−Vt)” by the coupling of the first clamping unit 110 and the discharging unit 130, so that the discharging unit 130 is driven. Accordingly, the excessive voltage is discharged to the second power line P2 through the first clamping unit 110 and the discharging unit 130. Reference sign “a” in the drawing indicates an excessive voltage discharge path.

As known, when an excessive voltage VPP is applied, power melting is generally generated in the lowest-resistance region. That is to say, when a normal power voltage is applied, a circuit component having the lowest resistance may be the first clamping unit 110. According to an embodiment of the present invention, when an excessive voltage VPP is applied to the first power line P1, melting of the first clamping unit 110 can be prevented by allowing the excessive voltage VPP to separately link through the first clamping unit 110 and the discharging unit 130.

Accordingly, it is possible to prevent an excessive voltage VPP from being introduced into an internal circuit 150.

In addition, an effect by an excessive voltage can be minimized by sufficiently spacing the distance between the protection circuit and a pad (not shown) to which the power lines P1 and P2 are connected. Additionally, a graph of excessive voltage VPP and a voltage less than the excessive voltage VPP VDD is illustrated in FIG. 1.

Also, as illustrated in FIG. 2, a first clamping unit 115 of a protection circuit 100a can be configured with a PMOS transistor, the gate and source of which are connected to the first power line P1; and a second clamping unit 125 thereof can be configured with a PMOS transistor, the gate and drain of which are connected to the second power line P2.

A discharging unit 135 can be configured with an NMOS transistor to be coupled to the first clamping unit 115 or second clamping unit 125. The gate electrode of an NMOS transistor constituting the discharging unit 135 can be connected to a connection node n2 between the first clamping unit 115 and the second clamping unit 125.

The protection circuit 100a having the configuration described above operates such that, when an abnormal voltage Vgg is temporarily applied from the second power line P2, the second clamping unit 125 is turned on, and the voltage of the connection node n2 between the first clamping unit 115 and the second clamping unit 125 is transitioned to a positive level “−(Vgg-Vt)” by the coupling of the second clamping unit 125 and the discharging unit 135, so that the discharging unit 135 is driven. Accordingly, the abnormal voltage generated on the second power line P2 is separately discharged by the second clamping unit 125 and the discharging unit 135. Therefore, it is possible to reduce a phenomenon that an excessive voltage is concentrated on a specific element and melting is caused. Additionally, a graph of abnormal voltage Vgg and a voltage greater than the abnormal voltage Vgg Vss is illustrated in FIG. 2.

Also, as illustrated in FIG. 3, a first protection circuit 100a and a second protection circuit 100 can be doubly connected creating a protection circuit 100b. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. The first protection circuit 100a can have the same configuration as that illustrated in FIG. 2, and the second protection circuit 100 can have the same configuration as that illustrated in FIG. 1. In addition, the connection order of the first protection circuit 100a and second protection circuit 100 can vary. In the case in which the first protection circuit 100a and second protection circuit 100 are doubly connected, abnormal voltages are simultaneously introduced through a first power line P1 and a second power line P2, it is possible to discharge the abnormal voltages in both directions according to the aforementioned principle. Additionally, a graph of excessive voltage VPP and a voltage less than the excessive voltage VPP VDD is illustrated in FIG. 3.

Also, as illustrated in FIG. 4, a first clamping unit 117 can be configured with a PMOS transistor, the gate and source of which are connected to a first power line P1; and a second clamping unit 127 can be configured with an NMOS transistor, the gate and source of which are connected to a second power line P2. A discharging unit 137 can be a capacitor connected between the first power line P1 and the second power line P2.

When an abnormal voltage, e.g. power noise, is introduced into the first and second power line P1 and P2, the electric potential of each gate of the first clamping unit 117 and second clamping unit 127 is shaken as shown in the graphs above and below first and second power lines P1 and P2.

Accordingly, an interference and coupling are generated between the first clamping unit 117 and the second clamping unit 127, and thus current linkage is caused. In this case, the current linkage first offsets and eliminates power noise generated in the power lines P1 and P2. Additionally, the current linkage can discharge residual power noise through the discharging unit 137.

In this case, as illustrated in FIG. 5, a resistor R can be connected between the first clamping unit 117 and the second clamping unit 127 to stabilize the protection circuit. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

According to the present invention, when an abnormal voltage applied through power lines is introduced, the abnormal voltage is separately discharged by linkage using a coupling between elements, so that a power voltage and power noise can be effectively discharged.

While certain embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the device described herein should not be limited based on the described embodiments.

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Citation

Patents Cited in This Cited by
Title Current Assignee Application Date Publication Date
Input and power protection circuit implemented in a complementary metal oxide semiconductor process using salicides AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED 26 May 1999 12 February 2002
Semiconductor integrated circuit SK HYNIX INC. 05 September 2013 16 February 2016
Electrostatic Discharge Protection Circuit, Integrated Circuit And Method Of Protecting Circuitry From An Electrostatic Discharge Voltage INFINEON TECHNOLOGIES AG 16 September 2009 17 March 2011
Electrostatic discharge protection circuit and driving circuit for an LCD using the same INNOLUX CORPORATION 29 September 2006 03 May 2007
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US10153272 Semiconductor integrated circuit 1 US10153272 Semiconductor integrated circuit 2 US10153272 Semiconductor integrated circuit 3