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Patent Analysis of

Electronic device

Updated Time 12 June 2019

Patent Registration Data

Publication Number

US10153423

Application Number

US15/843674

Application Date

15 December 2017

Publication Date

11 December 2018

Current Assignee

SK HYNIX INC.,TOSHIBA MEMORY CORPORATION

Original Assignee (Applicant)

SK HYNIX INC.,TOSHIBA MEMORY CORPORATION

International Classification

G11C11/00,H01L43/02,H01L27/22,H01L43/08,H01L43/10

Cooperative Classification

H01L43/02,G06F3/0604,G06F3/0659,G06F3/0679,G11C11/161

Inventor

KIM, YANG-KON,KIM, GUK-CHEON,LEE, JAE-HYOUNG,LIM, JONG-KOO,JUNG, KU-YOUL,NAGASE, TOSHIHIKO,EEH, YOUNGMIN

Patent Images

This patent contains figures and images illustrating the invention and its embodiment.

US10153423 Electronic 1 US10153423 Electronic 2 US10153423 Electronic 3
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Abstract

An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer which is in contact with the free layer and includes a rare earth metal nitride.

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Claims

1. An electronic device including a semiconductor memory, the semiconductor memory comprising:

a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer which is in contact with the free layer and includes a rare earth metal nitride.

2. The electronic device of claim 1, wherein the under layer comprises a nitride of a rare earth metal including one or more selected from a group consisting of lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), scandium (Sc) and yttrium (Y).

3. The electronic device of claim 1, further comprising a buffer layer being in contact with the under layer to aid a crystal growth of the under layer.

4. The electronic device of claim 3, wherein the buffer layer comprises a material having a hexagonal close packed (HCP) crystal structure.

5. The electronic device of claim 3, wherein the buffer layer comprises one or more selected from a group consisting of hafnium (Hf), magnesium (Mg), zinc (Zn), zirconium (Zr), titanium (Ti), beryllium (Be), cadmium (Cd), ruthenium (Ru) and osmium (Os).

6. The electronic device of claim 3, wherein the buffer layer comprises a material having a wurtzite crystal structure.

7. The electronic device of claim 6, wherein the buffer layer comprises one or more selected from a group consisting of aluminum nitride (AlN), silver iodide (AgI), zinc oxide (ZnO), cadmium sulfide (CdS), cadmium selenide (CdSe), silicon carbide (SiC), galium nitride (GaN) and boron nitride (BN).

8. The electronic device of claim 3, wherein the buffer layer comprises a single-layer or multilayer structure.

9. The electronic device of claim 3, wherein the buffer layer comprises a first buffer layer including a material having a hexagonal close packed (HCP) crystal structure and a second buffer layer including a material having a wurtzite crystal structure.

10. The electronic device of claim 1, wherein sidewalls of the free layer, sidewalls of the tunnel barrier layer and sidewalls of the pinned layer are aligned with one another, and

the under layer has sidewalls which are not aligned with the sidewalls of the free layer, the sidewalls of the tunnel barrier layer and the sidewalls of the pinned layer.

11. The electronic device of claim 3, wherein sidewalls of the free layer, sidewalls of the tunnel barrier layer and sidewalls of the pinned layer are aligned with one another,

sidewalls of the under layer and sidewalls of the buffer layer are aligned with each other, and the sidewalls of the free layer, the sidewalls of the tunnel barrier layer and the sidewalls of the pinned layer are not aligned with the sidewalls of the under layer and the sidewalls of the buffer layer.

12. The electronic device according to claim 1, further comprising a microprocessor which includes:

a control unit configured to receive a signal including a command from an outside of the microprocessor, and perform extracting, decoding of the command, or controlling input or output of a signal of the microprocessor; an operation unit configured to perform an operation based on a result that the control unit decodes the command; and a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed, wherein the semiconductor memory is part of the memory unit in the microprocessor.

13. The electronic device according to claim 1, further comprising a processor which includes:

a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data; a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit, wherein the semiconductor memory is part of the cache memory unit in the processor.

14. The electronic device according to claim 1, further comprising a processing system which includes:

a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command; an auxiliary memory device configured to store a program for decoding the command and the information; a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside, wherein the semiconductor memory is part of the auxiliary memory device or the main memory device in the processing system.

15. The electronic device according to claim 1, further comprising a data storage system which includes:

a storage device configured to store data and conserve stored data regardless of power supply; a controller configured to control input and output of data to and from the storage device according to a command inputted from an outside; a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside, wherein the semiconductor memory is part of the storage device or the temporary storage device in the data storage system.

16. The electronic device according to claim 1, further comprising a memory system which includes:

a memory configured to store data and conserve stored data regardless of power supply; a memory controller configured to control input and output of data to and from the memory according to a command inputted from an outside; a buffer memory configured to buffer data exchanged between the memory and the outside; and an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside, wherein the semiconductor memory is part of the memory or the buffer memory in the memory system.

17. An electronic device including a semiconductor memory, the semiconductor memory comprising:

a substrate; a plurality of memory cells formed over the substrate, each memory cell including a magnetic layer and an under layer which is in contact with the magnetic layer to enhance a magnetic characteristic of the magnetic layer and includes a rare earth metal nitride; and switching elements formed over the substrate and coupled to the memory cells, respectively to select or de-select the memory cells.

18. The electronic device of claim 17, wherein each memory cell comprises the under layer and a magnetic tunnel junction structure including the magnetic layer.

19. The electronic device of claim 17, wherein the under layer comprises a nitride of a rare earth metal including one or more selected from a group consisting of lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), scandium (Sc) and yttrium (Y).

20. The electronic device of claim 17, wherein each memory cell further comprises a buffer layer being in contact with the under layer to aid a crystal growth of the under layer.

21. The electronic device of claim 20, wherein the buffer layer comprises a material having a hexagonal close packed (HCP) crystal structure.

22. The electronic device of claim 21, wherein the buffer layer comprises one or more selected from a group consisting of hafnium (Hf), magnesium (Mg), zinc (Zn), zirconium (Zr), titanium (Ti), beryllium (Be), cadmium (Cd), ruthenium (Ru) and osmium (Os).

23. The electronic device of claim 20, wherein the buffer layer comprises a material having a wurtzite crystal structure.

24. The electronic device of claim 23, wherein the buffer layer comprises one or more selected from a group consisting of aluminum nitride (AlN), silver iodide (AgI), zinc oxide (ZnO), cadmium sulfide (CdS), cadmium selenide (CdSe), silicon carbide (SiC), galium nitride (GaN) and boron nitride (BN).

25. The electronic device of claim 20, wherein the buffer layer comprises a single-layer or multilayer structure.

26. The electronic device of claim 20, wherein the buffer layer comprises a first buffer layer including a material having a hexagonal close packed (HCP) crystal structure and a second buffer layer including a material having a wurtzite crystal structure.

27. The electronic device of claim 17, wherein each memory cell further comprises:

a free layer which is contact in with the under layer and has a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, and wherein sidewalls of the free layer, sidewalls of the tunnel barrier layer and sidewalls of the pinned layer are aligned with one another, and the under layer has sidewalls which are not aligned with the sidewalls of the free layer, the sidewalls of the tunnel barrier layer and the sidewalls of the pinned layer.

28. The electronic device of claim 20, wherein each memory cell further comprises:

a free layer which is contact in with the under layer and has a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, and wherein sidewalls of the free layer, sidewalls of the tunnel barrier layer and sidewalls of the pinned layer are aligned with one another, sidewalls of the under layer and sidewalls of the buffer layer are aligned with each other, and the sidewalls of the free layer, the sidewalls of the tunnel barrier layer and the sidewalls of the pinned layer are not aligned with the sidewalls of the under layer and the sidewalls of the buffer layer.

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Claim Tree

  • 1
    1. An electronic device including
    • a semiconductor memory, the semiconductor memory comprising: a free layer having a variable magnetization direction
    • a pinned layer having a pinned magnetization direction
    • a tunnel barrier layer interposed between the free layer and the pinned layer
    • and an under layer which is in contact with the free layer and includes a rare earth metal nitride.
    • 2. The electronic device of claim 1, wherein
      • the under layer comprises
    • 3. The electronic device of claim 1, further comprising
      • a buffer layer being in contact with the under layer to aid a crystal growth of the under layer.
    • 10. The electronic device of claim 1, wherein
      • sidewalls of the free layer, sidewalls of the tunnel barrier layer and sidewalls of the pinned layer are aligned with one another, and the under layer has sidewalls which are not aligned with the sidewalls of the free layer, the sidewalls of the tunnel barrier layer and the sidewalls of the pinned layer.
    • 12. The electronic device according to claim 1, further comprising
      • a microprocessor which includes: a control unit configured to receive a signal including a command from an outside of the microprocessor, and perform extracting, decoding of the command, or controlling input or output of a signal of the microprocessor
      • an operation unit configured to perform an operation based on a result that the control unit decodes the command
      • and a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed, wherein the semiconductor memory is part of the memory unit in the microprocessor.
    • 13. The electronic device according to claim 1, further comprising
      • a processor which includes: a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data
      • a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed
      • and a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit, wherein the semiconductor memory is part of the cache memory unit in the processor.
    • 14. The electronic device according to claim 1, further comprising
      • a processing system which includes: a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command
      • an auxiliary memory device configured to store a program for decoding the command and the information
      • a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program
      • and an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside, wherein the semiconductor memory is part of the auxiliary memory device or the main memory device in the processing system.
    • 15. The electronic device according to claim 1, further comprising
      • a data storage system which includes: a storage device configured to store data and conserve stored data regardless of power supply
      • a controller configured to control input and output of data to and from the storage device according to a command inputted from an outside
      • a temporary storage device configured to temporarily store data exchanged between the storage device and the outside
      • and an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside, wherein the semiconductor memory is part of the storage device or the temporary storage device in the data storage system.
    • 16. The electronic device according to claim 1, further comprising
      • a memory system which includes: a memory configured to store data and conserve stored data regardless of power supply
      • a memory controller configured to control input and output of data to and from the memory according to a command inputted from an outside
      • a buffer memory configured to buffer data exchanged between the memory and the outside
      • and an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside, wherein the semiconductor memory is part of the memory or the buffer memory in the memory system.
  • 17
    17. An electronic device including
    • a semiconductor memory, the semiconductor memory comprising: a substrate
    • a plurality of memory cells formed over the substrate, each memory cell including a magnetic layer and an under layer which is in contact with the magnetic layer to enhance a magnetic characteristic of the magnetic layer and includes a rare earth metal nitride
    • and switching elements formed over the substrate and coupled to the memory cells, respectively to select or de-select the memory cells.
    • 18. The electronic device of claim 17, wherein
      • each memory cell comprises
    • 19. The electronic device of claim 17, wherein
      • the under layer comprises
    • 20. The electronic device of claim 17, wherein
      • each memory cell further comprises
    • 27. The electronic device of claim 17, wherein
      • each memory cell further comprises:
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Description

TECHNICAL FIELD

This patent document relates to memory circuits or devices and their applications in electronic devices or systems.

BACKGROUND

Recently, as electronic devices or appliances trend toward miniaturization, low power consumption, high performance, multi-functionality, and so on, there is a demand for electronic devices capable of storing information in various electronic devices or appliances such as a computer, a portable communication device, and so on, and research and development for such electronic devices has been increasing. Examples of such electronic devices include electronic devices which can store data using a characteristic switched between different resistant states according to an applied voltage or current, and can be implemented in various configurations, for example, a resistive random access memory (RRAM), a phase change random access memory (PRAM), a ferroelectric random access memory (FRAM), a magnetic random access memory (MRAM), and an E-fuse.

SUMMARY

The disclosed technology in this patent document is directed to memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device, in which an electronic device includes a semiconductor memory which can improve characteristics of a variable resistance element.

In an implementation, an electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer which is in contact with the free layer and includes a rare earth metal nitride.

Implementations of the above electronic device may include one or more the following.

The under layer may include a nitride of a rare earth metal including one or more selected from a group consisting of lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), scandium (Sc) and yttrium (Y). The semiconductor memory may further include a buffer layer being in contact with the under layer to aid a crystal growth of the under layer. The buffer layer may include a material having a hexagonal close packed (HCP) crystal structure. The buffer layer may include one or more selected from a group consisting of hafnium (Hf), magnesium (Mg), zinc (Zn), zirconium (Zr), titanium (Ti), beryllium (Be), cadmium (Cd), ruthenium (Ru) and osmium (Os). The buffer layer may include a material having a wurtzite crystal structure. The buffer layer may include one or more selected from a group consisting of aluminum nitride (AlN), silver iodide (AgI), zinc oxide (ZnO), cadmium sulfide (CdS), cadmium selenide (CdSe), silicon carbide (SiC), galium nitride (GaN) and boron nitride (BN). The buffer layer may include a single-layer or multilayer structure. The buffer layer may include a first buffer layer including a material having a HCP crystal structure and a second buffer layer including a material having a wurtzite crystal structure. Sidewalls of the free layer, sidewalls of the tunnel barrier layer and sidewalls of the pinned layer may be aligned with one another, and the under layer may have sidewalls which are not aligned with the sidewalls of the free layer, the sidewalls of the tunnel barrier layer and the sidewalls of the pinned layer. Sidewalls of the free layer, sidewalls of the tunnel barrier layer and sidewalls of the pinned layer may be aligned with one another, sidewalls of the under layer and sidewalls of the buffer layer may be aligned with each other, and the sidewalls of the free layer, the sidewalls of the tunnel barrier layer and the sidewalls of the pinned layer may not be aligned with the sidewalls of the under layer and the sidewalls of the buffer layer.

The electronic device may further include a microprocessor which includes: a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor; an operation unit configured to perform an operation based on a result that the control unit decodes the command; and a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed, wherein the semiconductor memory is part of the memory unit in the microprocessor.

The electronic device may further include a processor which includes: a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data; a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit, wherein the semiconductor memory is part of the cache memory unit in the processor.

The electronic device may further include a processing system which includes: a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command; an auxiliary memory device configured to store a program for decoding the command and the information; a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside, wherein the semiconductor memory is part of the auxiliary memory device or the main memory device in the processing system.

The electronic device may further include a data storage system which includes: a storage device configured to store data and conserve stored data regardless of power supply; a controller configured to control input and output of data to and from the storage device according to a command inputted from an outside; a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside, wherein the semiconductor memory is part of the storage device or the temporary storage device in the data storage system.

The electronic device may further include a memory system which includes: a memory configured to store data and conserve stored data regardless of power supply; a memory controller configured to control input and output of data to and from the memory according to a command inputted from an outside; a buffer memory configured to buffer data exchanged between the memory and the outside; and an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside, wherein the semiconductor memory is part of the memory or the buffer memory in the memory system.

In another implementation, an electronic device may include a semiconductor memory, and the semiconductor memory may include a substrate; a plurality of memory cells formed over the substrate, each memory cell including a magnetic layer and an under layer which is in contact with the magnetic layer to enhance a magnetic characteristic of the magnetic layer and includes a rare earth metal nitride; and switching elements formed over the substrate and coupled to the memory cells, respectively, to select or de-select the memory cells.

Implementations of the above electronic device for fabricating the electronic device may include one or more the following.

Each memory cell may include the under layer and a magnetic tunnel junction structure including the magnetic layer. The under layer may include a nitride of a rare earth metal including one or more selected from a group consisting of lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), scandium (Sc) and yttrium (Y). Each memory cell may further include a buffer layer being in contact with the under layer to aid a crystal growth of the under layer. The buffer layer may include a material having a hexagonal close packed (HCP) crystal structure. The buffer layer may include one or more selected from a group consisting of hafnium (Hf), magnesium (Mg), zinc (Zn), zirconium (Zr), titanium (Ti), beryllium (Be), cadmium (Cd), ruthenium (Ru) and osmium (Os). The buffer layer may include a material having a wurtzite crystal structure. The buffer layer may include one or more selected from a group consisting of aluminum nitride (AlN), silver iodide (AgI), zinc oxide (ZnO), cadmium sulfide (CdS), cadmium selenide (CdSe), silicon carbide (SiC), galium nitride (GaN) and boron nitride (BN). The buffer layer may include a single-layer or multilayer structure. The buffer layer may include a first buffer layer including a material having a HCP crystal structure and a second buffer layer including a material having a wurtzite crystal structure. Each memory cell may further include: a free layer which is contact in with the under layer and has a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, and wherein sidewalls of the free layer, sidewalls of the tunnel barrier layer and sidewalls of the pinned layer may be aligned with one another, and the under layer may have sidewalls which are not aligned with the sidewalls of the free layer, the sidewalls of the tunnel barrier layer and the sidewalls of the pinned layer. Each memory cell may further include: a free layer which is contact in with the under layer and has a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, and wherein sidewalls of the free layer, sidewalls of the tunnel barrier layer and sidewalls of the pinned layer may be aligned with one another, sidewalls of the under layer and sidewalls of the buffer layer may be aligned with each other, and the sidewalls of the free layer, the sidewalls of the tunnel barrier layer and the sidewalls of the pinned layer may not be aligned with the sidewalls of the under layer and the sidewalls of the buffer layer.

These and other aspects, implementations and associated advantages are described in greater detail in the drawings, the description and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present invention will become more apparent to those skilled in the art to which the present invention pertains by the following detailed description with reference to the attached drawings in which:

FIG. 1 is a cross-sectional view of a variable resistance element in accordance with an implementation of the present disclosure.

FIG. 2 is a cross-sectional view of a variable resistance element in accordance with another implementation of the present disclosure.

FIG. 3 is a graph illustrating the perpendicular magnetic anisotropy of free layers in variable resistance elements in accordance with examples of an implementation of the present disclosure and a comparative example.

FIG. 4 is a cross-sectional view illustrating a memory device and a method for fabricating the same in accordance with an implementation of the present disclosure.

FIG. 5 is a cross-sectional view illustrating a memory device and a method for fabricating the same in accordance with another implementation of the present disclosure.

FIG. 6 is an example of configuration diagram of a microprocessor implementing memory circuitry based on the disclosed technology.

FIG. 7 is an example of configuration diagram of a processor implementing memory circuitry based on the disclosed technology.

FIG. 8 is an example of configuration diagram of a system implementing memory circuitry based on the disclosed technology.

FIG. 9 is an example of configuration diagram of a data storage system implementing memory circuitry based on the disclosed technology.

FIG. 10 is an example of configuration diagram of a memory system implementing memory circuitry based on the disclosed technology.

DETAILED DESCRIPTION

Various examples and implementations of the disclosed technology are described below in detail with reference to the accompanying drawings.

The drawings may not be necessarily to scale and in some instances, proportions of at least some of structures in the drawings may have been exaggerated in order to clearly illustrate certain features of the described examples or implementations. In presenting a specific example in a drawing or description having two or more layers in a multi-layer structure, the relative positioning relationship of such layers or the sequence of arranging the layers as shown reflects a particular implementation for the described or illustrated example and a different relative positioning relationship or sequence of arranging the layers may be possible. In addition, a described or illustrated example of a multi-layer structure may not reflect all layers present in that particular multilayer structure (e.g., one or more additional layers may be present between two illustrated layers). As a specific example, when a first layer in a described or illustrated multi-layer structure is referred to as being “on” or “over” a second layer or “on” or “over” a substrate, the first layer may be directly formed on the second layer or the substrate but may also represent a structure where one or more other intermediate layers may exist between the first layer and the second layer or the substrate.

A variable resistance element may mean an element which is capable of being switched between different resistance states in response to the applied bias (for example, a current or voltage). The variable resistance element may store different data according to the resistance states. That is, the variable resistance element may function as a memory cell. The memory cell may further include a selecting element coupled to the variable resistance element and for controlling access to the variable resistance element. The memory cells may be arranged in various way so as to form a semiconductor memory.

In particular, the variable resistance element may include a magnetic tunnel Junction (MTJ) structure including a free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer. When a voltage or current is applied to the variable resistance element, the magnetization direction of the free layer can be changed so as to be parallel or anti-parallel to the magnetization direction of the pinned layer. Thus, the variable resistance element can be changed between a low-resistance state and a high-resistance state. In accordance with implementations to be described below, it is intended to provide a variable resistance element capable of satisfying or improving various characteristics required for the variable resistance element.

FIG. 1 is a cross-sectional view of a variable resistance element in accordance with an implementation of the present disclosure, and FIG. 2 is a cross-sectional view of a variable resistance element in accordance with another implementation of the present disclosure.

Referring to FIGS. 1 and 2, a variable resistance element 100 may include a magnetic tunnel junction (MTJ) structure including a free layer 120 having a variable magnetization direction, a pinned layer 140 having a pinned magnetization direction and a tunnel barrier layer 130 interposed between the free layer 120 and the pinned layer 140.

The free layer 120 may have a variable magnetization direction, and thus may store different data. The free layer 120 may also be referred to as a storage layer. The magnetization direction of the free layer 120 may be substantially perpendicular to the planes of a substrate and the aforementioned layers. In other words, the magnetization direction of the free layer 120 may be substantially parallel to the stacking direction of the free layer 120, the tunnel barrier layer 130 and the pinned layer 140. Accordingly, the magnetization direction of the free layer 120 may be variable between a downward direction and an upward direction. The change in the magnetization direction of the free layer 120 may be caused by a spin transfer torque.

The free layer 120 may be formed of or include a ferromagnetic material. The free layer 120 may have a single-layer or a multilayer structure including the ferromagnetic material. The ferromagnetic material may be an alloy based on at least one of Fe, Ni, Co, Pt, or Pd. For example, the ferromagnetic material may be an Fe—Pt alloy, an Fe—Pd alloy, a Co—Pd alloy, a Co—Pt alloy, an Fe—Ni—Pt alloy, a Co—Fe—Pt alloy, a Co—Ni—Pt alloy, an Fe—Pd alloy, a Co—Pd alloy, a Co—Pt alloy, an Fe—Ni—Pt alloy, a Co—Fe—Pt alloy, a Co—Ni—Pt alloy, or a Co—Fe—B alloy. The ferromagnetic material may be formed of a stack of at least two or more metal layers including Fe, Ni, Co, Pt or Pd, respectively. In an implementation, the free layer 120 may include a stack of metal layers such as a Co layer and a Pt layer, or a Co layer and a Pd layer.

The tunnel barrier layer 130 may be formed of or include a material that allows the tunneling of electrons in a data write operation that changes the resistance state of the variable resistance element 100 so as to change the magnetization direction of the free layer 120. The tunnel barrier layer 130 may be formed of or include a dielectric oxide, for example, an oxide such as MgO, CaO, SrO, TiO, VO, or NbO.

The pinned layer 140 may have a pinned magnetization direction which contrasts with the magnetization direction of the free layer 120 and may be referred to as a reference layer. The pinned layer 140 may have any one of a downward magnetization direction and an upward magnetization direction.

The pinned layer 140 may have a single-layer or a multilayer structure and may be formed of or include a ferromagnetic material. The ferromagnetic material may be an alloy based on at least one of Fe, Ni, Co, Pt, or Pd. For example, the ferromagnetic material may be an Fe—Pt alloy, an Fe—Pd alloy, a Co—Pd alloy, a Co—Pt alloy, an Fe—Ni—Pt alloy, a Co—Fe—Pt alloy, a Co—Ni—Pt alloy, an Fe—Pd alloy, a Co—Pd alloy, a Co—Pt alloy, an Fe—Ni—Pt alloy, a Co—Fe—Pt alloy, a Co—Ni—Pt alloy, or a Co—Fe—B alloy. The ferromagnetic material may be formed of a stack of at least two or more metal layers including Fe, Ni, Co, Pt or Pd, respectively. In an implementation, the pinned layer 140 may include a stack of metal layers such as a Co layer and a Pt layer, or a Co layer and a Pd layer.

When a voltage or current is applied to both of the ends of the variable resistance element 100, the magnetization direction of the free layer 120 may be changed due to spin torque. When the magnetization direction of the free layer 120 and the magnetization direction of the pinned layer 140 are parallel to each other, the variable resistance element 100 may be in a low-resistance state to store a particular designated data bit with a level of “0”. Conversely, when the magnetization direction of the free layer 120 and the magnetization direction of the pinned layer 140 are opposite (anti-parallel) to each other, the variable resistance element 100 may be in a high-resistance state to store a particular designated data bit with a level of “1”.

The variable resistance element 100 may further include one or more additional layers performing various functions to improve a characteristic of the MTJ structure or a fabricating process. For example, the variable resistance element 100 may include a buffer layer 105, an under layer 110, a spacer layer 150, a magnetic correction layer 160 and a capping layer 170.

The under layer 110 may be disposed under the free layer 120 and be in contact with the free layer 120. The under layer 110 may serve to improve perpendicular magnetic anisotropy (Hk) of the free layer 120.

In an implementation, the under layer 110 may be formed of or include a rare earth metal nitride for improving crystal orientation at an interface between the free layer 120 and the under layer 110 and increase perpendicular magnetic anisotropy (Hk) of the free layer 120. As a result, it is possible to improve characteristics of the MTJ element. By contrast if the under layer is formed of a metal, the under layer does not greatly affect the perpendicular magnetic anisotropy of the free layer 120. The perpendicular magnetic anisotropy of the free layer 120 is a major factor relating to the characteristics of the free layer 120 in the MTJ structure.

Preferably, the rare earth metal may include one or more selected from a group consisting of lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), scandium (Sc) and yttrium (Y).

The under layer 110 may have a single-layer or multilayer structure including the rare earth metal nitride.

The buffer layer 105 may be formed under the under layer 110. When the buffer layer 105 is formed under the under layer 110, it is possible to aid the crystal growth of the under layer 110 and further improve the perpendicular magnetic anisotropy of the free layer 120.

In some implementations, in order to effectively aid the crystal growth of the under layer 110 including the rare earth metal nitride, the buffer layer 105 may be formed of or include a material having an hexagonal close packed (HCP) crystal structure or a material having a wurtzite crystal structure.

The material having an HCP crystal structure may be or include one or more selected from a group consisting of hafnium (Hf), magnesium (Mg), zinc (Zn), zirconium (Zr), titanium (Ti), beryllium (Be), cadmium (Cd), ruthenium (Ru) and osmium (Os), but is not limited thereto.

The material having a wurtzite crystal structure may be or include one or more selected from a group consisting of aluminum nitride (AlN), silver iodide (AgI), zinc oxide (ZnO), cadmium sulfide (CdS), cadmium selenide (CdSe), silicon carbide (SiC), gallium nitride (GaN) and boron nitride (BN), but is not limited thereto.

The buffer layer 105 may have a single-layer or multilayer structure.

As shown in FIG. 1, the buffer layer 105 may have a single-layer structure including one or more of the material having a HCP crystal structure or the material having a wurtzite crystal structure.

As shown in FIG. 2, the buffer layer 105 may have a multilayer structure including a first buffer layer 101 and a second buffer layer 102. In some implementations, each of the first buffer layer 101 and the second buffer layer 102 may be formed of or include one or more the material having a HCP crystal structure or the material having a wurtzite crystal structure. Alternatively, any one layer of the first buffer layer 101 and the second buffer layer 102 may be formed of or include the material having a HCP crystal structure, and the other layer may include the material having a wurtzite crystal structure.

In some implementations, when the buffer layer 105 including the material having a HCP crystal structure or the material having a wurtzite crystal structure is formed under the under layer 110 including the rare earth metal nitride, it has been experimentally confirmed that characteristics required for the MTJ structure can be further improved. In particular, by selecting a combination of the specific materials included in the under layer 110 and the buffer layer 105 as described above, it is possible to improve the crystal orientation at an interface between the under layer 110 and the free layer 120, and thus increase the perpendicular magnetic anisotropy of the free layer 120 disposed over the under layer 110. This will be further described below with reference to FIG. 3.

The magnetic correction layer 160 may serve to offset or reduce the effect of the stray magnetic field produced by the pinned layer 140. In this case, the effect of the stray magnetic field of the pinned layer 140 on the free layer 120 can be decreased, and thus a biased magnetic field in the free layer 120 can decrease. The magnetic correction layer 160 may have a magnetization direction anti-parallel to the magnetization direction of the pinned layer 140. For example, when the pinned layer 140 has a downward magnetization direction, the magnetic correction layer 160 may have an upward magnetization direction. In contrary, when the pinned layer 140 has an upward magnetization direction, the magnetic correction layer 160 may have a downward magnetization direction. The magnetic correction layer 160 may have a single-layer or multilayer structure including a ferromagnetic material.

In the illustrated implementation of FIG. 1, the magnetic correction layer 160 is located above the pinned layer 140 and adjacent to the spacer layer 150. It is noted, however, that the position of the magnetic correction layer may be changed. For example, the magnetic correction layer 160 may be located below the MTJ structure. In another implementation, the magnetic correction layer 160 may be located next to the MTJ structure while it is patterned separately from the MTJ structure.

The spacer layer 150 may be interposed between the magnetic correction layer 160 and the pinned layer 140 and function as a buffer therebetween. In addition, the spacer layer 150 may serve to improve characteristics of the magnetic correction layer 160. The spacer layer 150 may include a noble metal such as ruthenium (Ru).

The capping layer 170 may function as a hard mask for patterning the variable resistance element 100 and may be formed of or include various conductive materials such as a metal. In particular, the capping layer 170 may be formed of a metallic material having few pin holes in the layer and high resistance to a wet and/or dry etch. For example, the capping layer 170 may include a noble metal such as ruthenium (Ru).

In the implementation as described above, the free layer 120 is formed under the pinned layer 140. However, it is noted that it is possible to form the free layer 120 over the pinned layer 140.

Hereinafter, the advantages of an implementation of the variable resistance element 100 wherein the under layer 110 including the rare earth metal nitride is formed under the free layer 120 and the buffer layer 105 including one or more of the material having a HCP crystal structure and the material having a wurtzite crystal structure is formed under the under layer 110 will be described in more detail with reference to FIG. 3.

FIG. 3 is a graph illustrating perpendicular magnetic anisotropy of the free layer of three examples of a variable resistance element formed in accordance with the structure of the implementation of FIG. 1 and of free layer of a conventional structure as a comparative example. The horizontal axis represents the value obtained by multiplying the normalized saturation magnetization (Ms) by the thickness (t) of the free saturation magnetization by the thickness of the free layer. The vertical axis represents the value of the normalized perpendicular magnetic anisotropy field. Ms means a value of saturation magnetization and Hk means a value of perpendicular magnetic anisotropy field. In accordance with the comparative example, the variable resistance element has substantially the same structure as the variable resistance element 100 shown in FIG. 1 except that an under layer 110 is formed of a single layer of tungsten and a buffer layer 105 is formed of a single layer of tungsten. In accordance with the Example 1, the variable resistance element includes an under layer 110 formed of GdN under the free layer 120 and a buffer layer 105 formed of HfB under the under layer 110. In accordance with the Example 2, the variable resistance element includes an under layer 110 formed of GdN under the free layer 120 and a buffer layer 105 formed of Hf under the under layer 110. In accordance with the Example 3, the variable resistance element includes an under layer 110 formed of GdN under the free layer 120 and a buffer layer 105 formed of AlN under the under layer 110.

Referring to FIG. 3, it can be shown that the Hk values of the free layer in accordance with the aforementioned implementations are significantly increased in comparison to that of the free layer in accordance with the comparative example. That is, the perpendicular magnetic anisotropy of the free layer in accordance with the aforementioned implementations of the present disclosure can be increased. As a result, the thermal stability of the free layer in accordance with the aforementioned implementations can be improved. For reference, the thermal conductivity Δ may be represented by the below formula (1):

Δ=Ms*t*S*Hk2kBT(1)

where Ms represents saturation magnetization of the free layer, t represents the thickness of the free layer, Hk represents perpendicular magnetic anisotropy field of the free layer, S represents the area of the free layer, kB represents the Boltzmann constant, and T represents the temperature.

Referring to the formula (1), since the thermal stability is proportional to the Hk value of the free layer, if the Hk value is increased, then the thermal stability may be increased.

As such, in the variable resistance element 100, the under layer 110 including the rare earth metal nitride is formed under the free layer 120 and the buffer layer 105 including one or more of the material having a HCP crystal structure or material having a wurtzite crystal structure is formed under the under layer 110, so that the crystal orientation at an interface between the under layer 110 and the free layer 120 can be increased, and thus the high perpendicular magnetic anisotropy and the thermal stability of the free layer 120 can be secured. As a result, it is possible to improve data storage characteristics and operation characteristics of the variable resistance element 100.

The variable resistance elements in accordance with the aforementioned implementations, for example, a plurality of the variable resistance elements 100 shown in FIGS. 1 and 2 may be provided to form a cell array. The cell array may include various components such as lines, elements, etc. to drive or control each variable resistance element 100. This will be exemplarily described with reference to FIGS. 4 and 5.

FIG. 4 is a cross-sectional view illustrating a memory device and a method for fabricating the same in accordance with an implementation of the present disclosure.

Referring to FIG. 4, the memory device of this implementation may include a substrate 400, a lower contact 420 formed over the substrate 400, a variable resistance element 100 formed over the substrate 400 and an upper contact 450 formed over the substrate 400. For each variable resistance element 100, a specific structure as a switch or switching circuit/element, for example, a transistor, for controlling an access to a particular variable resistance element 100 may be provided over the substrate 400. The lower contact 420 may be disposed over the substrate 400, and couple a lower end of the variable resistance element 100 with a portion of the substrate 400, for example, a drain of the transistor as the switching circuit for the variable resistance element 100. The upper contact 450 may be disposed over the variable resistance element 100, and couple an upper end of the variable resistance element 100 with a certain line (not shown), for example, a bit line.

The above memory device may be fabricated by the following processes.

First, the substrate 400 in which the transistor is formed may be provided, and then a first interlayer dielectric layer 410 may be formed over the substrate 400. Second, the lower contact 420 may be formed by selectively etching the first interlayer dielectric layer 410 to form a hole H exposing a portion of the substrate 400 and filling the hole H with a conductive material. Third, the variable resistance element 100 may be formed by forming material layers for the variable resistance element 100 over the first interlayer dielectric layer 410 and the lower contact 420 and selectively etching the material layers. The etching process for forming the variable resistance element 100 may include an ion-beam evaporation (IBE) method which has a strong physical etching characteristic. Fourth, a second interlayer dielectric layer 430 may be formed by filling the space between the variable resistance elements 100 with an insulating material. Finally, a third interlayer dielectric layer 440 may be formed over the variable resistance element 100 and the second interlayer dielectric layer 430, and then the upper contact 450 passing through the third interlayer dielectric layer 440 and coupled to an upper end of the variable resistance element 100 may be formed.

In the memory device in accordance with this implementation, all layers forming the variable resistance element 100 may have sidewalls which are aligned with each other. That is because the variable resistance element 100 is formed through an etching process using one mask.

Unlike the implementation of FIG. 4, a part of the variable resistance element 100 may be patterned separately from other parts. This process is illustrated in FIG. 5.

FIG. 5 is a cross-sectional view illustrating a memory device and a method for fabricating the same in accordance with another implementation of the present disclosure.

Referring to FIG. 5, the memory device of this implementation may include the variable resistance element 100 of which parts, for example, the buffer layer 105 and the under layer 110 have sidewalls that are not aligned with the other layers thereof. Specifically, as shown in FIG. 5, the buffer layer 105 and the under layer 110 may have sidewalls which are aligned with the sidewalls of a lower contact 520.

The memory device in FIG. 5 may be fabricated by the following processes.

First, a first interlayer dielectric layer 510 may be formed over a substrate 500, and then selectively etched to form a hole H which exposes a part of the substrate 500. Second, the lower contact 520 filling the lower portion of the hole H may be formed. More specifically, the lower contact 520 may be formed through a series of processes of forming a conductive material to cover the resultant structure having the hole H formed therein, and removing a part of the conductive material through an etch back process or the like until the conductive material has a desired thickness. Third, the buffer layer 105 and the under layer 110 may be formed to fill the remaining portion of the hole H having the lower contact 520 formed therein. More specifically, the buffer layer 105 may be formed through a series of processes of forming a material layer for the buffer layer 105 to cover the resultant structure in which the lower contact 520 is formed, and removing a portion of the material layer by performing an etch back process or the like until the material layer has a desired thickness. Fourth, the under layer 110 may be formed through a series of processes of forming a material layer for the first interlayer dielectric layer 510 to cover the resultant structure in which the lower contact 520 and the buffer layer 105 are formed, and performing a planarization process, for example, a chemical mechanical polishing (CMP) process until the top surface of the first interlayer dielectric layer 510 is exposed. Subsequently, the other layers of the variable resistance element 100 may be formed by forming material layers for forming the other layers of the variable resistance element 100 except for the buffer layer 105 and the under layer 110 over the lower contact 520 and the first interlayer dielectric layer 510 and then selectively etching the material layers. The subsequent processes may be performed in substantially the same manner as described with reference to FIG. 4.

In this implementation, the height which needs to be etched at a time in order to form the variable resistance element 100 can be reduced, which makes it possible to lower the difficulty level of the etching process.

Although in this implementation, the buffer layer 105 and the under layer 110 are buried in the hole H, other parts may also be buried as needed.

The above and other memory circuits or semiconductor devices based on the disclosed technology can be used in a range of devices or systems. FIGS. 6 to 10 provide some examples of devices or systems that can implement the memory circuits disclosed herein.

FIG. 6 is a diagram illustrating a

FIG. 6 is an example of configuration diagram of a microprocessor implementing memory circuitry based on the disclosed technology.

Referring to FIG. 6, a microprocessor 1000 may perform tasks for controlling and tuning a series of processes of receiving data from various external devices, processing the data, and outputting processing results to external devices. The microprocessor 1000 may include a memory unit 1010, an operation unit 1020, a control unit 1030, and so on. The microprocessor 1000 may be various data processing units such as a central processing unit (CPU), a graphic processing unit (GPU), a digital signal processor (DSP) and an application processor (AP).

The memory unit 1010 is a part which stores data in the microprocessor 1000, as a processor register, register or the like. The memory unit 1010 may include a data register, an address register, a floating point register and so on. Besides, the memory unit 1010 may include various registers. The memory unit 1010 may perform the function of temporarily storing data for which operations are to be performed by the operation unit 1020, result data of performing the operations and addresses where data for performing of the operations are stored.

The memory unit 1010 may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the memory unit 1010 may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer which is in contact with the free layer and includes a rare earth metal nitride. Through this, data storage characteristics of the memory unit 1010 may be improved. As a consequence, operating characteristics of the microprocessor 1000 may be improved.

The operation unit 1020 may perform four arithmetical operations or logical operations according to results that the control unit 1030 decodes commands. The operation unit 1020 may include at least one arithmetic logic unit (ALU) and so on.

The control unit 1030 may receive signals from the memory unit 1010, the operation unit 1020 and an external device of the microprocessor 1000, perform extraction, decoding of commands, and controlling input and output of signals of the microprocessor 1000, and execute processing represented by programs.

The microprocessor 1000 according to this implementation may additionally include a cache memory unit 1040 which can temporarily store data to be inputted from an external device other than the memory unit 1010 or to be outputted to an external device. In this case, the cache memory unit 1040 may exchange data with the memory unit 1010, the operation unit 1020 and the control unit 1030 through a bus interface 1050.

FIG. 7 is an example of configuration diagram of a processor implementing memory circuitry based on the disclosed technology.

Referring to FIG. 7, a processor 1100 may improve performance and realize multi-functionality by including various functions other than those of a microprocessor which performs tasks for controlling and tuning a series of processes of receiving data from various external devices, processing the data, and outputting processing results to external devices. The processor 1100 may include a core unit 1110 which serves as the microprocessor, a cache memory unit 1120 which serves to storing data temporarily, and a bus interface 1130 for transferring data between internal and external devices. The processor 1100 may include various system-on-chips (SoCs) such as a multi-core processor, a graphic processing unit (GPU) and an application processor (AP).

The core unit 1110 of this implementation is a part which performs arithmetic logic operations for data inputted from an external device, and may include a memory unit 1111, an operation unit 1112 and a control unit 1113.

The memory unit 1111 is a part which stores data in the processor 1100, as a processor register, a register or the like. The memory unit 1111 may include a data register, an address register, a floating point register and so on. Besides, the memory unit 1111 may include various registers. The memory unit 1111 may perform the function of temporarily storing data for which operations are to be performed by the operation unit 1112, result data of performing the operations and addresses where data for performing of the operations are stored. The operation unit 1112 is a part which performs operations in the processor 1100. The operation unit 1112 may perform four arithmetical operations, logical operations, according to results that the control unit 1113 decodes commands, or the like. The operation unit 1112 may include at least one arithmetic logic unit (ALU) and so on. The control unit 1113 may receive signals from the memory unit 1111, the operation unit 1112 and an external device of the processor 1100, perform extraction, decoding of commands, controlling input and output of signals of processor 1100, and execute processing represented by programs.

The cache memory unit 1120 is a part which temporarily stores data to compensate for a difference in data processing speed between the core unit 1110 operating at a high speed and an external device operating at a low speed. The cache memory unit 1120 may include a primary storage section 1121, a secondary storage section 1122 and a tertiary storage section 1123. In general, the cache memory unit 1120 includes the primary and secondary storage sections 1121 and 1122, and may include the tertiary storage section 1123 in the case where high storage capacity is required. As the occasion demands, the cache memory unit 1120 may include an increased number of storage sections. That is to say, the number of storage sections which are included in the cache memory unit 1120 may be changed according to a design. The speeds at which the primary, secondary and tertiary storage sections 1121, 1122 and 1123 store and discriminate data may be the same or different. In the case where the speeds of the respective storage sections 1121, 1122 and 1123 are different, the speed of the primary storage section 1121 may be largest. At least one storage section of the primary storage section 1121, the secondary storage section 1122 and the tertiary storage section 1123 of the cache memory unit 1120 may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the cache memory unit 1120 may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer which is in contact with the free layer and includes a rare earth metal nitride. Through this, data storage characteristics of the cache memory unit 1120 may be improved. As a consequence, operating characteristics of the processor 1100 may be improved.

Although it was shown in FIG. 7 that all the primary, secondary and tertiary storage sections 1121, 1122 and 1123 are configured inside the cache memory unit 1120, it is to be noted that all the primary, secondary and tertiary storage sections 1121, 1122 and 1123 of the cache memory unit 1120 may be configured outside the core unit 1110 and may compensate for a difference in data processing speed between the core unit 1110 and the external device. Meanwhile, it is to be noted that the primary storage section 1121 of the cache memory unit 1120 may be disposed inside the core unit 1110 and the secondary storage section 1122 and the tertiary storage section 1123 may be configured outside the core unit 1110 to strengthen the function of compensating for a difference in data processing speed. In another implementation, the primary and secondary storage sections 1121, 1122 may be disposed inside the core units 1110 and tertiary storage sections 1123 may be disposed outside core units 1110.

The bus interface 1130 is a part which connects the core unit 1110, the cache memory unit 1120 and external device and allows data to be efficiently transmitted.

The processor 1100 according to this implementation may include a plurality of core units 1110, and the plurality of core units 1110 may share the cache memory unit 1120. The plurality of core units 1110 and the cache memory unit 1120 may be directly connected or be connected through the bus interface 1130. The plurality of core units 1110 may be configured in the same way as the above-described configuration of the core unit 1110. In the case where the processor 1100 includes the plurality of core unit 1110, the primary storage section 1121 of the cache memory unit 1120 may be configured in each core unit 1110 in correspondence to the number of the plurality of core units 1110, and the secondary storage section 1122 and the tertiary storage section 1123 may be configured outside the plurality of core units 1110 in such a way as to be shared through the bus interface 1130. The processing speed of the primary storage section 1121 may be larger than the processing speeds of the secondary and tertiary storage section 1122 and 1123. In another implementation, the primary storage section 1121 and the secondary storage section 1122 may be configured in each core unit 1110 in correspondence to the number of the plurality of core units 1110, and the tertiary storage section 1123 may be configured outside the plurality of core units 1110 in such a way as to be shared through the bus interface 1130.

The processor 1100 according to this implementation may further include an embedded memory unit 1140 which stores data, a communication module unit 1150 which can transmit and receive data to and from an external device in a wired or wireless manner, a memory control unit 1160 which drives an external memory device, and a media processing unit 1170 which processes the data processed in the processor 1100 or the data inputted from an external input device and outputs the processed data to an external interface device and so on. Besides, the processor 1100 may include a plurality of various modules and devices. In this case, the plurality of modules which are added may exchange data with the core units 1110 and the cache memory unit 1120 and with one another, through the bus interface 1130.

The embedded memory unit 1140 may include not only a volatile memory but also a nonvolatile memory. The volatile memory may include a DRAM (dynamic random access memory), a mobile DRAM, an SRAM (static random access memory), and a memory with similar functions to above mentioned memories, and so on. The nonvolatile memory may include a ROM (read only memory), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), a memory with similar functions.

The communication module unit 1150 may include a module capable of being connected with a wired network, a module capable of being connected with a wireless network and both of them. The wired network module may include a local area network (LAN), a universal serial bus (USB), an Ethernet, power line communication (PLC) such as various devices which send and receive data through transmit lines, and so on. The wireless network module may include Infrared Data Association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), a wireless LAN, Zigbee, a ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), a wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), wideband CDMA (WCDMA), ultra wideband (UWB) such as various devices which send and receive data without transmit lines, and so on.

The memory control unit 1160 is to administrate and process data transmitted between the processor 1100 and an external storage device operating according to a different communication standard. The memory control unit 1160 may include various memory controllers, for example, devices which may control IDE (Integrated Device Electronics), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), RAID (Redundant Array of Independent Disks), an SSD (solid state disk), eSATA (External SATA), PCMCIA (Personal Computer Memory Card International Association), a USB (universal serial bus), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on.

The media processing unit 1170 may process the data processed in the processor 1100 or the data inputted in the forms of image, voice and others from the external input device and output the data to the external interface device. The media processing unit 1170 may include a graphic processing unit (GPU), a digital signal processor (DSP), a high definition audio device (HD audio), a high definition multimedia interface (HDMI) controller, and so on.

FIG. 8 is an example of configuration diagram of a system implementing memory circuitry based on the disclosed technology.

Referring to FIG. 8, a system 1200 as an apparatus for processing data may perform input, processing, output, communication, storage, etc. to conduct a series of manipulations for data. The system 1200 may include a processor 1210, a main memory device 1220, an auxiliary memory device 1230, an interface device 1240, and so on. The system 1200 of this implementation may be various electronic systems which operate using processors, such as a computer, a server, a PDA (personal digital assistant), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, a digital music player, a PMP (portable multimedia player), a camera, a global positioning system (GPS), a video camera, a voice recorder, a telematics, an audio visual (AV) system, a smart television, and so on.

The processor 1210 may decode inputted commands and processes operation, comparison, etc. for the data stored in the system 1200, and controls these operations. The processor 1210 may include a microprocessor unit (MPU), a central processing unit (CPU), a single/multi-core processor, a graphic processing unit (GPU), an application processor (AP), a digital signal processor (DSP), and so on.

The main memory device 1220 is a storage which can temporarily store, call and execute program codes or data from the auxiliary memory device 1230 when programs are executed and can conserve memorized contents even when power supply is cut off. The main memory device 1220 may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the main memory device 1220 may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer which is in contact with the free layer and includes a rare earth metal nitride. Through this, data storage characteristics of the main memory device 1220 may be improved. As a consequence, operating characteristics of the system 1200 may be improved.

Also, the main memory device 1220 may further include a static random access memory (SRAM), a dynamic random access memory (DRAM), and so on, of a volatile memory type in which all contents are erased when power supply is cut off. Unlike this, the main memory device 1220 may not include the semiconductor devices according to the implementations, but may include a static random access memory (SRAM), a dynamic random access memory (DRAM), and so on, of a volatile memory type in which all contents are erased when power supply is cut off.

The auxiliary memory device 1230 is a memory device for storing program codes or data. While the speed of the auxiliary memory device 1230 is slower than the main memory device 1220, the auxiliary memory device 1230 can store a larger amount of data. The auxiliary memory device 1230 may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the auxiliary memory device 1230 may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer which is in contact with the free layer and includes a rare earth metal nitride. Through this, data storage characteristics of the auxiliary memory device 1230 may be improved. As a consequence, operating characteristics of the system 1200 may be improved.

Also, the auxiliary memory device 1230 may further include a data storage system (see the reference numeral 1300 of FIG. 9) such as a magnetic tape using magnetism, a magnetic disk, a laser disk using optics, a magneto-optical disc using both magnetism and optics, a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on. Unlike this, the auxiliary memory device 1230 may not include the semiconductor devices according to the implementations, but may include data storage systems (see the reference numeral 1300 of FIG. 9) such as a magnetic tape using magnetism, a magnetic disk, a laser disk using optics, a magneto-optical disc using both magnetism and optics, a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on.

The interface device 1240 may be to perform exchange of commands and data between the system 1200 of this implementation and an external device. The interface device 1240 may be a keypad, a keyboard, a mouse, a speaker, a mike, a display, various human interface devices (HIDs), a communication device, and so on. The communication device may include a module capable of being connected with a wired network, a module capable of being connected with a wireless network and both of them. The wired network module may include a local area network (LAN), a universal serial bus (USB), an Ethernet, power line communication (PLC), such as various devices which send and receive data through transmit lines, and so on. The wireless network module may include Infrared Data Association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), a wireless LAN, Zigbee, a ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), a wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), wideband CDMA (WCDMA), ultra wideband (UWB), such as various devices which send and receive data without transmit lines, and so on.

FIG. 9 is an example of configuration diagram of a data storage system implementing memory circuitry based on the disclosed technology.

Referring to FIG. 9, a data storage system 1300 may include a storage device 1310 which has a nonvolatile characteristic as a component for storing data, a controller 1320 which controls the storage device 1310, an interface 1330 for connection with an external device, and a temporary storage device 1340 for storing data temporarily. The data storage system 1300 may be a disk type such as a hard disk drive (HDD), a compact disc read only memory (CDROM), a digital versatile disc (DVD), a solid state disk (SSD), and so on, and a card type such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on.

The storage device 1310 may include a nonvolatile memory which stores data semi-permanently. The nonvolatile memory may include a ROM (read only memory), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), and so on.

The controller 1320 may control exchange of data between the storage device 1310 and the interface 1330. To this end, the controller 1320 may include a processor 1321 for performing an operation for, processing commands inputted through the interface 1330 from an outside of the data storage system 1300 and so on.

The interface 1330 is to perform exchange of commands and data between the data storage system 1300 and the external device. In the case where the data storage system 1300 is a card type, the interface 1330 may be compatible with interfaces which are used in devices, such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on, or be compatible with interfaces which are used in devices similar to the above mentioned devices. In the case where the data storage system 1300 is a disk type, the interface 1330 may be compatible with interfaces, such as IDE (Integrated Device Electronics), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), eSATA (External SATA), PCMCIA (Personal Computer Memory Card International Association), a USB (universal serial bus), and so on, or be compatible with the interfaces which are similar to the above mentioned interfaces. The interface 1330 may be compatible with one or more interfaces having a different type from each other.

The temporary storage device 1340 can store data temporarily for efficiently transferring data between the interface 1330 and the storage device 1310 according to diversifications and high performance of an interface with an external device, a controller and a system. The temporary storage device 1340 for temporarily storing data may include one or more of the above-described semiconductor devices in accordance with the implementations. The temporary storage device 1340 may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer which is in contact with the free layer and includes a rare earth metal nitride. Through this, data storage characteristics of the storage device 1310 or the temporary storage device 1340 may be improved. As a consequence, operating characteristics and data storage characteristics of the data storage system 1300 may be improved.

FIG. 10 is an example of configuration diagram of a memory system implementing memory circuitry based on the disclosed technology.

Referring to FIG. 10, a memory system 1400 may include a memory 1410 which has a nonvolatile characteristic as a component for storing data, a memory controller 1420 which controls the memory 1410, an interface 1430 for connection with an external device, and so on. The memory system 1400 may be a card type such as a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on.

The memory 1410 for storing data may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the memory 1410 may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer which is in contact with the free layer and includes a rare earth metal nitride. Through this, data storage characteristics of the memory 1410 may be improved. As a consequence, operating characteristics and data storage characteristics of the memory system 1400 may be improved.

Also, the memory 1410 according to this implementation may further include a ROM (read only memory), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), and so on, which have a nonvolatile characteristic.

The memory controller 1420 may control exchange of data between the memory 1410 and the interface 1430. To this end, the memory controller 1420 may include a processor 1421 for performing an operation for and processing commands inputted through the interface 1430 from an outside of the memory system 1400.

The interface 1430 is to perform exchange of commands and data between the memory system 1400 and the external device. The interface 1430 may be compatible with interfaces which are used in devices, such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on, or be compatible with interfaces which are used in devices similar to the above mentioned devices. The interface 1430 may be compatible with one or more interfaces having a different type from each other.

The memory system 1400 according to this implementation may further include a buffer memory 1440 for efficiently transferring data between the interface 1430 and the memory 1410 according to diversification and high performance of an interface with an external device, a memory controller and a memory system. For example, the buffer memory 1440 for temporarily storing data may include one or more of the above-described semiconductor devices in accordance with the implementations. The buffer memory 1440 may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer which is in contact with the free layer and includes a rare earth metal nitride. Through this, data storage characteristics of the buffer memory 1440 may be improved. As a consequence, operating characteristics and data storage characteristics of the memory system 1400 may be improved.

Moreover, the buffer memory 1440 according to this implementation may further include an SRAM (static random access memory), a DRAM (dynamic random access memory), and so on, which have a volatile characteristic, and a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), and so on, which have a nonvolatile characteristic. Unlike this, the buffer memory 1440 may not include the semiconductor devices according to the implementations, but may include an SRAM (static random access memory), a DRAM (dynamic random access memory), and so on, which have a volatile characteristic, and a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), and so on, which have a nonvolatile characteristic.

Features in the above examples of electronic devices or systems in FIGS. 6-10 based on the memory devices disclosed in this document may be implemented in various devices, systems or applications. Some examples include mobile phones or other portable communication devices, tablet computers, notebook or laptop computers, game machines, smart TV sets, TV set top boxes, multimedia servers, digital cameras with or without wireless communication functions, wrist watches or other wearable devices with wireless communication capabilities.

While this patent document contains many specifics, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this patent document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Moreover, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.

Only a few implementations and examples are described. Other implementations, enhancements and variations can be made based on what is described and illustrated in this patent document.

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Citation

Patents Cited in This Cited by
Title Current Assignee Application Date Publication Date
Semiconductor devices including reversible and one-time programmable magnetic tunnel junctions SAMSUNG ELECTRONICS CO., LTD. 14 October 2016 20 April 2017
스핀 전달 토크 자기 램의 응용들에 사용되는 희토류 자기 접합을 제공하는 방법 및 시스템 삼성전자주식회사 02 July 2015 13 January 2016
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