 (a): for an active vector with unidirectional switches S_{1m }and S_{1n }switched on, in Sectors I, III, V, turning on unidirectional switch S_{1x}, where x is chosen such that (m, x)=(1, 4), (3, 6), (5, 2); and in Sectors II, IV, VI, turning on unidirectional switch S_{1x}, where x is chosen such that (x, n)=(1, 4), (3, 6), (5, 2); orfor an active vector with unidirectional switches S_{2m }and S_{2n }switched on, in Sectors I, III, V, turning on unidirectional switch S_{2y}, where y is chosen such that (y, n)=(1, 4), (3, 6), (5, 2); and in Sectors II, IV, VI, turning on unidirectional switch S_{2y}, where y is chosen such that (m, y)=(1, 4), (3, 6), (5, 2); andstep
 (b): for the active vector with unidirectional switches S_{1m }and S_{1n }initially switched on, in Sectors I, III, V, turning off unidirectional switch S_{1n}; and in Sectors II, IV, VI, turning off unidirectional switch S_{1m}; orfor the active vector with unidirectional switches S_{2m }and S_{2n }initially switched on, in Sectors I, III, V, turning off unidirectional switch S_{2m}; in Sectors II, IV, VI, turning off unidirectional switch S_{2n}.
Apparatus and method of fast commutation for matrix converterbased rectifier
Updated Time 12 June 2019
Patent Registration DataPublication Number
US10153686
Application Number
US15/975827
Application Date
10 May 2018
Publication Date
11 December 2018
Current Assignee
MURATA MANUFACTURING CO., LTD.
Original Assignee (Applicant)
MURATA MANUFACTURING CO., LTD.
International Classification
H02M1/08,H02M7/155,H02M1/088,H02M7/162
Cooperative Classification
H02M1/088,H02M7/1623,H02M7/1552,H02M1/38,H02M5/293
Inventor
ZHAO, TAO,XU, DEWEI,AFSHARIAN, JAHANGIR,GONG, BING,YANG, ZHIHUA
Patent Images
This patent contains figures and images illustrating the invention and its embodiment.
Abstract
A method of commutation in a matrix rectifier from an active vector to a zero vector includes two steps. A method of commutation in a matrix rectifier from a zero vector to an active vector includes three steps.
Claims
1. A matrix rectifier comprising:
first, second, and third phases; and unidirectional switches S_{ij}, where i=1, 2 and j=1, 2, 3, 4, 5, 6 and where unidirectional switches S_{1j }and S_{2j }are connected together to define first, second, third, fourth, fifth, and sixth bidirectional switches; wherein first ends of the first, third, and fifth bidirectional switches are connected together to provide a positivevoltage node; first ends of the second, fourth, and sixth bidirectional switches are connected together to provide a negativevoltage node; second ends of the first and fourth bidirectional switches are connected to the first phase; second ends of the third and sixth bidirectional switches are connected to the second phase; second ends of the fifth and second bidirectional switches are connected to the third phase; a zero vector is defined by either unidirectional switches S_{1m }and S_{1n }switched on or unidirectional switches S_{2m }and S_{2n }switched on, where (m, n)=(1, 4), (3, 6), (5, 2), and by all other unidirectional switches S_{pq }switched off, where p≠m and q≠n; and an active vector is defined by either unidirectional switches S_{1m }and S_{1n }switched on or unidirectional switches S_{2m }and S_{2n }switched on, where m=1, 3, 5; n=2, 4, 6; and m, n are not connected to the same phase, and by all other unidirectional switches S_{pq }switched off, where p≠m and q≠n; Sectors I, II, III, IV, V, and VI are defined by using active vectors with (a, b)=(1, 6), (1, 2), (3, 2), (3, 4), (5, 4), and (5, 6); commutation from an active vector to a zero vector includes:step (a):
for an active vector with unidirectional switches S_{1m }and S_{1n }switched on,
in Sectors I, III, V, turning on unidirectional switch S_{1x}, where x is chosen such that (m, x)=(1, 4), (3, 6), (5, 2); and in Sectors II, IV, VI, turning on unidirectional switch S_{1x}, where x is chosen such that (x, n)=(1, 4), (3, 6), (5, 2); orfor an active vector with unidirectional switches S_{2m }and S_{2n }switched on,
in Sectors I, III, V, turning on unidirectional switch S_{2y}, where y is chosen such that (y, n)=(1, 4), (3, 6), (5, 2); and in Sectors II, IV, VI, turning on unidirectional switch S_{2y}, where y is chosen such that (m, y)=(1, 4), (3, 6), (5, 2); andstep (b):
for the active vector with unidirectional switches S_{1m }and S_{1n }initially switched on,
in Sectors I, III, V, turning off unidirectional switch S_{1n}; and in Sectors II, IV, VI, turning off unidirectional switch S_{1m}; orfor the active vector with unidirectional switches S_{2m }and S_{2n }initially switched on,
in Sectors I, III, V, turning off unidirectional switch S_{2m}; in Sectors II, IV, VI, turning off unidirectional switch S_{2n}.
2. The matrix rectifier of claim 1, wherein the commutation includes measuring input voltage and not measuring output current or output voltage.
3. The matrix rectifier of claim 1, wherein the first, second, third, fourth, fifth, and sixth bidirectional switches are modulated based on space vector modulation.
4. The matrix rectifier of claim 3, wherein gate signals s_{ij }applied to the unidirectional switches S_{ij }are generated by:
determining a spacevectormodulation sector; andgenerating:
a carrier signal; first, second, and third comparison signals based on dwell times of corresponding zero vector and two active vectors of the spacevectormodulation sector; modulation signals s_{j }corresponding to the first, second, third, fourth, fifth, and sixth bidirectional switches based on the comparison of the carrier signal and the first, second, and third comparison signals, where j=1, 2, 3, 4, 5, 6; and a first converter select signal SelectCon1 and a second converter select signal SelectCon2 based on if a positive or a negative voltage is outputted; whereinthe gate signals s_{ij }are generated based on:
s_{1j}=s_{j}×SelectCon1(j=1,3,5,4,6,2)
s_{2j}=s_{j}×SelectCon2(j=1,3,5,4,6,2).
5. A matrix rectifier comprising:
first, second, and third phases; and unidirectional switches S_{ij}, where i=1, 2 and j=1, 2, 3, 4, 5, 6 and where unidirectional switches S_{ij }and S_{2j }are connected together to define first, second, third, fourth, fifth, and sixth bidirectional switches; wherein first ends of the first, third, and fifth bidirectional switches are connected together to provide a positivevoltage node; first ends of the second, fourth, and sixth bidirectional switches are connected together to provide a negativevoltage node; second ends of the first and fourth bidirectional switches are connected to the first phase; second ends of the third and sixth bidirectional switches are connected to the second phase; second ends of the fifth and second bidirectional switches are connected to the third phase; a zero vector is defined by either unidirectional switches S_{1m }and S_{1n }switched on or unidirectional switches S_{2m }and S_{2n }switched on, where (m, n)=(1, 4), (3, 6), (5, 2), and by all other unidirectional switches S_{pq }switched off, where p≠m and q≠n; an active vector is defined by either unidirectional switches S_{1m }and S_{1n }switched on or unidirectional switches S_{2m }and S_{2n }switched on, where m=1, 3, 5; n=2, 4, 6; and m, n are not connected to the same phase, and by all other unidirectional switches S_{pq }switched off, where p≠m and q≠n; and Sectors I, II, III, IV, V, and VI are defined by using active vectors with (a, b)=(1, 6), (1, 2), (3, 2), (3, 4), (5, 4), and (5, 6); commutation from a zero vector to an active vector includes:step (a):
for a zero vector with unidirectional switches S_{1m }and S_{1n }switched on,
in Sectors I, III, V, turning on unidirectional switch S_{1x}, where x=1, 3, 5 and x is chosen such that a negative voltage is provided at the positivevoltage node; and in Sectors II, IV, VI, turning on unidirectional switch S_{1x}, where x=2, 4, 6 and x is chosen such that a positive voltage is provided at the negativevoltage node; orfor a zero vector with unidirectional switches S_{2m }and S_{2n }switched on,
in Sectors I, III, V, turning on unidirectional switch S_{2y}, where y=2, 4, 6 and y is chosen such that a positive voltage is provided at the negativevoltage node; and in Sectors II, IV, VI, turning on unidirectional switch S_{2y}, where y=1, 3, 5 and y is chosen such that a negative voltage is provided at the positivevoltage node;step (b):
for the zero vector with unidirectional switches S_{1m }and S_{1n }initially switched on,
in Sectors I, III, V, turning off unidirectional switch S_{1m}; and in Sectors II, IV, VI, turning off unidirectional switch S_{1n}; orfor the zero vector with unidirectional switches S_{2m }and S_{2n }initially switched on,
in Sectors I, III, V, turning off unidirectional switch S_{2n}; and in Sectors II, IV, VI, turning off unidirectional switch S_{2m}; andstep (c):
for the zero vector with unidirectional switches S_{1m }and S_{1n }initially switched on,
in Sectors I, III, V, turning off unidirectional switches S_{1x }and S_{1n }and turning on unidirectional switches S_{2x }and S_{2n}; and in Sectors II, IV, VI, turning off unidirectional switches S_{1x }and S_{1m }and turning on unidirectional switches S_{2x }and S_{2m}; orfor the zero vector with unidirectional switches S_{2m }and S_{2n }initially switched on,
in Sectors I, III, V, turning off unidirectional switches S_{2m }and S_{2y }and turning on unidirectional switches S_{1m }and S_{1y}; and in Sectors II, IV, VI, turning off unidirectional switches S_{2n }and S_{2y }and turning on unidirectional switches S_{1n }and S_{1y}.
6. The matrix rectifier of claim 5, wherein the commutation includes measuring input voltage and not measuring output current or output voltage.
7. The matrix rectifier of claim 5, wherein in step (a):
for the zero vector with unidirectional switches S_{1m }and S_{1n }initially switched on, no current passes through the unidirectional switch S_{1x}; or for the zero vector with unidirectional switches S_{2m }and S_{2n }initially switched on, no current passes through the unidirectional switch S_{2y}.
8. The matrix rectifier of claim 5, wherein step (b) continues until a current through the positivevoltage node or the negativevoltage node reaches zero.
9. The matrix rectifier of claim 5, further comprising a transformer connected to the positivevoltage and negativevoltage nodes; wherein
a holding time Δt of step (b) is provided by:
10. The matrix rectifier of claim 5, wherein the first, second, third, fourth, fifth, and sixth bidirectional switches are modulated based on space vector modulation.
11. The matrix rectifier of claim 10, wherein gate signals s_{ij }applied to the unidirectional switches S_{ij }are generated by:
determining a spacevectormodulation sector;generating:
a carrier signal; first, second, and third comparison signals based on dwell times of corresponding zero vector and two active vectors of the spacevectormodulation sector; modulation signals s_{j }corresponding to the first, second, third, fourth, fifth, and sixth bidirectional switches based on the comparison of the carrier signal and the first, second, and third comparison signals, where j=1, 2, 3, 4, 5, 6; and a first converter select signal SelectCon1 and a second converter select signal SelectCon2 based on if a positive or a negative voltage is outputted; whereinthe gate signals s_{ij }are generated based on:
s_{1j}=s_{j}×SelectCon1(j=1,3,5,4,6,2)
s_{2j}=s_{j}×SelectCon2(j=1,3,5,4,6,2).
Claim Tree

11. A matrix rectifier comprising: first, second, and third phases; and unidirectional switches S_{ij}, where i=1, 2 and j=1, 2, 3, 4, 5, 6 and where unidirectional switches S_{1j }and S_{2j }are connected together to define first, second, third, fourth, fifth, and sixth bidirectional switches; wherein first ends of the first, third, and fifth bidirectional switches are connected together to provide a positivevoltage node; first ends of the second, fourth, and sixth bidirectional switches are connected together to provide a negativevoltage node; second ends of the first and fourth bidirectional switches are connected to the first phase; second ends of the third and sixth bidirectional switches are connected to the second phase; second ends of the fifth and second bidirectional switches are connected to the third phase; a zero vector is defined by either unidirectional switches S_{1m }and S_{1n }switched on or unidirectional switches S_{2m }and S_{2n }switched on, where (m, n)=(1, 4), (3, 6), (5, 2), and by all other unidirectional switches S_{pq }switched off, where p≠m and q≠n; and an active vector is defined by either unidirectional switches S_{1m }and S_{1n }switched on or unidirectional switches S_{2m }and S_{2n }switched on, where m=1, 3, 5; n=2, 4, 6; and m, n are not connected to the same phase, and by all other unidirectional switches S_{pq }switched off, where p≠m and q≠n; Sectors I, II, III, IV, V, and VI are defined by using active vectors with (a, b)=(1, 6), (1, 2), (3, 2), (3, 4), (5, 4), and (5, 6); commutation from an active vector to a zero vector includes:step

2. The matrix rectifier of claim 1, wherein
 the commutation includes measuring input voltage and not measuring output current or output voltage.

3. The matrix rectifier of claim 1, wherein
 the first, second, third, fourth, fifth, and sixth bidirectional switches are modulated based on space vector modulation.


55. A matrix rectifier comprising: first, second, and third phases; and unidirectional switches S_{ij}, where i=1, 2 and j=1, 2, 3, 4, 5, 6 and where unidirectional switches S_{ij }and S_{2j }are connected together to define first, second, third, fourth, fifth, and sixth bidirectional switches; wherein first ends of the first, third, and fifth bidirectional switches are connected together to provide a positivevoltage node; first ends of the second, fourth, and sixth bidirectional switches are connected together to provide a negativevoltage node; second ends of the first and fourth bidirectional switches are connected to the first phase; second ends of the third and sixth bidirectional switches are connected to the second phase; second ends of the fifth and second bidirectional switches are connected to the third phase; a zero vector is defined by either unidirectional switches S_{1m }and S_{1n }switched on or unidirectional switches S_{2m }and S_{2n }switched on, where (m, n)=(1, 4), (3, 6), (5, 2), and by all other unidirectional switches S_{pq }switched off, where p≠m and q≠n; an active vector is defined by either unidirectional switches S_{1m }and S_{1n }switched on or unidirectional switches S_{2m }and S_{2n }switched on, where m=1, 3, 5; n=2, 4, 6; and m, n are not connected to the same phase, and by all other unidirectional switches S_{pq }switched off, where p≠m and q≠n; and Sectors I, II, III, IV, V, and VI are defined by using active vectors with (a, b)=(1, 6), (1, 2), (3, 2), (3, 4), (5, 4), and (5, 6); commutation from a zero vector to an active vector includes:step
 (a): for a zero vector with unidirectional switches S_{1m }and S_{1n }switched on, in Sectors I, III, V, turning on unidirectional switch S_{1x}, where x=1, 3, 5 and x is chosen such that a negative voltage is provided at the positivevoltage node; and in Sectors II, IV, VI, turning on unidirectional switch S_{1x}, where x=2, 4, 6 and x is chosen such that a positive voltage is provided at the negativevoltage node; orfor a zero vector with unidirectional switches S_{2m }and S_{2n }switched on, in Sectors I, III, V, turning on unidirectional switch S_{2y}, where y=2, 4, 6 and y is chosen such that a positive voltage is provided at the negativevoltage node; and in Sectors II, IV, VI, turning on unidirectional switch S_{2y}, where y=1, 3, 5 and y is chosen such that a negative voltage is provided at the positivevoltage node;step
 (b): for the zero vector with unidirectional switches S_{1m }and S_{1n }initially switched on, in Sectors I, III, V, turning off unidirectional switch S_{1m}; and in Sectors II, IV, VI, turning off unidirectional switch S_{1n}; orfor the zero vector with unidirectional switches S_{2m }and S_{2n }initially switched on, in Sectors I, III, V, turning off unidirectional switch S_{2n}; and in Sectors II, IV, VI, turning off unidirectional switch S_{2m}; andstep
 (c): for the zero vector with unidirectional switches S_{1m }and S_{1n }initially switched on, in Sectors I, III, V, turning off unidirectional switches S_{1x }and S_{1n }and turning on unidirectional switches S_{2x }and S_{2n}; and in Sectors II, IV, VI, turning off unidirectional switches S_{1x }and S_{1m }and turning on unidirectional switches S_{2x }and S_{2m}; orfor the zero vector with unidirectional switches S_{2m }and S_{2n }initially switched on, in Sectors I, III, V, turning off unidirectional switches S_{2m }and S_{2y }and turning on unidirectional switches S_{1m }and S_{1y}; and in Sectors II, IV, VI, turning off unidirectional switches S_{2n }and S_{2y }and turning on unidirectional switches S_{1n }and S_{1y}.

6. The matrix rectifier of claim 5, wherein
 the commutation includes measuring input voltage and not measuring output current or output voltage.

7. The matrix rectifier of claim 5, wherein
 in step (a): for the zero vector with unidirectional switches S_{1m }and S_{1n }initially switched on, no current passes through the unidirectional switch S_{1x}; or for the zero vector with unidirectional switches S_{2m }and S_{2n }initially switched on, no current passes through the unidirectional switch S_{2y}.

8. The matrix rectifier of claim 5, wherein
 step (b) continues until a current through the positivevoltage node or the negativevoltage node reaches zero.

9. The matrix rectifier of claim 5, further comprising
 a transformer connected to the positivevoltage and negativevoltage nodes

wherein
a holding time Δt of step (b) is provided by:
$\Delta \phantom{\rule{0.3em}{0.3ex}}t=\frac{{L}_{o}{L}_{1\mathrm{ma}\phantom{\rule{0.3em}{0.3ex}}x}}{{U}_{1m\phantom{\rule{0.3em}{0.3ex}}i\phantom{\rule{0.3em}{0.3ex}}n}}$ where I_{1max }is a maximum current of the matrix converter, U_{1min }is a minimum output voltage of the matrix converter, and L_{o }is a leakage inductance of the transformer.

10. The matrix rectifier of claim 5, wherein
 the first, second, third, fourth, fifth, and sixth bidirectional switches are modulated based on space vector modulation.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to matrix converters. More specifically, the present invention relates to fast commutation for the rectifiers of matrix converters.
2. Description of the Related Art
FIG. 1A is a circuit diagram showing the topology of a 3phaseto1phase matrix converter, and FIG. 1B is an equivalent circuit diagram of a portion of the 3phaseto1phase matrix converter shown in FIG. 1A. Each of the circuits shown in FIGS. 1A and 1B can be used either with known commutation methods discussed in this section or with the novel commutation methods according to the preferred embodiments of the present invention discussed in the Detailed Description of Preferred Embodiments section below.
In FIG. 1A, “line side” refers to the portion of the circuit on the lefthand side of the transformer T_{r }that is connected to the line voltages u_{a}, u_{b}, u_{c }for each of the phases A, B, C, and “load side” refers to the portion of the circuit on the righthand side of the transformer T_{r }that is connected to the output voltage u_{o}, i.e., the load. On the line side, the threephase AC current is combined into a singlephase AC current, and on the load side, the singlephase AC current is rectified by diodes D_{1 }to D_{4 }to provide DC current.
The isolated matrix rectifier of FIG. 1A includes filter inductors L_{f }and filter capacitors C_{f }that define a lineside filter that reduces the total harmonic distortion (THD), bidirectional switches S_{1 }to S_{6 }arranged in a bridge as a 3phaseto1phase matrix converter, a transformer T_{r }that provides highvoltage isolation between the lineside circuit and the loadside circuit, four diodes D_{1 }to D_{4 }arranged in a bridge to provide output rectification, an output inductor L_{o }and an output capacitor C_{o }that define a loadside filter for the output voltage. Bidirectional switches S_{1 }to S_{6 }are used in this isolated matrix rectifier to open or close the current path in either direction. As shown in FIG. 1A, the bidirectional switches S_{1 }to S_{6 }include two unidirectional switches connected in parallel. Thus, switch S_{i }in FIG. 1A corresponds to switches S_{1i }and S_{2i }in FIG. 1B, where i=1, 2, 3, 4, 5, 6.
As shown in FIG. 1A, the rectifier of the matrix converter preferably includes two parts: (1) a 3phaseto1phase matrix converter and (2) a diode rectifier. The matrix converter and the diode rectifier are isolated by a highfrequency transformer T_{r}. As shown in FIG. 1B, the matrix converter can be considered a reverse parallel connection of two currentsource rectifiers that are labeled as converter #1 and converter #2. Converter #1 can provide a positive voltage pulse and can be referred to as a positive rectifier, and converter #2 can provide a negative voltage pulse and can be referred to as a negative rectifier.
The controller of the matrix converter turns the switches S_{1 }to S_{6 }on and off to generate a desired output voltage u_{o}. One method for determining when and for how long the switches S_{1 }to S_{6 }are turned on is spacevector modulation (SVM). SVM is an algorithm for the pulsewidth modulation (PWM) of the switches S_{1 }to S_{6}. That is, SVM is used to determine when the bidirectional switches S_{1 }to S_{6 }should be turned on and off. The bidirectional switches S_{1 }to S_{6 }are controlled by digital signals, e.g., either ones or zeros. Typically, a one means the switch is on, and a zero means the switch is off. In PWM, the width of the on signal, controls how long a switch is turned on, i.e., modulated. Implementations of SVM are disclosed in U.S. Application No. 62/069,815, which is hereby incorporated by reference in its entirety.
For the matrix converter shown in FIG. 1A, the switching function S_{i }can be defined as
where S_{i }is the switching function for the i^{th }switch. For example, if S_{1}=1, then switch S_{1 }is on, and if S_{1}=0, then switch S_{1 }is off.
In FIG. 1A, only two switches can be turned on at the same time to define a single current path. For example, if switches S_{1 }and S_{6 }are on, a single current path is defined between phases A and B through the transformer T_{r}. If only two switches can conduct at the same time, with one switch in the top half of the bridge (S_{1}, S_{3}, S_{5}) and with the other switch in the bottom half of the bridge (S_{2}, S_{4}, S_{6}), then there are nine possible switching states as listed in Tables 1 and 2, including six active switching states and three zero switching states. In Table 1, line currents i_{a}, i_{b}, i_{c }are the currents in phases A, B, C, and the lineside current i_{p }is the current through the primary winding of the transformer T_{r}. In Table 2, the transformer turns ratio k is assumed to be 1 so that the inductor current i_{L }is equal to the lineside current i_{p}.
The matrixconverter's controller determines a reference current {right arrow over (I)}_{ref }and calculates the on and off times of the switches S_{1 }to S_{6 }to approximate the reference current {right arrow over (I)}_{ref }to produce the lineside currents i_{a}, i_{b}, and i_{c}. The reference current {right arrow over (I)}_{ref }preferably is sinusoidal with a fixed frequency and a fixed magnitude: {right arrow over (I)}_{ref}=I_{ref}e^{jθ}. The fixed frequency is preferably the same as the fixed frequency of each of the threephase i_{a}(t), i_{b}(t), and i_{c}(t) to reduce harmful reflections. The controller determines the magnitude of the reference current {right arrow over (I)}_{ref }to achieve a desired output voltage u_{o}. That is, the controller regulates the output voltage u_{o }by varying the magnitude of the reference current {right arrow over (I)}_{ref}. Varying the magnitude of the reference current {right arrow over (I)}_{ref }changes the on and off times of the switches S_{1 }to S_{6}.
The reference current {right arrow over (I)}_{ref }moves through the αβ plane shown in FIG. 14. The angle θ is defined as the angle between the aaxis and the reference current {right arrow over (I)}_{ref}. Thus, as the angle θ changes, the reference current {right arrow over (I)}_{ref }sweeps through the different sectors IVI.
The reference current {right arrow over (I)}_{ref }can be synthesized by using combinations of the active and zero vectors. As used herein “synthesized” means that the reference current {right arrow over (I)}_{ref }can be represented as a combination of the active and zero vectors. The active and zero vectors are stationary and do not move in the αβ plane as shown in FIG. 14. The vectors used to synthesize the reference current {right arrow over (I)}_{ref }change depending on which sector the reference current {right arrow over (I)}_{ref }is located. The active vectors are chosen by the active vectors defining the sector. The zero vector is chosen for each sector by determining which on switch the two active vectors have in common and choosing the zero vector that also includes the same on switch. Using the zero vectors allows the magnitude of the lineside current i_{p }to be adjusted.
For example, consider when the current reference {right arrow over (I)}_{ref }is in sector I. The active vectors {right arrow over (I)}_{1 }and {right arrow over (I)}_{2 }define sector I. The switch S_{1 }is on for both active vectors {right arrow over (I)}_{1 }and {right arrow over (I)}_{2}. The zero vector {right arrow over (I)}_{7 }also has the switch S_{1 }on. Thus, when the reference current {right arrow over (I)}_{ref }is located in sector I, the active vectors {right arrow over (I)}_{1 }and {right arrow over (I)}_{2 }and zero vector {right arrow over (I)}_{7 }are used to synthesize the reference current {right arrow over (I)}_{ref}, which provides the following equation, with the righthand side of the equation resulting from vector {right arrow over (I)}_{7 }being a zero vector with zero magnitude:
where T_{1}, T_{2}, and T_{0 }are the dwell times for the corresponding active switches and T_{s }is the sampling period.
The dwell time is the on time of the corresponding switches. For example, T_{1 }is the on time of the switches S_{1 }and S_{6 }for the active vector {right arrow over (I)}_{1}. Because the switch S_{1 }is on for each of vectors {right arrow over (I)}_{1}, {right arrow over (I)}_{2}, and {right arrow over (I)}_{7}, the switch S_{1 }is on during the entire sampling period T_{s}. The ratio T_{1}/T_{s }is the duty cycle for the switch S_{6 }during the sampling period T_{s}.
The sampling period T_{s }is typically chosen such that the reference current {right arrow over (I)}_{ref }is synthesized multiple times per sector. For example, the reference current {right arrow over (I)}_{ref}, can be synthesized twice per sector so that the reference current {right arrow over (I)}_{ref}, is synthesized twelve times per cycle, where one complete cycle is when the reference current {right arrow over (I)}_{ref }goes through sectors IVI.
The dwell times can be calculated using the amperesecond balancing principle, i.e., the product of the reference current {right arrow over (I)}_{ref}, and sampling period T_{s }equals the sum of the current vectors multiplied by the time interval of synthesizing space vectors. Assuming that the sampling period T_{s }is sufficiently small, the reference current {right arrow over (I)}_{ref }can be considered constant during the sampling period T_{5}. The reference current {right arrow over (I)}_{ref }can be synthesized by two adjacent active vectors and a zero vector. For example, when the reference current {right arrow over (I)}_{ref }is in sector I, the reference current {right arrow over (I)}_{ref }can be synthesized by vectors {right arrow over (I)}_{1}, {right arrow over (I)}_{2}, and {right arrow over (I)}_{7}. The amperesecond balancing equation is thus given by the following equations.
{right arrow over (I)}_{ref}T_{s}={right arrow over (I)}_{1}T_{1}+{right arrow over (I)}T_{2}+{right arrow over (I)}_{7}T_{7 }
T_{s}=T_{1}+T_{2}+T_{7 }
where T_{1}, T_{2}, and T_{7 }are the dwell times for the vectors {right arrow over (I)}_{1}, {right arrow over (I)}_{2}, and {right arrow over (I)}_{7 }and T_{s }is sampling time. Then the dwell times are given by
T_{1}=mT_{s }sin(π/6−θ)
T_{2}=mT_{s }sin(π/6+θ)
T_{7}=T_{s}−T_{1}−T_{2 }
where
θ is sector angle between current reference {right arrow over (I)}_{ref }and aaxis shown in FIG. 5, and k is the transformer turns ratio.
Because of the isolation provided by the transformer, the matrixconverter output voltage u_{1}(t) must alternate between positive and negative with high frequency to maintain the voltsec balance. Thus, the preferred vector sequence in every sampling period T_{s }is divided into eight segments as {right arrow over (I)}_{α}, {right arrow over (I)}_{0}, −{right arrow over (I)}_{β}, {right arrow over (I)}_{0}, −{right arrow over (I)}_{β}, {right arrow over (I)}_{0}, −{right arrow over (I)}_{α}, {right arrow over (I)}_{0}, where vectors {right arrow over (I)}_{α }and {right arrow over (I)}_{β }are active vectors and {right arrow over (I)}_{0 }is a zero vector. For example, in sector I, vectors {right arrow over (I)}_{α }and {right arrow over (I)}_{β }are active vectors {right arrow over (I)}_{1 }and {right arrow over (I)}_{2}, and vector {right arrow over (I)}_{0 }is zero vector {right arrow over (I)}_{7}. When converter #1 is active, a positive vector can be used, and when converter #2 is active, a negative vector can be used.
The waveforms of the matrixconverter output voltage u_{1}(t) and the matrixconverter output current i_{p}(t) during one sampling period T_{s }are shown in FIG. 5. In FIG. 5, the matrixconverter output voltage u_{1}(t) has three kinds of polarities:
 (1) u_{1}(t) has positive polarity between times to and t_{1 }and between times t_{4 }and t_{5}. These time intervals can be referred to as Pintervals. The current vector in a Pinterval can be referred to as a Pvector. Under the effect of a Pvector, the matrixconverter output current i_{p}(t) increases.
 (2) u_{1}(t) has negative polarity between times t_{2 }and t_{3 }and between times t_{6 }and t_{7}. These time intervals can be referred to as Nintervals. The current vector in a Ninterval can be referred to as a Nvector. Under the effect of an Nvector, the matrixconverter output current i_{p}(t) decreases.
 (3) u_{1}(t) is zero between times t_{1 }and t_{2}, between times t_{3 }and t_{4}, between times t_{5 }and t_{6}, and between times t_{7 }and t_{8}. These time intervals can be referred to as Zintervals. The current vector in a Zinterval can be referred to as a Zvector. Under the effect of a Zvector, the absolute value of the matrixconverter output current i_{p}(t) decreases at most to be zero, and the direction of the matrixconverter output current i_{p}(t) will not change during the Zinterval.
In one sampling period T_{s}, the eight intervals are in sequence: Pinterval, Zinterval, Ninterval, Zinterval, Pinterval, Zinterval, Ninterval, Zinterval. As shown in FIG. 5, there is a commutation between the different intervals.
Commutation refers to turning on and off of the switches to switch from one vector to another vector. Known commutation methods for matrix converters are 4step commutation methods based on either output current or input voltage. These known commutation methods are very complicated and require accurately measuring either the output current or the input voltage.
(1) Known 4Step CurrentBased Commutation
The 4step currentbased commutation measures the output current direction. The twophasetosinglephase matrix converter in FIG. 2 illustrates the problems with currentbased commutation. All the important commutations can be seen in the circuit shown in FIG. 2.
As an example, assume that switches S_{11 }and S_{21 }are initially on and the switches S_{13 }and S_{23 }are initially off so that current can flow in either direction in the bidirectional switch on the left side of FIG. 2 and assume that we want to turn off the bidirectional switch on the left side of FIG. 2 and turn on the bidirectional switch on the right side of FIG. 2. As shown in FIG. 3A, when the current i>0, the following four steps can be used:
 (1) switch S_{11 }turns off;
 (2) switch S_{23 }turns on;
 (3) switch S_{21 }turns off;
 (4) switch S_{13 }turns on.
As shown in FIG. 3B, when the current i<0, the following fourstep commuting method is possible:
 (1) switch S_{21 }turns off;
 (2) switch S_{13 }turn on;
 (3) switch S_{11 }turns off;
 (4) switch S_{23 }turns on.
(2) Known 4Step VoltageBased Commutation
Known 4step voltagebased commutation is similar to currentbased commutation. Assuming that switches S_{11 }and S_{21 }are on and switches S13 and S23 are off so that current can flow in either direction in the bidirectional switch on the left side of FIG. 2 and assume that the bidirectional switch on the left side of FIG. 2 is to be turned off, and the bidirectional switch on the right side of FIG. 2 is to be turned on. As shown in FIG. 4A, when voltage u_{a}>voltage u_{b}, the following four steps can be used:
 (1) switch S_{23 }turns on;
 (2) switch S_{21 }turns off;
 (3) switch S_{13 }turns on;
 (4) switch S_{11 }turns off.
As shown in FIG. 4B, when the voltage u_{a}<voltage u_{b}, the following four steps can be used:
 (1) switch S_{13 }turns on;
 (2) switch S_{11 }turns off;
 (3) switch S_{23 }turns on;
 (4) switch S_{21 }turns off.
Both current and voltagebased commutation methods have problems such as taking a very long time to complete commutation, requiring complicated logic circuitry to implement the commutation methods, and requiring accurate current or voltage measurements. The frequency using these known commutation methods is limited because of the long time it takes to complete the commutation.
SUMMARY OF THE INVENTION
To overcome the problems described above, preferred embodiments of the present invention provide fast commutation. Preferred embodiments of the present invention provide 2 or 3step commutation that achieves one or more of the following advantages:
 (1) shorter time to complete commutation.
 (2) no need to measure the output current or input voltage because, in a rectifierbased matrix converter, the primary current i_{p }of the transformer is well defined because the input power factor is unity, i.e. the lineside current and voltage are in the same phase.
 (3) easier implementation than known 4step commutation methods.
 (4) suitable for highfrequency applications.
A matrix rectifier that can be used with the preferred embodiments of the present invention includes first, second, and third phases; and unidirectional switches S_{ij}, where i=1, 2 and j=1, 2, 3, 4, 5, 6 and where unidirectional switches S_{ij }and S_{2j }are connected together to define first, second, third, fourth, fifth, and sixth bidirectional switches. First ends of the first, third, and fifth bidirectional switches are connected together to provide a positivevoltage node. First ends of the second, fourth, and sixth bidirectional switches are connected together to provide a negativevoltage node. Second ends of the first and fourth bidirectional switches are connected to the first phase. Second ends of the third and sixth bidirectional switches are connected to the second phase. Second ends of the fifth and second bidirectional switches are connected to the third phase. A zero vector is defined by either unidirectional switches S_{1m }and S_{1n }switched on or unidirectional switches S_{2m }and S_{2n }switched on, where (m, n)=(1, 4), (3, 6), (5, 2), and by all other unidirectional switches S_{pq }switched off, where p≠m and q≠n. An active vector is defined by either unidirectional switches S_{1m }and S_{1n }switched on or unidirectional switches S_{2m }and S_{2n }switched on, where m=1, 3, 5; n=2, 4, 6; and m, n are not connected to the same phase, and by all other unidirectional switches S_{pq }switched off, where p≠m and q≠n. Sectors I, II, III, IV, V, and VI are defined by using active vectors with (a, b)=(1, 6), (1, 2), (3, 2), (3, 4), (5, 4), and (5, 6).
According to a preferred embodiment of the present invention, a method of performing commutation in a matrix rectifier from an active vector to a zero vector includes
step (a):
 for an active vector with unidirectional switches S_{1m }and S_{1n }switched on,
 in Sectors I, III, V, turning on unidirectional switch S_{1x}, where x is chosen such that (m, x)=(1, 4), (3, 6), (5, 2); and
 in Sectors II, IV, VI, turning on unidirectional switch S_{1x}, where x is chosen such that (x, n)=(1, 4), (3, 6), (5, 2); or
 for an active vector with unidirectional switches S_{2m }and S_{2n }switched on,
 in Sectors I, III, V, turning on unidirectional switch S_{2y}, where y is chosen such that (y, n)=(1, 4), (3, 6), (5, 2); and
 in Sectors II, IV, VI, turning on unidirectional switch S_{2y}, where y is chosen such that (m, y)=(1, 4), (3, 6), (5, 2);
 for an active vector with unidirectional switches S_{1m }and S_{1n }switched on,
step (b):
 for the active vector with unidirectional switches S_{1m }and S_{1n }initially switched on,
 in Sectors I, III, V, turning off unidirectional switch S_{1n}; and
 in Sectors II, IV, VI, turning off unidirectional switch S_{1m}; or
 for the active vector with unidirectional switches S_{2m }and S_{2n }initially switched on,
 in Sectors I, III, V, turning off unidirectional switch S_{2m};
 in Sectors II, IV, VI, turning off unidirectional switch S_{2n}.
 for the active vector with unidirectional switches S_{1m }and S_{1n }initially switched on,
Commutation is preferably performed by measuring input voltage and without measuring output current or output voltage.
According to a preferred embodiment of the present invention, a method of operating a matrix rectifier includes performing commutation from an active vector to a zero vector using the commutation method according to various other preferred embodiments of the present invention and modulating the first, second, third, fourth, fifth, and sixth bidirectional switches based on space vector modulation.
According to a preferred embodiment of the present invention, a method of performing commutation in a matrix rectifier from a zero vector to an active vector includes:
step (a):
 for a zero vector with unidirectional switches S_{1m }and S_{1n }switched on,
 in Sectors I, III, V, turning on unidirectional switch S_{1x}, where x=1, 3, 5 and x is chosen such that a negative voltage is provided at the positivevoltage node; and
 in Sectors II, IV, VI, turning on unidirectional switch S_{1x}, where x=2, 4, 6 and x is chosen such that a positive voltage is provided at the negativevoltage node; or
 for a zero vector with unidirectional switches S_{2m }and S_{2n }switched on,
 in Sectors I, III, V, turning on unidirectional switch S_{2y}, where y=2, 4, 6 and y is chosen such that a positive voltage is provided at the negativevoltage node; and
 in Sectors II, IV, VI, turning on unidirectional switch S_{2y}, where y=1, 3, 5 and y is chosen such that a negative voltage is provided at the positivevoltage node;
 for a zero vector with unidirectional switches S_{1m }and S_{1n }switched on,
step (b):
 for the zero vector with unidirectional switches S_{1m }and S_{1n }initially switched on,
 in Sectors I, III, V, turning off unidirectional switch S_{1m}; and
 in Sectors II, IV, VI, turning off unidirectional switch S_{1n}; or
 for the zero vector with unidirectional switches S_{2m }and S_{2n }initially switched on,
 in Sectors I, III, V, turning off unidirectional switch S_{2n}; and
 in Sectors II, IV, VI, turning off unidirectional switch S_{2m}; and
 for the zero vector with unidirectional switches S_{1m }and S_{1n }initially switched on,
step (c):
 for the zero vector with unidirectional switches S_{1m }and S_{1n }initially switched on,
 in Sectors I, III, V, turning off unidirectional switches S_{1x }and S_{1n }and turning on unidirectional switches S_{2x }and S_{2n}; and
 in Sectors II, IV, VI, turning off unidirectional switches S_{1x }and S_{1m }and turning on unidirectional switches S_{2x }and S_{2m}; or
 for the zero vector with unidirectional switches S_{2m }and S_{2n }initially switched on,
 in Sectors I, III, V, turning off unidirectional switches S_{2m }and S_{2y }and turning on unidirectional switches S_{1m }and S_{1y}; and
 in Sectors II, IV, VI, turning off unidirectional switches S_{2n }and S_{2y }and turning on unidirectional switches S_{1n }and S_{1y}.
 for the zero vector with unidirectional switches S_{1m }and S_{1n }initially switched on,
Commutation is preferably performed by measuring input voltage and without measuring output current or output voltage. Preferably, in step (a), for the zero vector with unidirectional switches S_{1m }and S_{1n }initially switched on, no current passes through unidirectional switch S_{1x}; or for the zero vector with unidirectional switches S_{2m }and S_{2n }initially switched on, no current passes through unidirectional switch S_{2y}. Preferably, step (b) lasts until a current through the positivevoltage node or the negativevoltage node reaches zero. The method further preferably includes a transformer connected to the positivevoltage and negativevoltage nodes, where a holding time Δt of step (b) is provided by:
where I_{1max }is a maximum current of the matrix converter, U_{1min }is a minimum output voltage of the matrix converter, and L_{o }is a leakage inductance of the transformer.
According to a preferred embodiment of the present invention, a method of operating a matrix rectifier includes performing commutation from a zero vector to an active vector using the commutation method according to various other preferred embodiments of the present invention and modulating the first, second, third, fourth, fifth, and sixth bidirectional switches based on space vector modulation.
Preferably, gate signals s_{ij }applied to unidirectional switches S_{ij }are generated by determining a spacevectormodulation sector and generating:
 a carrier signal;
 first, second, and third comparison signals based on dwell times of corresponding zero vector and two active vectors of the spacevectormodulation sector;
 modulation signals s_{i }corresponding to the first, second, third, fourth, fifth, and sixth bidirectional switches based on the comparison of the carrier signal and the first, second, and third comparison signals, where i=1, 2, 3, 4, 5, 6;
 first converter select signal SelectCon1 and second converter select signal SelectCon2 based on if a positive or a negative voltage is outputted; wherein the gate signals s_{ij }are generated based on:
s_{1j}=s_{i}×SelectCon1(j=1,3,5,4,6,2)
S_{2j}=s_{i}×SelectCon2(j=1,3,5,4,6,2).
The above and other features, elements, characteristics, steps, and advantages of the present invention will become more apparent from the following detailed description of preferred embodiments of the present invention with reference to the attached drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1A and 1B are circuit diagrams of matrixconverters.
FIG. 2 is a circuit diagram of a twophasetosinglephase matrix converter.
FIGS. 3A and 3B show the steps of currentbased commutation.
FIGS. 4A and 4B show the steps of voltagebased commutation.
FIG. 5 shows the waveforms of the rectifier of a matrix converter.
FIG. 6 shows eight switching modes in one sampling period in sector I.
FIGS. 7A and 7B show 2step commutation from an active vector to a zero vector for a positive current in sector I.
FIGS. 8A and 8B show 3step commutation from a zero vector to an active vector.
FIG. 9 is a block diagram of gatesignal generator.
FIG. 10 shows SVMmodulation and commutation signals in one sampling period.
FIG. 11 shows gate signals in one sampling period in sector I.
FIG. 12 shows 2step commutation at time t_{2}.
FIG. 13 shows 3step commutation at time t_{3}.
FIG. 14 shows a currentspace vector hexagon.
FIG. 15 shows 2step commutation from an active vector to a zero vector for a negative current in sector I.
FIG. 16 shows 3step commutation from a zero vector to an active vector for a negative current in sector I.
FIG. 17 shows 2step commutation from an active vector to a zero vector for a positive current in sector II.
FIG. 18 shows 3step commutation from a zero vector to an active vector for a positive current in sector II.
FIG. 19 shows 2step commutation from an active vector to a zero vector for a negative current in sector II.
FIG. 20 shows 3step commutation from a zero vector to an active vector for a negative current in sector II.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
Preferred embodiments of the present invention improve the known fourstep commutation methods. Current commutation can ensure reliable operation. Because the rectifiers of 3phaseto1phase matrixconverters have a different structure compared to the rectifiers of known 3phaseto3phase matrix converters, rectifiers of a 3phaseto1phase matrixconverter can use a different currentbased commutation method, as discussed below.
As shown in FIG. 5, the matrixconverter output current i_{p}(t) is positive in adjacent P and Zintervals, except for the commutation area, and the matrixconverter output current i_{p}(t) is negative in adjacent N and Zintervals, except for the commutation area. During adjacent P and Zintervals, converter #1 works normally and converter #2 stops working, and in contrast, during adjacent N and Zintervals, converter #2 works normally and converter #1 stops working. Thus, there are eight switching modes in one sampling period exclusive of the commutation areas as shown in FIG. 6. In one sampling period, there are two types of currentbased commutations: (1) active vector (i.e., either Pvector or Nvector) to zero vector and (2) zero vector to active vector. A twostep activevectortozerovector commutation and a threestep zerovectortoactivevector commutation are discussed below.
(1) Active Vector to Zero Vector (PVector to ZVector or NVector to ZVector)
As seen in FIGS. 5 and 6, activevectortozerovector commutations include the commutations from mode 1 (Pvector) to mode 2 (Zvector), mode 3 (Nvector) to mode 4 (Zvector), mode 5 (Pvector) to mode 6 (Zvector), and mode 7 (Nvector) to mode 8 (Zvector). During activevectortozerovector commutation, the direction of the output current of the rectifier of the matrix converter does not change. Thus, activevectortozerovector commutation only adds an overlap time just as the commutation method of the currentsource inverter. The overlap time is added to make sure that the current can smoothly transition from one switch to another switch and that no overvoltage is induced during this transition. The overlap time is determined by the “turn on” and “turn off” speed of these two switches. For example, as shown in FIGS. 7A and 7B, the commutation from mode 1 to mode 2 only has two steps:
 (1) switch S_{14 }turns on, and
 (2) switch S_{16 }turns off.
Thus, commutation from an active vector to a zero vector is achieved. FIGS. 7A and 7B show an example of the 2step commutation from an active vector to a zero vector for a positive current in sector I. Similar commutation steps are performed in sectors III and V.
FIG. 15 shows a 2step commutation from an active vector to a zero vector for a negative current in sector I. The commutation steps include:
 (1) switch S_{21 }turns on, and
 (2) switch S_{23 }turns off.
Similar commutation steps are performed in sectors III and V.
FIG. 17 shows a 2step commutation from an active vector to a zero vector for a positive current in sector II. The commutation steps include:
 (3) switch S_{15 }turns on, and
 (4) switch S_{11 }turns off.
Similar commutation steps are performed in sectors IV and VI.
FIG. 19 shows a 2step commutation from an active vector to a zero vector for a negative current in sector II. The commutation steps include:
 (1) switch S_{22 }turns on, and
 (2) switch S_{24 }turns off.
Similar commutation steps are performed in sectors IV and VI.
(2) Zero Vector to Active Vector (ZVector to PVector or ZVector to NVector)
As seen in FIGS. 5 and 6, zerovectortoactivevector commutations include the commutations from mode 2 (Zvector) to mode 3 (Nvector), mode 4 (Zvector) to mode 5 (Pvector), mode 6 (Zvector) to mode 7 (Nvector), and mode 8 (Zvector) to mode 1 of the next sampling period (Pvector). During zerovectortoactivevector commutation, the direction of the output current of the rectifier of the matrix converter changes. Thus, zerovectortoactivevector commutation requires an additional step. For example, as shown in FIGS. 8A and 8B, the commutation from mode 2 to mode 3 in sector I includes three steps:
 (1) switch S_{15 }turns on. The purpose of this step is to provide a current path for the next step. Although switch S_{15 }is on in this step, there is no current passing through switch S_{15 }because the voltage u_{a }is larger than the voltage u_{c }and because the diode in series with the switch S_{15 }is reversed biased. The output vector is still the Zvector. The time span Δt_{1 }that this step maintains can be decided according to the overlap time of the currentsource inverter. The overlap time is added to make sure that the switch S_{15 }is on before switch S_{11 }turns off, considering the delay between the gate signals of the switches S_{11 }and S_{15}.
 (2) Switch S_{11 }turns off. After turning switch S_{11 }off, the output vector is substantially the Nvector, so the output current will be reduced sharply and reach zero quickly. This step should last long enough to ensure that the current reaches zero. The holding time Δt_{2 }of this step can be estimated by the maximum current I_{1max }of the matrix converter, the minimum output voltage U_{1min }of the matrix converter, and the leakage inductance L_{o }of the transformer:
 For simplicity, the holding time Δt_{2 }can be selected as a fixed value according to eq. (1). The holding time Δt_{2 }is determined by the transition time required for the output current to reach zero. The holding time Δt_{2 }based on eq. (1) is long enough to ensure that the current reaches zero under all the conditions.
 (3) Switches S_{15 }and S_{14 }turn off and switches S_{24 }and S_{24 }turn on.
Thus, commutation from a zero vector to an active vector is achieved. FIGS. 8A and 8B show an example of the 3step commutation from a zero vector to an active vector for a positive current in sector I. Similar commutation steps are performed in sectors III and V.
FIG. 16 shows a 3step commutation from a zero vector to an active vector for a negative current in sector I. The commutation steps include:
 (1) switch S_{22 }turns on,
 (2) switch S_{24 }turns off, and
 (3) switches S_{21 }and S_{22 }turn off and switches S_{11 }and S_{12 }turn on.
Similar commutation steps are performed in sectors III and V.
FIG. 18 shows a 3step commutation from a zero vector to an active vector for a positive current in sector II. The commutation steps include:
 (1) switch S_{16 }turns on,
 (2) switch S_{12 }turns off, and
 (3) switches S_{15 }and S_{16 }turn off and switches S_{25 }and S_{26 }turn on.
Similar commutation steps are performed in sectors IV and VI.
FIG. 20 shows a 3step commutation from a zero vector to an active vector for a negative current in sector II. The commutation steps include:
 (1) switch S_{23 }turns on,
 (2) switch S_{25 }turns off, and
 (3) switches S_{23 }and S_{22 }turn off and switches S_{13 }and S_{12 }turn on.
Similar commutation steps are performed in sectors IV and VI.
As shown in FIG. 10, the time periods (or “effective area” in FIG. 10) when only converter #1 is on and the time periods when only converter #2 is on are separate from each other. In FIG. 10, the signal SelectCon1 is 1 when converter #1 is on, i.e., the effective area for converter #1, and is 0 when converter #1 is off, i.e., the effective area for converter #2. Similarly, the signal SelectCon2 when converter #2 is on, i.e., the effective area for converter #2, and is 0 when converter #2 is off, i.e., the effective area for converter #1. As shown in FIG. 9, the following three steps can be used to achieve modulation and commutation.
(1) Generate the Signals S_{i }(i=1, 2, 3, 4, 5, 6)
Accordingly, a carrier signal and three compare value signals CMP0, CMP1, CMP2 are used to generate the SVM PWM signals S_{i}′ (i=1, 2, 3, 4, 5, 6). The compare values signals CMP0, CMP1, CMP2 are determined by the dwell time of each vector. After the holding time Δt_{1 }for the falling edge of signals S_{i}′ has lapsed, the signals S_{i }(i=1, 2, 3, 4, 5, 6) can be generated. The falling edge of signal S_{i }is delayed for holding time Δt_{1 }compared with the signal S_{i}′. An overlap time is added to the signals S_{1}, S_{3}, S_{5}, and S_{4}, S_{6}, S_{2 }just as in the commutation method of the currentsource inverter. In sector I, for example, the signals S_{1}, S_{3}, S_{5 }and S_{4}, S_{6}, S_{2 }are shown in FIG. 10.
(2) Generate Signal SelectCon1 and Signal SelectCon2
After comparison between the carrier signal and CMP1 and the delay Δt of both rising and falling edges, signal SelectCon1 can be generated, as shown in FIGS. 9 and 10. The fixed delay time Δt is based on the three steps of zerovectortoactivevector commutation. So the delay time Δt can be determined by eq. (2).
Δt=Δt_{1}+Δt_{2} (2)
where Δt_{1 }is the overlap time and Δt_{2 }is estimated by eq. (1).
(3) Generate Gate Signals S_{i1 }for Converter #1 and Gate Signals S_{i2 }for Converter #2
The gate signals S_{1j }for converter #1 can be generated by eq. (3), and the gate signals S_{2j }for converter #2 can be generated by eq. (4):
S_{1j}=S_{j}×SelectCon1(j=1,3,5,4,6,2) (3)
S_{2j}=S_{j}×SelectCon2(j=1,3,5,4,6,2) (4)
For example, in sector I, the gate signals S_{11}, S_{13}, S_{15}, S_{14}, S_{16}, and S_{12 }are generated for converter #1, and the gate signals S_{21}, S_{23}, S_{22}, S_{24}, S_{26}, and S_{22 }are generated for converter #1 as shown in FIG. 10.
FIGS. 1113 show the gate signals generated using a field programmable gate array (FPGA) to implement the method described above. FIG. 11 shows the gate signals for switches S_{1 }to S_{6 }in sector I. The time period from time t_{1 }to time t_{9 }is one sampling period T_{s}. Times t_{2}, t_{4}, t_{6}, and t_{8 }use 2step commutation, and times t_{1}, t_{2}, t_{3}, t_{7}, and t_{9 }use 3step commutation.
For example, at time t_{2}, the commutation from mode 1 to mode 2 (from active vector to zero vector) as shown in FIG. 7 is in two steps. The 2step commutation waveforms are shown in FIG. 12. At time t_{3}, the commutation from mode 2 to mode 3 (from zero vector to active vector) as shown in FIG. 8 is in three steps. The 3step commutation waveforms are shown in FIG. 13.
It should be understood that the foregoing description is only illustrative of the present invention. Various alternatives and modifications can be devised by those skilled in the art without departing from the present invention. Accordingly, the present invention is intended to embrace all such alternatives, modifications, and variances that fall within the scope of the appended claims.