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Patent Analysis of

Apparatus and method of fast commutation for matrix converter-based rectifier

Updated Time 12 June 2019

Patent Registration Data

Publication Number

US10153686

Application Number

US15/975827

Application Date

10 May 2018

Publication Date

11 December 2018

Current Assignee

MURATA MANUFACTURING CO., LTD.

Original Assignee (Applicant)

MURATA MANUFACTURING CO., LTD.

International Classification

H02M1/08,H02M7/155,H02M1/088,H02M7/162

Cooperative Classification

H02M1/088,H02M7/1623,H02M7/1552,H02M1/38,H02M5/293

Inventor

ZHAO, TAO,XU, DEWEI,AFSHARIAN, JAHANGIR,GONG, BING,YANG, ZHIHUA

Patent Images

This patent contains figures and images illustrating the invention and its embodiment.

US10153686 Apparatus fast 1 US10153686 Apparatus fast 2 US10153686 Apparatus fast 3
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Abstract

A method of commutation in a matrix rectifier from an active vector to a zero vector includes two steps. A method of commutation in a matrix rectifier from a zero vector to an active vector includes three steps.

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Claims

1. A matrix rectifier comprising:

first, second, and third phases; and uni-directional switches Sij, where i=1, 2 and j=1, 2, 3, 4, 5, 6 and where uni-directional switches S1j and S2j are connected together to define first, second, third, fourth, fifth, and sixth bi-directional switches; wherein first ends of the first, third, and fifth bidirectional switches are connected together to provide a positive-voltage node; first ends of the second, fourth, and sixth bidirectional switches are connected together to provide a negative-voltage node; second ends of the first and fourth bidirectional switches are connected to the first phase; second ends of the third and sixth bidirectional switches are connected to the second phase; second ends of the fifth and second bidirectional switches are connected to the third phase; a zero vector is defined by either uni-directional switches S1m and S1n switched on or uni-directional switches S2m and S2n switched on, where (m, n)=(1, 4), (3, 6), (5, 2), and by all other uni-directional switches Spq switched off, where p≠m and q≠n; and an active vector is defined by either uni-directional switches S1m and S1n switched on or uni-directional switches S2m and S2n switched on, where m=1, 3, 5; n=2, 4, 6; and m, n are not connected to the same phase, and by all other uni-directional switches Spq switched off, where p≠m and q≠n; Sectors I, II, III, IV, V, and VI are defined by using active vectors with (a, b)=(1, 6), (1, 2), (3, 2), (3, 4), (5, 4), and (5, 6); commutation from an active vector to a zero vector includes:step (a):

for an active vector with uni-directional switches S1m and S1n switched on,

in Sectors I, III, V, turning on uni-directional switch S1x, where x is chosen such that (m, x)=(1, 4), (3, 6), (5, 2); and in Sectors II, IV, VI, turning on uni-directional switch S1x, where x is chosen such that (x, n)=(1, 4), (3, 6), (5, 2); orfor an active vector with uni-directional switches S2m and S2n switched on,

in Sectors I, III, V, turning on uni-directional switch S2y, where y is chosen such that (y, n)=(1, 4), (3, 6), (5, 2); and in Sectors II, IV, VI, turning on uni-directional switch S2y, where y is chosen such that (m, y)=(1, 4), (3, 6), (5, 2); andstep (b):

for the active vector with uni-directional switches S1m and S1n initially switched on,

in Sectors I, III, V, turning off uni-directional switch S1n; and in Sectors II, IV, VI, turning off uni-directional switch S1m; orfor the active vector with uni-directional switches S2m and S2n initially switched on,

in Sectors I, III, V, turning off uni-directional switch S2m; in Sectors II, IV, VI, turning off uni-directional switch S2n.

2. The matrix rectifier of claim 1, wherein the commutation includes measuring input voltage and not measuring output current or output voltage.

3. The matrix rectifier of claim 1, wherein the first, second, third, fourth, fifth, and sixth bi-directional switches are modulated based on space vector modulation.

4. The matrix rectifier of claim 3, wherein gate signals sij applied to the uni-directional switches Sij are generated by:

determining a space-vector-modulation sector; andgenerating:

a carrier signal; first, second, and third comparison signals based on dwell times of corresponding zero vector and two active vectors of the space-vector-modulation sector; modulation signals sj corresponding to the first, second, third, fourth, fifth, and sixth bi-directional switches based on the comparison of the carrier signal and the first, second, and third comparison signals, where j=1, 2, 3, 4, 5, 6; and a first converter select signal SelectCon1 and a second converter select signal SelectCon2 based on if a positive or a negative voltage is outputted; whereinthe gate signals sij are generated based on:

s1j=sj×SelectCon1(j=1,3,5,4,6,2)

s2j=sj×SelectCon2(j=1,3,5,4,6,2).

5. A matrix rectifier comprising:

first, second, and third phases; and uni-directional switches Sij, where i=1, 2 and j=1, 2, 3, 4, 5, 6 and where uni-directional switches Sij and S2j are connected together to define first, second, third, fourth, fifth, and sixth bi-directional switches; wherein first ends of the first, third, and fifth bidirectional switches are connected together to provide a positive-voltage node; first ends of the second, fourth, and sixth bidirectional switches are connected together to provide a negative-voltage node; second ends of the first and fourth bidirectional switches are connected to the first phase; second ends of the third and sixth bidirectional switches are connected to the second phase; second ends of the fifth and second bidirectional switches are connected to the third phase; a zero vector is defined by either uni-directional switches S1m and S1n switched on or uni-directional switches S2m and S2n switched on, where (m, n)=(1, 4), (3, 6), (5, 2), and by all other uni-directional switches Spq switched off, where p≠m and q≠n; an active vector is defined by either uni-directional switches S1m and S1n switched on or uni-directional switches S2m and S2n switched on, where m=1, 3, 5; n=2, 4, 6; and m, n are not connected to the same phase, and by all other uni-directional switches Spq switched off, where p≠m and q≠n; and Sectors I, II, III, IV, V, and VI are defined by using active vectors with (a, b)=(1, 6), (1, 2), (3, 2), (3, 4), (5, 4), and (5, 6); commutation from a zero vector to an active vector includes:step (a):

for a zero vector with uni-directional switches S1m and S1n switched on,

in Sectors I, III, V, turning on uni-directional switch S1x, where x=1, 3, 5 and x is chosen such that a negative voltage is provided at the positive-voltage node; and in Sectors II, IV, VI, turning on uni-directional switch S1x, where x=2, 4, 6 and x is chosen such that a positive voltage is provided at the negative-voltage node; orfor a zero vector with uni-directional switches S2m and S2n switched on,

in Sectors I, III, V, turning on uni-directional switch S2y, where y=2, 4, 6 and y is chosen such that a positive voltage is provided at the negative-voltage node; and in Sectors II, IV, VI, turning on uni-directional switch S2y, where y=1, 3, 5 and y is chosen such that a negative voltage is provided at the positive-voltage node;step (b):

for the zero vector with uni-directional switches S1m and S1n initially switched on,

in Sectors I, III, V, turning off uni-directional switch S1m; and in Sectors II, IV, VI, turning off uni-directional switch S1n; orfor the zero vector with uni-directional switches S2m and S2n initially switched on,

in Sectors I, III, V, turning off uni-directional switch S2n; and in Sectors II, IV, VI, turning off uni-directional switch S2m; andstep (c):

for the zero vector with uni-directional switches S1m and S1n initially switched on,

in Sectors I, III, V, turning off uni-directional switches S1x and S1n and turning on uni-directional switches S2x and S2n; and in Sectors II, IV, VI, turning off uni-directional switches S1x and S1m and turning on uni-directional switches S2x and S2m; orfor the zero vector with uni-directional switches S2m and S2n initially switched on,

in Sectors I, III, V, turning off uni-directional switches S2m and S2y and turning on uni-directional switches S1m and S1y; and in Sectors II, IV, VI, turning off uni-directional switches S2n and S2y and turning on uni-directional switches S1n and S1y.

6. The matrix rectifier of claim 5, wherein the commutation includes measuring input voltage and not measuring output current or output voltage.

7. The matrix rectifier of claim 5, wherein in step (a):

for the zero vector with uni-directional switches S1m and S1n initially switched on, no current passes through the uni-directional switch S1x; or for the zero vector with uni-directional switches S2m and S2n initially switched on, no current passes through the uni-directional switch S2y.

8. The matrix rectifier of claim 5, wherein step (b) continues until a current through the positive-voltage node or the negative-voltage node reaches zero.

9. The matrix rectifier of claim 5, further comprising a transformer connected to the positive-voltage and negative-voltage nodes; wherein

a holding time Δt of step (b) is provided by: Δt=LoL1maxU1min where I1max is a maximum current of the matrix converter, U1min is a minimum output voltage of the matrix converter, and Lo is a leakage inductance of the transformer.

10. The matrix rectifier of claim 5, wherein the first, second, third, fourth, fifth, and sixth bi-directional switches are modulated based on space vector modulation.

11. The matrix rectifier of claim 10, wherein gate signals sij applied to the uni-directional switches Sij are generated by:

determining a space-vector-modulation sector;generating:

a carrier signal; first, second, and third comparison signals based on dwell times of corresponding zero vector and two active vectors of the space-vector-modulation sector; modulation signals sj corresponding to the first, second, third, fourth, fifth, and sixth bi-directional switches based on the comparison of the carrier signal and the first, second, and third comparison signals, where j=1, 2, 3, 4, 5, 6; and a first converter select signal SelectCon1 and a second converter select signal SelectCon2 based on if a positive or a negative voltage is outputted; whereinthe gate signals sij are generated based on:

s1j=sj×SelectCon1(j=1,3,5,4,6,2)

s2j=sj×SelectCon2(j=1,3,5,4,6,2).

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Claim Tree

  • 1
    1. A matrix rectifier comprising: first, second, and third phases; and uni-directional switches Sij, where i=1, 2 and j=1, 2, 3, 4, 5, 6 and where uni-directional switches S1j and S2j are connected together to define first, second, third, fourth, fifth, and sixth bi-directional switches; wherein first ends of the first, third, and fifth bidirectional switches are connected together to provide a positive-voltage node; first ends of the second, fourth, and sixth bidirectional switches are connected together to provide a negative-voltage node; second ends of the first and fourth bidirectional switches are connected to the first phase; second ends of the third and sixth bidirectional switches are connected to the second phase; second ends of the fifth and second bidirectional switches are connected to the third phase; a zero vector is defined by either uni-directional switches S1m and S1n switched on or uni-directional switches S2m and S2n switched on, where (m, n)=(1, 4), (3, 6), (5, 2), and by all other uni-directional switches Spq switched off, where p≠m and q≠n; and an active vector is defined by either uni-directional switches S1m and S1n switched on or uni-directional switches S2m and S2n switched on, where m=1, 3, 5; n=2, 4, 6; and m, n are not connected to the same phase, and by all other uni-directional switches Spq switched off, where p≠m and q≠n; Sectors I, II, III, IV, V, and VI are defined by using active vectors with (a, b)=(1, 6), (1, 2), (3, 2), (3, 4), (5, 4), and (5, 6); commutation from an active vector to a zero vector includes:step
    • (a): for an active vector with uni-directional switches S1m and S1n switched on, in Sectors I, III, V, turning on uni-directional switch S1x, where x is chosen such that (m, x)=(1, 4), (3, 6), (5, 2); and in Sectors II, IV, VI, turning on uni-directional switch S1x, where x is chosen such that (x, n)=(1, 4), (3, 6), (5, 2); orfor an active vector with uni-directional switches S2m and S2n switched on, in Sectors I, III, V, turning on uni-directional switch S2y, where y is chosen such that (y, n)=(1, 4), (3, 6), (5, 2); and in Sectors II, IV, VI, turning on uni-directional switch S2y, where y is chosen such that (m, y)=(1, 4), (3, 6), (5, 2); andstep
    • (b): for the active vector with uni-directional switches S1m and S1n initially switched on, in Sectors I, III, V, turning off uni-directional switch S1n; and in Sectors II, IV, VI, turning off uni-directional switch S1m; orfor the active vector with uni-directional switches S2m and S2n initially switched on, in Sectors I, III, V, turning off uni-directional switch S2m; in Sectors II, IV, VI, turning off uni-directional switch S2n.
    • 2. The matrix rectifier of claim 1, wherein
      • the commutation includes measuring input voltage and not measuring output current or output voltage.
    • 3. The matrix rectifier of claim 1, wherein
      • the first, second, third, fourth, fifth, and sixth bi-directional switches are modulated based on space vector modulation.
  • 5
    5. A matrix rectifier comprising: first, second, and third phases; and uni-directional switches Sij, where i=1, 2 and j=1, 2, 3, 4, 5, 6 and where uni-directional switches Sij and S2j are connected together to define first, second, third, fourth, fifth, and sixth bi-directional switches; wherein first ends of the first, third, and fifth bidirectional switches are connected together to provide a positive-voltage node; first ends of the second, fourth, and sixth bidirectional switches are connected together to provide a negative-voltage node; second ends of the first and fourth bidirectional switches are connected to the first phase; second ends of the third and sixth bidirectional switches are connected to the second phase; second ends of the fifth and second bidirectional switches are connected to the third phase; a zero vector is defined by either uni-directional switches S1m and S1n switched on or uni-directional switches S2m and S2n switched on, where (m, n)=(1, 4), (3, 6), (5, 2), and by all other uni-directional switches Spq switched off, where p≠m and q≠n; an active vector is defined by either uni-directional switches S1m and S1n switched on or uni-directional switches S2m and S2n switched on, where m=1, 3, 5; n=2, 4, 6; and m, n are not connected to the same phase, and by all other uni-directional switches Spq switched off, where p≠m and q≠n; and Sectors I, II, III, IV, V, and VI are defined by using active vectors with (a, b)=(1, 6), (1, 2), (3, 2), (3, 4), (5, 4), and (5, 6); commutation from a zero vector to an active vector includes:step
    • (a): for a zero vector with uni-directional switches S1m and S1n switched on, in Sectors I, III, V, turning on uni-directional switch S1x, where x=1, 3, 5 and x is chosen such that a negative voltage is provided at the positive-voltage node; and in Sectors II, IV, VI, turning on uni-directional switch S1x, where x=2, 4, 6 and x is chosen such that a positive voltage is provided at the negative-voltage node; orfor a zero vector with uni-directional switches S2m and S2n switched on, in Sectors I, III, V, turning on uni-directional switch S2y, where y=2, 4, 6 and y is chosen such that a positive voltage is provided at the negative-voltage node; and in Sectors II, IV, VI, turning on uni-directional switch S2y, where y=1, 3, 5 and y is chosen such that a negative voltage is provided at the positive-voltage node;step
    • (b): for the zero vector with uni-directional switches S1m and S1n initially switched on, in Sectors I, III, V, turning off uni-directional switch S1m; and in Sectors II, IV, VI, turning off uni-directional switch S1n; orfor the zero vector with uni-directional switches S2m and S2n initially switched on, in Sectors I, III, V, turning off uni-directional switch S2n; and in Sectors II, IV, VI, turning off uni-directional switch S2m; andstep
    • (c): for the zero vector with uni-directional switches S1m and S1n initially switched on, in Sectors I, III, V, turning off uni-directional switches S1x and S1n and turning on uni-directional switches S2x and S2n; and in Sectors II, IV, VI, turning off uni-directional switches S1x and S1m and turning on uni-directional switches S2x and S2m; orfor the zero vector with uni-directional switches S2m and S2n initially switched on, in Sectors I, III, V, turning off uni-directional switches S2m and S2y and turning on uni-directional switches S1m and S1y; and in Sectors II, IV, VI, turning off uni-directional switches S2n and S2y and turning on uni-directional switches S1n and S1y.
    • 6. The matrix rectifier of claim 5, wherein
      • the commutation includes measuring input voltage and not measuring output current or output voltage.
    • 7. The matrix rectifier of claim 5, wherein
      • in step (a): for the zero vector with uni-directional switches S1m and S1n initially switched on, no current passes through the uni-directional switch S1x; or for the zero vector with uni-directional switches S2m and S2n initially switched on, no current passes through the uni-directional switch S2y.
    • 8. The matrix rectifier of claim 5, wherein
      • step (b) continues until a current through the positive-voltage node or the negative-voltage node reaches zero.
    • 9. The matrix rectifier of claim 5, further comprising
      • a transformer connected to the positive-voltage and negative-voltage nodes
      • wherein a holding time Δt of step (b) is provided by: Δt=LoL1maxU1min where I1max is a maximum current of the matrix converter, U1min is a minimum output voltage of the matrix converter, and Lo is a leakage inductance of the transformer.
    • 10. The matrix rectifier of claim 5, wherein
      • the first, second, third, fourth, fifth, and sixth bi-directional switches are modulated based on space vector modulation.
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Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to matrix converters. More specifically, the present invention relates to fast commutation for the rectifiers of matrix converters.

2. Description of the Related Art

FIG. 1A is a circuit diagram showing the topology of a 3-phase-to-1-phase matrix converter, and FIG. 1B is an equivalent circuit diagram of a portion of the 3-phase-to-1-phase matrix converter shown in FIG. 1A. Each of the circuits shown in FIGS. 1A and 1B can be used either with known commutation methods discussed in this section or with the novel commutation methods according to the preferred embodiments of the present invention discussed in the Detailed Description of Preferred Embodiments section below.

In FIG. 1A, “line side” refers to the portion of the circuit on the left-hand side of the transformer Tr that is connected to the line voltages ua, ub, uc for each of the phases A, B, C, and “load side” refers to the portion of the circuit on the right-hand side of the transformer Tr that is connected to the output voltage uo, i.e., the load. On the line side, the three-phase AC current is combined into a single-phase AC current, and on the load side, the single-phase AC current is rectified by diodes D1 to D4 to provide DC current.

The isolated matrix rectifier of FIG. 1A includes filter inductors Lf and filter capacitors Cf that define a line-side filter that reduces the total harmonic distortion (THD), bi-directional switches S1 to S6 arranged in a bridge as a 3-phase-to-1-phase matrix converter, a transformer Tr that provides high-voltage isolation between the line-side circuit and the load-side circuit, four diodes D1 to D4 arranged in a bridge to provide output rectification, an output inductor Lo and an output capacitor Co that define a load-side filter for the output voltage. Bi-directional switches S1 to S6 are used in this isolated matrix rectifier to open or close the current path in either direction. As shown in FIG. 1A, the bi-directional switches S1 to S6 include two uni-directional switches connected in parallel. Thus, switch Si in FIG. 1A corresponds to switches S1i and S2i in FIG. 1B, where i=1, 2, 3, 4, 5, 6.

As shown in FIG. 1A, the rectifier of the matrix converter preferably includes two parts: (1) a 3-phase-to-1-phase matrix converter and (2) a diode rectifier. The matrix converter and the diode rectifier are isolated by a high-frequency transformer Tr. As shown in FIG. 1B, the matrix converter can be considered a reverse parallel connection of two current-source rectifiers that are labeled as converter #1 and converter #2. Converter #1 can provide a positive voltage pulse and can be referred to as a positive rectifier, and converter #2 can provide a negative voltage pulse and can be referred to as a negative rectifier.

The controller of the matrix converter turns the switches S1 to S6 on and off to generate a desired output voltage uo. One method for determining when and for how long the switches S1 to S6 are turned on is space-vector modulation (SVM). SVM is an algorithm for the pulse-width modulation (PWM) of the switches S1 to S6. That is, SVM is used to determine when the bi-directional switches S1 to S6 should be turned on and off. The bi-directional switches S1 to S6 are controlled by digital signals, e.g., either ones or zeros. Typically, a one means the switch is on, and a zero means the switch is off. In PWM, the width of the on signal, controls how long a switch is turned on, i.e., modulated. Implementations of SVM are disclosed in U.S. Application No. 62/069,815, which is hereby incorporated by reference in its entirety.

For the matrix converter shown in FIG. 1A, the switching function Si can be defined as

Si={1,Siturnon0,Siturnoffi[1,2,3,4,5,6]

where Si is the switching function for the ith switch. For example, if S1=1, then switch S1 is on, and if S1=0, then switch S1 is off.

In FIG. 1A, only two switches can be turned on at the same time to define a single current path. For example, if switches S1 and S6 are on, a single current path is defined between phases A and B through the transformer Tr. If only two switches can conduct at the same time, with one switch in the top half of the bridge (S1, S3, S5) and with the other switch in the bottom half of the bridge (S2, S4, S6), then there are nine possible switching states as listed in Tables 1 and 2, including six active switching states and three zero switching states. In Table 1, line currents ia, ib, ic are the currents in phases A, B, C, and the line-side current ip is the current through the primary winding of the transformer Tr. In Table 2, the transformer turns ratio k is assumed to be 1 so that the inductor current iL is equal to the line-side current ip.


TABLE 1
Space Vectors, Switching States, and Phase Currents
Space
Switching States
Vector
S1
S2
S3
S4
S5
S6
ia
ib
ic
I1
1
0
0
0
0
1
ip
−ip
0
I2
1
1
0
0
0
0
ip
0
−ip
I3
0
1
1
0
0
0
0
ip
−ip
I4
0
0
1
1
0
0
−ip
ip
0
I5
0
0
0
1
1
0
−ip
0
ip
I6
0
0
0
0
1
1
0
−ip
ip
I7
1
0
0
1
0
0
0
0
0
I8
0
0
1
0
0
1
0
0
0
I9
0
1
0
0
1
0
0
0
0


TABLE 2
Space Vectors, Switching States, and Phase Currents
Space
Switching States
Vector
S1
S2
S3
S4
S5
S6
ia
ib
ic
I1
1
0
0
0
0
1
id
−id
0
I2
1
1
0
0
0
0
id
0
−id
I3
0
1
1
0
0
0
0
id
−id
I4
0
0
1
1
0
0
−id
id
0
I5
0
0
0
1
1
0
−id
0
id
I6
0
0
0
0
1
1
0
−id
Id
I7
1
0
0
1
0
0
0
0
0
I8
0
0
1
0
0
1
0
0
0
I9
0
1
0
0
1
0
0
0
0

The matrix-converter's controller determines a reference current {right arrow over (I)}ref and calculates the on and off times of the switches S1 to S6 to approximate the reference current {right arrow over (I)}ref to produce the line-side currents ia, ib, and ic. The reference current {right arrow over (I)}ref preferably is sinusoidal with a fixed frequency and a fixed magnitude: {right arrow over (I)}ref=Irefe. The fixed frequency is preferably the same as the fixed frequency of each of the three-phase ia(t), ib(t), and ic(t) to reduce harmful reflections. The controller determines the magnitude of the reference current {right arrow over (I)}ref to achieve a desired output voltage uo. That is, the controller regulates the output voltage uo by varying the magnitude of the reference current {right arrow over (I)}ref. Varying the magnitude of the reference current {right arrow over (I)}ref changes the on and off times of the switches S1 to S6.

The reference current {right arrow over (I)}ref moves through the α-β plane shown in FIG. 14. The angle θ is defined as the angle between the a-axis and the reference current {right arrow over (I)}ref. Thus, as the angle θ changes, the reference current {right arrow over (I)}ref sweeps through the different sectors I-VI.

The reference current {right arrow over (I)}ref can be synthesized by using combinations of the active and zero vectors. As used herein “synthesized” means that the reference current {right arrow over (I)}ref can be represented as a combination of the active and zero vectors. The active and zero vectors are stationary and do not move in the α-β plane as shown in FIG. 14. The vectors used to synthesize the reference current {right arrow over (I)}ref change depending on which sector the reference current {right arrow over (I)}ref is located. The active vectors are chosen by the active vectors defining the sector. The zero vector is chosen for each sector by determining which on switch the two active vectors have in common and choosing the zero vector that also includes the same on switch. Using the zero vectors allows the magnitude of the line-side current ip to be adjusted.

For example, consider when the current reference {right arrow over (I)}ref is in sector I. The active vectors {right arrow over (I)}1 and {right arrow over (I)}2 define sector I. The switch S1 is on for both active vectors {right arrow over (I)}1 and {right arrow over (I)}2. The zero vector {right arrow over (I)}7 also has the switch S1 on. Thus, when the reference current {right arrow over (I)}ref is located in sector I, the active vectors {right arrow over (I)}1 and {right arrow over (I)}2 and zero vector {right arrow over (I)}7 are used to synthesize the reference current {right arrow over (I)}ref, which provides the following equation, with the right-hand side of the equation resulting from vector {right arrow over (I)}7 being a zero vector with zero magnitude:

Iref=T1TsI1+T2TsI2+T7TsI7=T1TsI1+T2TsI2

where T1, T2, and T0 are the dwell times for the corresponding active switches and Ts is the sampling period.

The dwell time is the on time of the corresponding switches. For example, T1 is the on time of the switches S1 and S6 for the active vector {right arrow over (I)}1. Because the switch S1 is on for each of vectors {right arrow over (I)}1, {right arrow over (I)}2, and {right arrow over (I)}7, the switch S1 is on during the entire sampling period Ts. The ratio T1/Ts is the duty cycle for the switch S6 during the sampling period Ts.

The sampling period Ts is typically chosen such that the reference current {right arrow over (I)}ref is synthesized multiple times per sector. For example, the reference current {right arrow over (I)}ref, can be synthesized twice per sector so that the reference current {right arrow over (I)}ref, is synthesized twelve times per cycle, where one complete cycle is when the reference current {right arrow over (I)}ref goes through sectors I-VI.

The dwell times can be calculated using the ampere-second balancing principle, i.e., the product of the reference current {right arrow over (I)}ref, and sampling period Ts equals the sum of the current vectors multiplied by the time interval of synthesizing space vectors. Assuming that the sampling period Ts is sufficiently small, the reference current {right arrow over (I)}ref can be considered constant during the sampling period T5. The reference current {right arrow over (I)}ref can be synthesized by two adjacent active vectors and a zero vector. For example, when the reference current {right arrow over (I)}ref is in sector I, the reference current {right arrow over (I)}ref can be synthesized by vectors {right arrow over (I)}1, {right arrow over (I)}2, and {right arrow over (I)}7. The ampere-second balancing equation is thus given by the following equations.

{right arrow over (I)}refTs={right arrow over (I)}1T1+{right arrow over (I)}T2+{right arrow over (I)}7T7

Ts=T1+T2+T7

where T1, T2, and T7 are the dwell times for the vectors {right arrow over (I)}1, {right arrow over (I)}2, and {right arrow over (I)}7 and Ts is sampling time. Then the dwell times are given by

T1=mTs sin(π/6−θ)

T2=mTs sin(π/6+θ)

T7=Ts−T1−T2

where

m=kIrefiL,

θ is sector angle between current reference {right arrow over (I)}ref and a-axis shown in FIG. 5, and k is the transformer turns ratio.

Because of the isolation provided by the transformer, the matrix-converter output voltage u1(t) must alternate between positive and negative with high frequency to maintain the volt-sec balance. Thus, the preferred vector sequence in every sampling period Ts is divided into eight segments as {right arrow over (I)}α, {right arrow over (I)}0, −{right arrow over (I)}β, {right arrow over (I)}0, −{right arrow over (I)}β, {right arrow over (I)}0, −{right arrow over (I)}α, {right arrow over (I)}0, where vectors {right arrow over (I)}α and {right arrow over (I)}β are active vectors and {right arrow over (I)}0 is a zero vector. For example, in sector I, vectors {right arrow over (I)}α and {right arrow over (I)}β are active vectors {right arrow over (I)}1 and {right arrow over (I)}2, and vector {right arrow over (I)}0 is zero vector {right arrow over (I)}7. When converter #1 is active, a positive vector can be used, and when converter #2 is active, a negative vector can be used.

The waveforms of the matrix-converter output voltage u1(t) and the matrix-converter output current ip(t) during one sampling period Ts are shown in FIG. 5. In FIG. 5, the matrix-converter output voltage u1(t) has three kinds of polarities:

    • (1) u1(t) has positive polarity between times to and t1 and between times t4 and t5. These time intervals can be referred to as P-intervals. The current vector in a P-interval can be referred to as a P-vector. Under the effect of a P-vector, the matrix-converter output current ip(t) increases.
    • (2) u1(t) has negative polarity between times t2 and t3 and between times t6 and t7. These time intervals can be referred to as N-intervals. The current vector in a N-interval can be referred to as a N-vector. Under the effect of an N-vector, the matrix-converter output current ip(t) decreases.
    • (3) u1(t) is zero between times t1 and t2, between times t3 and t4, between times t5 and t6, and between times t7 and t8. These time intervals can be referred to as Z-intervals. The current vector in a Z-interval can be referred to as a Z-vector. Under the effect of a Z-vector, the absolute value of the matrix-converter output current ip(t) decreases at most to be zero, and the direction of the matrix-converter output current ip(t) will not change during the Z-interval.

In one sampling period Ts, the eight intervals are in sequence: P-interval, Z-interval, N-interval, Z-interval, P-interval, Z-interval, N-interval, Z-interval. As shown in FIG. 5, there is a commutation between the different intervals.

Commutation refers to turning on and off of the switches to switch from one vector to another vector. Known commutation methods for matrix converters are 4-step commutation methods based on either output current or input voltage. These known commutation methods are very complicated and require accurately measuring either the output current or the input voltage.

(1) Known 4-Step Current-Based Commutation

The 4-step current-based commutation measures the output current direction. The two-phase-to-single-phase matrix converter in FIG. 2 illustrates the problems with current-based commutation. All the important commutations can be seen in the circuit shown in FIG. 2.

As an example, assume that switches S11 and S21 are initially on and the switches S13 and S23 are initially off so that current can flow in either direction in the bi-directional switch on the left side of FIG. 2 and assume that we want to turn off the bi-directional switch on the left side of FIG. 2 and turn on the bi-directional switch on the right side of FIG. 2. As shown in FIG. 3A, when the current i>0, the following four steps can be used:

    • (1) switch S11 turns off;
    • (2) switch S23 turns on;
    • (3) switch S21 turns off;
    • (4) switch S13 turns on.

As shown in FIG. 3B, when the current i<0, the following four-step commuting method is possible:

    • (1) switch S21 turns off;
    • (2) switch S13 turn on;
    • (3) switch S11 turns off;
    • (4) switch S23 turns on.

(2) Known 4-Step Voltage-Based Commutation

Known 4-step voltage-based commutation is similar to current-based commutation. Assuming that switches S11 and S21 are on and switches S13 and S23 are off so that current can flow in either direction in the bi-directional switch on the left side of FIG. 2 and assume that the bi-directional switch on the left side of FIG. 2 is to be turned off, and the bi-directional switch on the right side of FIG. 2 is to be turned on. As shown in FIG. 4A, when voltage ua>voltage ub, the following four steps can be used:

    • (1) switch S23 turns on;
    • (2) switch S21 turns off;
    • (3) switch S13 turns on;
    • (4) switch S11 turns off.

As shown in FIG. 4B, when the voltage ua<voltage ub, the following four steps can be used:

    • (1) switch S13 turns on;
    • (2) switch S11 turns off;
    • (3) switch S23 turns on;
    • (4) switch S21 turns off.

Both current- and voltage-based commutation methods have problems such as taking a very long time to complete commutation, requiring complicated logic circuitry to implement the commutation methods, and requiring accurate current or voltage measurements. The frequency using these known commutation methods is limited because of the long time it takes to complete the commutation.

SUMMARY OF THE INVENTION

To overcome the problems described above, preferred embodiments of the present invention provide fast commutation. Preferred embodiments of the present invention provide 2- or 3-step commutation that achieves one or more of the following advantages:

    • (1) shorter time to complete commutation.
    • (2) no need to measure the output current or input voltage because, in a rectifier-based matrix converter, the primary current ip of the transformer is well defined because the input power factor is unity, i.e. the line-side current and voltage are in the same phase.
    • (3) easier implementation than known 4-step commutation methods.
    • (4) suitable for high-frequency applications.

A matrix rectifier that can be used with the preferred embodiments of the present invention includes first, second, and third phases; and uni-directional switches Sij, where i=1, 2 and j=1, 2, 3, 4, 5, 6 and where uni-directional switches Sij and S2j are connected together to define first, second, third, fourth, fifth, and sixth bi-directional switches. First ends of the first, third, and fifth bidirectional switches are connected together to provide a positive-voltage node. First ends of the second, fourth, and sixth bidirectional switches are connected together to provide a negative-voltage node. Second ends of the first and fourth bidirectional switches are connected to the first phase. Second ends of the third and sixth bidirectional switches are connected to the second phase. Second ends of the fifth and second bidirectional switches are connected to the third phase. A zero vector is defined by either uni-directional switches S1m and S1n switched on or uni-directional switches S2m and S2n switched on, where (m, n)=(1, 4), (3, 6), (5, 2), and by all other uni-directional switches Spq switched off, where p≠m and q≠n. An active vector is defined by either uni-directional switches S1m and S1n switched on or uni-directional switches S2m and S2n switched on, where m=1, 3, 5; n=2, 4, 6; and m, n are not connected to the same phase, and by all other uni-directional switches Spq switched off, where p≠m and q≠n. Sectors I, II, III, IV, V, and VI are defined by using active vectors with (a, b)=(1, 6), (1, 2), (3, 2), (3, 4), (5, 4), and (5, 6).

According to a preferred embodiment of the present invention, a method of performing commutation in a matrix rectifier from an active vector to a zero vector includes

step (a):

    • for an active vector with uni-directional switches S1m and S1n switched on,

      • in Sectors I, III, V, turning on uni-directional switch S1x, where x is chosen such that (m, x)=(1, 4), (3, 6), (5, 2); and
      • in Sectors II, IV, VI, turning on uni-directional switch S1x, where x is chosen such that (x, n)=(1, 4), (3, 6), (5, 2); or
    • for an active vector with uni-directional switches S2m and S2n switched on,

      • in Sectors I, III, V, turning on uni-directional switch S2y, where y is chosen such that (y, n)=(1, 4), (3, 6), (5, 2); and
      • in Sectors II, IV, VI, turning on uni-directional switch S2y, where y is chosen such that (m, y)=(1, 4), (3, 6), (5, 2);

step (b):

    • for the active vector with uni-directional switches S1m and S1n initially switched on,

      • in Sectors I, III, V, turning off uni-directional switch S1n; and
      • in Sectors II, IV, VI, turning off uni-directional switch S1m; or
    • for the active vector with uni-directional switches S2m and S2n initially switched on,

      • in Sectors I, III, V, turning off uni-directional switch S2m;
      • in Sectors II, IV, VI, turning off uni-directional switch S2n.

Commutation is preferably performed by measuring input voltage and without measuring output current or output voltage.

According to a preferred embodiment of the present invention, a method of operating a matrix rectifier includes performing commutation from an active vector to a zero vector using the commutation method according to various other preferred embodiments of the present invention and modulating the first, second, third, fourth, fifth, and sixth bi-directional switches based on space vector modulation.

According to a preferred embodiment of the present invention, a method of performing commutation in a matrix rectifier from a zero vector to an active vector includes:

step (a):

    • for a zero vector with uni-directional switches S1m and S1n switched on,

      • in Sectors I, III, V, turning on uni-directional switch S1x, where x=1, 3, 5 and x is chosen such that a negative voltage is provided at the positive-voltage node; and
      • in Sectors II, IV, VI, turning on uni-directional switch S1x, where x=2, 4, 6 and x is chosen such that a positive voltage is provided at the negative-voltage node; or
    • for a zero vector with uni-directional switches S2m and S2n switched on,

      • in Sectors I, III, V, turning on uni-directional switch S2y, where y=2, 4, 6 and y is chosen such that a positive voltage is provided at the negative-voltage node; and
      • in Sectors II, IV, VI, turning on uni-directional switch S2y, where y=1, 3, 5 and y is chosen such that a negative voltage is provided at the positive-voltage node;

step (b):

    • for the zero vector with uni-directional switches S1m and S1n initially switched on,

      • in Sectors I, III, V, turning off uni-directional switch S1m; and
      • in Sectors II, IV, VI, turning off uni-directional switch S1n; or
    • for the zero vector with uni-directional switches S2m and S2n initially switched on,

      • in Sectors I, III, V, turning off uni-directional switch S2n; and
      • in Sectors II, IV, VI, turning off uni-directional switch S2m; and

step (c):

    • for the zero vector with uni-directional switches S1m and S1n initially switched on,

      • in Sectors I, III, V, turning off uni-directional switches S1x and S1n and turning on uni-directional switches S2x and S2n; and
      • in Sectors II, IV, VI, turning off uni-directional switches S1x and S1m and turning on uni-directional switches S2x and S2m; or
    • for the zero vector with uni-directional switches S2m and S2n initially switched on,

      • in Sectors I, III, V, turning off uni-directional switches S2m and S2y and turning on uni-directional switches S1m and S1y; and
      • in Sectors II, IV, VI, turning off uni-directional switches S2n and S2y and turning on uni-directional switches S1n and S1y.

Commutation is preferably performed by measuring input voltage and without measuring output current or output voltage. Preferably, in step (a), for the zero vector with uni-directional switches S1m and S1n initially switched on, no current passes through uni-directional switch S1x; or for the zero vector with uni-directional switches S2m and S2n initially switched on, no current passes through uni-directional switch S2y. Preferably, step (b) lasts until a current through the positive-voltage node or the negative-voltage node reaches zero. The method further preferably includes a transformer connected to the positive-voltage and negative-voltage nodes, where a holding time Δt of step (b) is provided by:

Δt=LoL1maxU1min

where I1max is a maximum current of the matrix converter, U1min is a minimum output voltage of the matrix converter, and Lo is a leakage inductance of the transformer.

According to a preferred embodiment of the present invention, a method of operating a matrix rectifier includes performing commutation from a zero vector to an active vector using the commutation method according to various other preferred embodiments of the present invention and modulating the first, second, third, fourth, fifth, and sixth bi-directional switches based on space vector modulation.

Preferably, gate signals sij applied to uni-directional switches Sij are generated by determining a space-vector-modulation sector and generating:

    • a carrier signal;
    • first, second, and third comparison signals based on dwell times of corresponding zero vector and two active vectors of the space-vector-modulation sector;
    • modulation signals si corresponding to the first, second, third, fourth, fifth, and sixth bi-directional switches based on the comparison of the carrier signal and the first, second, and third comparison signals, where i=1, 2, 3, 4, 5, 6;
    • first converter select signal SelectCon1 and second converter select signal SelectCon2 based on if a positive or a negative voltage is outputted; wherein the gate signals sij are generated based on:

      s1j=si×SelectCon1(j=1,3,5,4,6,2)

      S2j=si×SelectCon2(j=1,3,5,4,6,2).

The above and other features, elements, characteristics, steps, and advantages of the present invention will become more apparent from the following detailed description of preferred embodiments of the present invention with reference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are circuit diagrams of matrix-converters.

FIG. 2 is a circuit diagram of a two-phase-to-single-phase matrix converter.

FIGS. 3A and 3B show the steps of current-based commutation.

FIGS. 4A and 4B show the steps of voltage-based commutation.

FIG. 5 shows the waveforms of the rectifier of a matrix converter.

FIG. 6 shows eight switching modes in one sampling period in sector I.

FIGS. 7A and 7B show 2-step commutation from an active vector to a zero vector for a positive current in sector I.

FIGS. 8A and 8B show 3-step commutation from a zero vector to an active vector.

FIG. 9 is a block diagram of gate-signal generator.

FIG. 10 shows SVM-modulation and commutation signals in one sampling period.

FIG. 11 shows gate signals in one sampling period in sector I.

FIG. 12 shows 2-step commutation at time t2.

FIG. 13 shows 3-step commutation at time t3.

FIG. 14 shows a current-space vector hexagon.

FIG. 15 shows 2-step commutation from an active vector to a zero vector for a negative current in sector I.

FIG. 16 shows 3-step commutation from a zero vector to an active vector for a negative current in sector I.

FIG. 17 shows 2-step commutation from an active vector to a zero vector for a positive current in sector II.

FIG. 18 shows 3-step commutation from a zero vector to an active vector for a positive current in sector II.

FIG. 19 shows 2-step commutation from an active vector to a zero vector for a negative current in sector II.

FIG. 20 shows 3-step commutation from a zero vector to an active vector for a negative current in sector II.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Preferred embodiments of the present invention improve the known four-step commutation methods. Current commutation can ensure reliable operation. Because the rectifiers of 3-phase-to-1-phase matrix-converters have a different structure compared to the rectifiers of known 3-phase-to-3-phase matrix converters, rectifiers of a 3-phase-to-1-phase matrix-converter can use a different current-based commutation method, as discussed below.

As shown in FIG. 5, the matrix-converter output current ip(t) is positive in adjacent P- and Z-intervals, except for the commutation area, and the matrix-converter output current ip(t) is negative in adjacent N- and Z-intervals, except for the commutation area. During adjacent P- and Z-intervals, converter #1 works normally and converter #2 stops working, and in contrast, during adjacent N- and Z-intervals, converter #2 works normally and converter #1 stops working. Thus, there are eight switching modes in one sampling period exclusive of the commutation areas as shown in FIG. 6. In one sampling period, there are two types of current-based commutations: (1) active vector (i.e., either P-vector or N-vector) to zero vector and (2) zero vector to active vector. A two-step active-vector-to-zero-vector commutation and a three-step zero-vector-to-active-vector commutation are discussed below.

(1) Active Vector to Zero Vector (P-Vector to Z-Vector or N-Vector to Z-Vector)

As seen in FIGS. 5 and 6, active-vector-to-zero-vector commutations include the commutations from mode 1 (P-vector) to mode 2 (Z-vector), mode 3 (N-vector) to mode 4 (Z-vector), mode 5 (P-vector) to mode 6 (Z-vector), and mode 7 (N-vector) to mode 8 (Z-vector). During active-vector-to-zero-vector commutation, the direction of the output current of the rectifier of the matrix converter does not change. Thus, active-vector-to-zero-vector commutation only adds an overlap time just as the commutation method of the current-source inverter. The overlap time is added to make sure that the current can smoothly transition from one switch to another switch and that no overvoltage is induced during this transition. The overlap time is determined by the “turn on” and “turn off” speed of these two switches. For example, as shown in FIGS. 7A and 7B, the commutation from mode 1 to mode 2 only has two steps:

    • (1) switch S14 turns on, and
    • (2) switch S16 turns off.

      Thus, commutation from an active vector to a zero vector is achieved. FIGS. 7A and 7B show an example of the 2-step commutation from an active vector to a zero vector for a positive current in sector I. Similar commutation steps are performed in sectors III and V.

FIG. 15 shows a 2-step commutation from an active vector to a zero vector for a negative current in sector I. The commutation steps include:

    • (1) switch S21 turns on, and
    • (2) switch S23 turns off.

      Similar commutation steps are performed in sectors III and V.

FIG. 17 shows a 2-step commutation from an active vector to a zero vector for a positive current in sector II. The commutation steps include:

    • (3) switch S15 turns on, and
    • (4) switch S11 turns off.

      Similar commutation steps are performed in sectors IV and VI.

FIG. 19 shows a 2-step commutation from an active vector to a zero vector for a negative current in sector II. The commutation steps include:

    • (1) switch S22 turns on, and
    • (2) switch S24 turns off.

      Similar commutation steps are performed in sectors IV and VI.

(2) Zero Vector to Active Vector (Z-Vector to P-Vector or Z-Vector to N-Vector)

As seen in FIGS. 5 and 6, zero-vector-to-active-vector commutations include the commutations from mode 2 (Z-vector) to mode 3 (N-vector), mode 4 (Z-vector) to mode 5 (P-vector), mode 6 (Z-vector) to mode 7 (N-vector), and mode 8 (Z-vector) to mode 1 of the next sampling period (P-vector). During zero-vector-to-active-vector commutation, the direction of the output current of the rectifier of the matrix converter changes. Thus, zero-vector-to-active-vector commutation requires an additional step. For example, as shown in FIGS. 8A and 8B, the commutation from mode 2 to mode 3 in sector I includes three steps:

    • (1) switch S15 turns on. The purpose of this step is to provide a current path for the next step. Although switch S15 is on in this step, there is no current passing through switch S15 because the voltage ua is larger than the voltage uc and because the diode in series with the switch S15 is reversed biased. The output vector is still the Z-vector. The time span Δt1 that this step maintains can be decided according to the overlap time of the current-source inverter. The overlap time is added to make sure that the switch S15 is on before switch S11 turns off, considering the delay between the gate signals of the switches S11 and S15.
    • (2) Switch S11 turns off. After turning switch S11 off, the output vector is substantially the N-vector, so the output current will be reduced sharply and reach zero quickly. This step should last long enough to ensure that the current reaches zero. The holding time Δt2 of this step can be estimated by the maximum current I1max of the matrix converter, the minimum output voltage U1min of the matrix converter, and the leakage inductance Lo of the transformer:

Δt2=LOL1maxU1min(1)

    • For simplicity, the holding time Δt2 can be selected as a fixed value according to eq. (1). The holding time Δt2 is determined by the transition time required for the output current to reach zero. The holding time Δt2 based on eq. (1) is long enough to ensure that the current reaches zero under all the conditions.
    • (3) Switches S15 and S14 turn off and switches S24 and S24 turn on.

      Thus, commutation from a zero vector to an active vector is achieved. FIGS. 8A and 8B show an example of the 3-step commutation from a zero vector to an active vector for a positive current in sector I. Similar commutation steps are performed in sectors III and V.

FIG. 16 shows a 3-step commutation from a zero vector to an active vector for a negative current in sector I. The commutation steps include:

    • (1) switch S22 turns on,
    • (2) switch S24 turns off, and
    • (3) switches S21 and S22 turn off and switches S11 and S12 turn on.

      Similar commutation steps are performed in sectors III and V.

FIG. 18 shows a 3-step commutation from a zero vector to an active vector for a positive current in sector II. The commutation steps include:

    • (1) switch S16 turns on,
    • (2) switch S12 turns off, and
    • (3) switches S15 and S16 turn off and switches S25 and S26 turn on.

      Similar commutation steps are performed in sectors IV and VI.

FIG. 20 shows a 3-step commutation from a zero vector to an active vector for a negative current in sector II. The commutation steps include:

    • (1) switch S23 turns on,
    • (2) switch S25 turns off, and
    • (3) switches S23 and S22 turn off and switches S13 and S12 turn on.

      Similar commutation steps are performed in sectors IV and VI.

As shown in FIG. 10, the time periods (or “effective area” in FIG. 10) when only converter #1 is on and the time periods when only converter #2 is on are separate from each other. In FIG. 10, the signal SelectCon1 is 1 when converter #1 is on, i.e., the effective area for converter #1, and is 0 when converter #1 is off, i.e., the effective area for converter #2. Similarly, the signal SelectCon2 when converter #2 is on, i.e., the effective area for converter #2, and is 0 when converter #2 is off, i.e., the effective area for converter #1. As shown in FIG. 9, the following three steps can be used to achieve modulation and commutation.

(1) Generate the Signals Si (i=1, 2, 3, 4, 5, 6)

Accordingly, a carrier signal and three compare value signals CMP0, CMP1, CMP2 are used to generate the SVM PWM signals Si′ (i=1, 2, 3, 4, 5, 6). The compare values signals CMP0, CMP1, CMP2 are determined by the dwell time of each vector. After the holding time Δt1 for the falling edge of signals Si′ has lapsed, the signals Si (i=1, 2, 3, 4, 5, 6) can be generated. The falling edge of signal Si is delayed for holding time Δt1 compared with the signal Si′. An overlap time is added to the signals S1, S3, S5, and S4, S6, S2 just as in the commutation method of the current-source inverter. In sector I, for example, the signals S1, S3, S5 and S4, S6, S2 are shown in FIG. 10.

(2) Generate Signal SelectCon1 and Signal SelectCon2

After comparison between the carrier signal and CMP1 and the delay Δt of both rising and falling edges, signal SelectCon1 can be generated, as shown in FIGS. 9 and 10. The fixed delay time Δt is based on the three steps of zero-vector-to-active-vector commutation. So the delay time Δt can be determined by eq. (2).

Δt=Δt1+Δt2  (2)

where Δt1 is the overlap time and Δt2 is estimated by eq. (1).

(3) Generate Gate Signals Si1 for Converter #1 and Gate Signals Si2 for Converter #2

The gate signals S1j for converter #1 can be generated by eq. (3), and the gate signals S2j for converter #2 can be generated by eq. (4):

S1j=Sj×SelectCon1(j=1,3,5,4,6,2)  (3)

S2j=Sj×SelectCon2(j=1,3,5,4,6,2)  (4)

For example, in sector I, the gate signals S11, S13, S15, S14, S16, and S12 are generated for converter #1, and the gate signals S21, S23, S22, S24, S26, and S22 are generated for converter #1 as shown in FIG. 10.

FIGS. 11-13 show the gate signals generated using a field programmable gate array (FPGA) to implement the method described above. FIG. 11 shows the gate signals for switches S1 to S6 in sector I. The time period from time t1 to time t9 is one sampling period Ts. Times t2, t4, t6, and t8 use 2-step commutation, and times t1, t2, t3, t7, and t9 use 3-step commutation.

For example, at time t2, the commutation from mode 1 to mode 2 (from active vector to zero vector) as shown in FIG. 7 is in two steps. The 2-step commutation waveforms are shown in FIG. 12. At time t3, the commutation from mode 2 to mode 3 (from zero vector to active vector) as shown in FIG. 8 is in three steps. The 3-step commutation waveforms are shown in FIG. 13.

It should be understood that the foregoing description is only illustrative of the present invention. Various alternatives and modifications can be devised by those skilled in the art without departing from the present invention. Accordingly, the present invention is intended to embrace all such alternatives, modifications, and variances that fall within the scope of the appended claims.

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Citation

Patents Cited in This Cited by
Title Current Assignee Application Date Publication Date
Power conversion systems and methods for controlling harmonic distortion ROCKWELL AUTOMATION TECHNOLOGIES, INC. 30 December 2008 01 July 2010
Polyphase Voltage Converter Control Method VALEO EQUIPEMENTS ELECTRIQUES MOTEUR 13 December 2006 30 October 2008
Direct-type converting apparatus and method for controlling the same DAIKIN INDUSTRIES, LTD. 19 June 2009 26 May 2011
Power Transfer Devices, Methods, and Systems with Crowbar Switch Shunting Energy-Transfer Reactance IDEAL POWER INC. 08 August 2011 01 December 2011
Power converting apparatus DAIKIN INDUSTRIES, LTD. 21 October 2008 26 August 2010
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The widest range of IP search tools makes getting the right answers and asking the right questions easier than ever. One click analysis extracts meaningful information on competitors and technology trends from IP data.
Business Intelligence
Gain powerful insights into future technology changes, market shifts and competitor strategies.
Workflow
Manage IP-related processes across multiple teams and departments with integrated collaboration and workflow tools.
Contact Sales
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