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Patent Analysis of

Semiconductor device and method for manufacturing semiconductor device

Updated Time 12 June 2019

Patent Registration Data

Publication Number

US9905657

Application Number

US15/408719

Application Date

18 January 2017

Publication Date

27 February 2018

Current Assignee

SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Original Assignee (Applicant)

SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

International Classification

H01L29/40,H01L29/423,H01L29/66,H01L29/786,H01L29/49

Cooperative Classification

H01L29/401,H01L27/1225,H01L27/14616,H01L29/42384,H01L29/66969

Inventor

ENDO, YUTA,SUZAWA, HIDEOMI,HANAOKA, KAZUYA,SASAGAWA, SHINYA,OKAMOTO, SATORU

Patent Images

This patent contains figures and images illustrating the invention and its embodiment.

US9905657 Semiconductor 1 US9905657 Semiconductor 2 US9905657 Semiconductor 3
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Abstract

A semiconductor device in which parasitic capacitance is reduced is provided. A first oxide insulating layer and a first oxide semiconductor layer are sequentially formed over a first insulating layer. A first conductive layer is formed over the first oxide semiconductor layer and etched to form a second conductive layer. The first oxide insulating layer and the first oxide semiconductor layer are etched with the second conductive layer as a mask to form a second oxide insulating layer and a second oxide semiconductor layer. A planarized insulating layer is formed over the first insulating layer and the second conductive layer. A second insulating layer, a source electrode layer, and a drain electrode layer are formed by etching the planarized insulating layer and the second conductive layer. A third oxide insulating layer, a gate insulating layer, and a gate electrode layer are formed over the second oxide semiconductor layer.

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Claims

1. A method for manufacturing a semiconductor device, comprising the steps of: forming a first insulating layer over a substrate; forming a first oxide insulating layer over the first insulating layer; forming a first oxide semiconductor layer over the first oxide insulating layer; forming a second insulating layer over the first oxide semiconductor layer; forming a third insulating layer by etching the second insulating layer with a first mask so that a first part of the first oxide semiconductor layer is exposed; forming a first conductive layer over the first oxide semiconductor layer and the third insulating layer; forming a second conductive layer by performing etch-back treatment on the first conductive layer so that a second part of the first oxide semiconductor layer is exposed, wherein the second conductive layer comprises a region in contact with a side surface of the third insulating layer; removing the third insulating layer; forming a second oxide insulating layer and a second oxide semiconductor layer by etching the first oxide insulating layer and the first oxide semiconductor layer with the second conductive layer as a second mask so that the first insulating layer is exposed; forming a fourth insulating layer over the first insulating layer and the second conductive layer; forming a fifth insulating layer by performing planarization treatment on the fourth insulating layer; forming a sixth insulating layer, a source electrode layer, and a drain electrode layer by etching the fifth insulating layer and the second conductive layer with a third mask; forming a third oxide insulating layer, a seventh insulating layer, and a third conductive layer over the sixth insulating layer and the second oxide semiconductor layer; and forming a fourth oxide insulating layer, a gate insulating layer, and a gate electrode layer by performing planarization treatment on the third oxide insulating layer, the seventh insulating layer, and the third conductive layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the first conductive layer is formed by a CVD method.

3. The method for manufacturing a semiconductor device according to claim 1, wherein the first conductive layer comprises at least one of aluminum, titanium, cobalt, nickel, copper, molybdenum, ruthenium, silver, tantalum, tungsten, platinum, palladium, silicon, iridium, iron, manganese, nitrogen, and oxygen.

4. The method for manufacturing a semiconductor device according to claim 1, wherein an angle between the side surface of the third insulating layer and a top surface of the substrate is substantially perpendicular.

5. The method for manufacturing a semiconductor device according to claim 1, wherein a thickness of the first conductive layer is greater than or equal to 4 nm and less than or equal to 40 nm.

6. A method for manufacturing a semiconductor device, comprising the steps of: forming a first insulating layer over a substrate; forming a first oxide insulating layer over the first insulating layer; forming a first oxide semiconductor layer over the first oxide insulating layer; forming a second insulating layer over the first oxide semiconductor layer; forming a third insulating layer by etching the second insulating layer with a first mask, wherein the third insulating layer has a frame shape when seen from a direction perpendicular to a surface of the substrate; forming a first conductive layer over the first oxide semiconductor layer and the third insulating layer; forming a second conductive layer by performing etch-back treatment on the first conductive layer, wherein the second conductive layer comprises a region in contact with inside and outside surfaces of a frame of the third insulating layer; removing the third insulating layer; forming a third conductive layer by etching the second conductive layer with a second mask, wherein the third conductive layer has a rectangular shape when seen from the direction perpendicular to the surface of the substrate; forming a second oxide insulating layer and a second oxide semiconductor layer by etching the first oxide insulating layer and the first oxide semiconductor layer with the third conductive layer as a third mask; forming a fourth insulating layer over the first insulating layer and the third conductive layer; forming a fifth insulating layer by performing planarization treatment on the fourth insulating layer; forming a sixth insulating layer, a source electrode layer, and a drain electrode layer by etching the fifth insulating layer and the third conductive layer with a fourth mask; forming a third oxide insulating layer over the sixth insulating layer and the second oxide semiconductor layer; forming a seventh insulating layer over the third oxide insulating layer; forming a fourth conductive layer over the seventh insulating layer; and forming a fourth oxide insulating layer, a gate insulating layer, and a gate electrode layer by performing planarization treatment on the third oxide insulating layer, the seventh insulating layer, and the fourth conductive layer.

7. The method for manufacturing a semiconductor device according to claim 6, wherein the first conductive layer is formed by a CVD method.

8. The method for manufacturing a semiconductor device according to claim 6, wherein the first conductive layer comprises at least one of aluminum, titanium, cobalt, nickel, copper, molybdenum, ruthenium, silver, tantalum, tungsten, platinum, palladium, silicon, iridium, iron, manganese, nitrogen, and oxygen.

9. The method for manufacturing a semiconductor device according to claim 6, wherein an angle between a side surface of the third insulating layer and a top surface of the substrate is substantially perpendicular.

10. The method for manufacturing a semiconductor device according to claim 6, wherein a thickness of the first conductive layer is greater than or equal to 4 nm and less than or equal to 40 nm.

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Claim Tree

  • 1
    1. A method for manufacturing a semiconductor device, comprising
    • the steps of: forming a first insulating layer over a substrate
    • forming a first oxide insulating layer over the first insulating layer
    • forming a first oxide semiconductor layer over the first oxide insulating layer
    • forming a second insulating layer over the first oxide semiconductor layer
    • forming a third insulating layer by etching the second insulating layer with a first mask so that a first part of the first oxide semiconductor layer is exposed
    • forming a first conductive layer over the first oxide semiconductor layer and the third insulating layer
    • forming a second conductive layer by performing etch-back treatment on the first conductive layer so that a second part of the first oxide semiconductor layer is exposed, wherein the second conductive layer comprises a region in contact with a side surface of the third insulating layer
    • removing the third insulating layer
    • forming a second oxide insulating layer and a second oxide semiconductor layer by etching the first oxide insulating layer and the first oxide semiconductor layer with the second conductive layer as a second mask so that the first insulating layer is exposed
    • forming a fourth insulating layer over the first insulating layer and the second conductive layer
    • forming a fifth insulating layer by performing planarization treatment on the fourth insulating layer
    • forming a sixth insulating layer, a source electrode layer, and a drain electrode layer by etching the fifth insulating layer and the second conductive layer with a third mask
    • forming a third oxide insulating layer, a seventh insulating layer, and a third conductive layer over the sixth insulating layer and the second oxide semiconductor layer
    • and forming a fourth oxide insulating layer, a gate insulating layer, and a gate electrode layer by performing planarization treatment on the third oxide insulating layer, the seventh insulating layer, and the third conductive layer.
    • 2. The method for manufacturing a semiconductor device according to claim 1, wherein
      • the first conductive layer is formed by a CVD method.
    • 3. The method for manufacturing a semiconductor device according to claim 1, wherein
      • the first conductive layer comprises
    • 4. The method for manufacturing a semiconductor device according to claim 1, wherein
      • an angle between the side surface of the third insulating layer and a top surface of the substrate is substantially perpendicular.
    • 5. The method for manufacturing a semiconductor device according to claim 1, wherein
      • a thickness of the first conductive layer is greater than or equal to 4 nm and less than or equal to 40 nm.
  • 6
    6. A method for manufacturing a semiconductor device, comprising
    • the steps of: forming a first insulating layer over a substrate
    • forming a first oxide insulating layer over the first insulating layer
    • forming a first oxide semiconductor layer over the first oxide insulating layer
    • forming a second insulating layer over the first oxide semiconductor layer
    • forming a third insulating layer by etching the second insulating layer with a first mask, wherein the third insulating layer has a frame shape when seen from a direction perpendicular to a surface of the substrate
    • forming a first conductive layer over the first oxide semiconductor layer and the third insulating layer
    • forming a second conductive layer by performing etch-back treatment on the first conductive layer, wherein the second conductive layer comprises a region in contact with inside and outside surfaces of a frame of the third insulating layer
    • removing the third insulating layer
    • forming a third conductive layer by etching the second conductive layer with a second mask, wherein the third conductive layer has a rectangular shape when seen from the direction perpendicular to the surface of the substrate
    • forming a second oxide insulating layer and a second oxide semiconductor layer by etching the first oxide insulating layer and the first oxide semiconductor layer with the third conductive layer as a third mask
    • forming a fourth insulating layer over the first insulating layer and the third conductive layer
    • forming a fifth insulating layer by performing planarization treatment on the fourth insulating layer
    • forming a sixth insulating layer, a source electrode layer, and a drain electrode layer by etching the fifth insulating layer and the third conductive layer with a fourth mask
    • forming a third oxide insulating layer over the sixth insulating layer and the second oxide semiconductor layer
    • forming a seventh insulating layer over the third oxide insulating layer
    • forming a fourth conductive layer over the seventh insulating layer
    • and forming a fourth oxide insulating layer, a gate insulating layer, and a gate electrode layer by performing planarization treatment on the third oxide insulating layer, the seventh insulating layer, and the fourth conductive layer.
    • 7. The method for manufacturing a semiconductor device according to claim 6, wherein
      • the first conductive layer is formed by a CVD method.
    • 8. The method for manufacturing a semiconductor device according to claim 6, wherein
      • the first conductive layer comprises
    • 9. The method for manufacturing a semiconductor device according to claim 6, wherein
      • an angle between a side surface of the third insulating layer and a top surface of the substrate is substantially perpendicular.
    • 10. The method for manufacturing a semiconductor device according to claim 6, wherein
      • a thickness of the first conductive layer is greater than or equal to 4 nm and less than or equal to 40 nm.
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Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an object, a method, or a manufacturing method. The present invention relates to a process, a machine, manufacture, or a composition of matter. In particular, the present invention relates to, for example, a semiconductor device, a display device, a light-emitting device, a power storage device, an imaging device, a driving method thereof, or a fabrication method thereof. In particular, one embodiment of the present invention relates to a semiconductor device or a method for manufacturing the semiconductor device.

In this specification and the like, the semiconductor device indicates all the devices that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are embodiments of semiconductor devices. In some cases, a memory device, a display device, or an electronic device includes a semiconductor device.

2. Description of the Related Art

Attention has been focused on a technique for forming a transistor using a semiconductor film formed over a substrate having an insulating surface. The transistor is applied to a wide range of electronic devices such as an integrated circuit (IC) or an image display device (display device). A silicon-based semiconductor material is widely known as a material for a semiconductor thin film applicable to a transistor. As another material, an oxide semiconductor has been attracting attention.

For example, Patent Document 1 discloses a transistor including an amorphous oxide semiconductor layer containing indium (In), gallium (Ga), and zinc (Zn) in a channel formation region layer.

REFERENCE

Patent Document

[Patent Document 1] Japanese Published Patent Application No. 2006-165528

SUMMARY OF THE INVENTION

Manufacturing of semiconductor devices with highly integrated transistors requires miniaturization of transistors. It becomes more difficult to control various steps of manufacturing transistors (in particular, film formation, processing, and the like) as the miniaturization advances. The variations in shape of transistors significantly affect transistor characteristics and reliability.

For example, in miniaturized transistors, a marked increase in the parasitic capacitance of the transistors may cause a problem. For example, in the case where parasitic capacitance exists in a channel formation region (e.g., between a source electrode and a drain electrode) and the vicinity of the channel formation region, a time for charging the parasitic capacitance is needed in the transistor operation; thus, the responsiveness of the semiconductor device is lowered.

Thus, an object of one embodiment of the present invention is to reduce the parasitic capacitance in the vicinity of a transistor. Another object is to provide a semiconductor device capable of high-speed operation. Another object is to provide a semiconductor device with favorable electrical characteristics. Another object is to provide a semiconductor device with high reliability. Another object is to reduce variations in characteristics of a semiconductor device. Another object is to provide a semiconductor device including an oxide semiconductor layer having few oxygen vacancies. Another object is to provide a semiconductor device that can be manufactured in a simple process. Another object is to provide a semiconductor device with a structure in which the density of interface states in the vicinity of the oxide semiconductor layer can be reduced. Another object is to provide a semiconductor device with low power consumption. Another object is to provide a novel semiconductor device. Another object is to provide a manufacturing method of the semiconductor device.

Note that the descriptions of these objects do not disturb the existence of other objects. In one embodiment of the present invention, there is no need to achieve all the objects. Other objects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.

(1) One embodiment of the present invention is a method for manufacturing a semiconductor device, including the steps of: forming a first insulating layer over a substrate; sequentially forming a first oxide insulating layer and a first oxide semiconductor layer over the first insulating layer; forming a second insulating layer over the first oxide semiconductor layer; forming a third insulating layer by etching the second insulating layer with a first mask; forming a first conductive layer over the first oxide semiconductor layer and the third insulating layer; forming a second conductive layer including a region in contact with a side surface of the third insulating layer by performing etch-back treatment on the first conductive layer; removing the third insulating layer; forming a second oxide insulating layer and a second oxide semiconductor layer by etching the first oxide insulating layer and the first oxide semiconductor layer with the second conductive layer as a second mask; forming a fourth insulating layer over the first insulating layer, the second oxide semiconductor layer, and the second conductive layer; forming a fifth insulating layer by performing planarization treatment on the fourth insulating layer; forming a sixth insulating layer, a source electrode layer, and a drain electrode layer by etching the fifth insulating layer and the second conductive layer with a third mask; forming a third oxide insulating layer, a seventh insulating layer, and a third conductive layer over the sixth insulating layer and the second oxide semiconductor layer; and forming a fourth oxide insulating layer, a gate insulating layer, and a gate electrode layer by performing planarization treatment on the third oxide insulating layer, the seventh insulating layer, and the third conductive layer.

(2) Another embodiment of the present invention is a method for manufacturing a semiconductor device, including the steps of: forming a first insulating layer over a substrate; sequentially forming a first oxide insulating layer and a first oxide semiconductor layer over the first insulating layer; forming a second insulating layer over the first oxide semiconductor layer; forming a third insulating layer with a frame shape by etching a second insulating layer with a first mask; forming a first conductive layer over the first oxide semiconductor layer and the third insulating layer; forming a second conductive layer by performing etch-back treatment on the first conductive layer, in which the second conductive layer includes a region in contact with inside and outside surfaces of a frame of the third insulating layer; removing the third insulating layer; forming a second mask over the first oxide semiconductor layer and the second conductive layer; forming a third conductive layer with a rectangular shape when seen from above by etching the second conductive layer with the second mask; forming a second oxide insulating layer and a second oxide semiconductor layer by etching the first oxide insulating layer and the first oxide semiconductor layer with the third conductive layer as a third mask; forming a fourth insulating layer over the first insulating layer, the second oxide semiconductor layer, and the third conductive layer; forming a fifth insulating layer by performing planarization treatment on the fourth insulating layer; forming a sixth insulating layer, a source electrode layer, and a drain electrode layer by etching the fifth insulating layer and the third conductive layer with a fourth mask; forming a third oxide insulating layer over the sixth insulating layer and the second oxide semiconductor layer, forming a seventh insulating layer over the third oxide insulating layer, forming a fourth conductive layer over the seventh insulating layer; and forming a fourth oxide insulating layer, a gate insulating layer, and a gate electrode layer by performing planarization treatment on the third oxide insulating layer, the seventh insulating layer, and the fourth conductive layer.

(3) It is preferable that, in the above method for manufacturing a semiconductor device, the first conductive layer be formed by a CVD method.

(4) It is preferable that, in the above method for manufacturing a semiconductor device, the first conductive layer include tungsten.

(5) It is preferable that, in the above method for manufacturing a semiconductor device, the angle between a side surface of the third insulating layer and a top surface of the substrate be substantially perpendicular.

(6) It is preferable that, in the above method for manufacturing a semiconductor device, the thickness of the first conductive layer be greater than or equal to 4 nm and less than or equal to 40 nm.

(7) Another embodiment of the present invention is a semiconductor device including a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a second insulating layer over the oxide semiconductor layer. In a cross section in the channel width direction, the value obtained by dividing the length of the bottom surface of the oxide semiconductor layer in the channel width direction by the length of the central portion of the oxide semiconductor layer in the thickness direction is less than or equal to 2.

(8) It is preferable that, in the above semiconductor device, the length of the oxide semiconductor layer in the channel width direction be less than or equal to 30 nm.

(9) It is preferable that, in the above semiconductor device, at least one of corners of the oxide semiconductor layer be rounded.

According to one embodiment of the present invention, the parasitic capacitance in a transistor and in the vicinity of the transistor can be reduced, and a semiconductor device capable of high-speed operation can be provided. Alternatively, a semiconductor device with favorable electrical characteristics can be provided. Alternatively, a semiconductor device with high reliability can be provided. Alternatively, variations in characteristics of a transistor or a semiconductor device that are caused by a manufacturing process can be reduced. Alternatively, a semiconductor device including an oxide semiconductor layer having few oxygen vacancies can be provided. Alternatively, a semiconductor device that can be manufactured in a simple process can be provided. Alternatively, a semiconductor device with a structure in which the density of interface states in and near an oxide semiconductor layer can be reduced can be provided. Alternatively, a semiconductor device with low power consumption can be provided. Alternatively, a novel semiconductor device or the like can be provided. Alternatively, a manufacturing method of the semiconductor device can be provided.

Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily achieve all the effects listed above. Other effects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a top view of a transistor, and FIGS. 1B and 1C are cross-sectional views thereof.

FIGS. 2A to 2C each illustrate an atomic ratio range of an oxide.

FIG. 3 illustrates a crystal of InMZnO4.

FIGS. 4A and 4B are each a band diagram of a stacked-layer structure in the oxide.

FIGS. 5A to 5D illustrate an ALD mechanism.

FIGS. 6A and 6B are schematic views of an ALD apparatus.

FIGS. 7A to 7C are a top view and cross-sectional views illustrating a method for manufacturing a transistor.

FIGS. 8A to 8C are a top view and cross-sectional views illustrating a method for manufacturing a transistor.

FIGS. 9A to 9C are a top view and cross-sectional views illustrating a method for manufacturing a transistor.

FIGS. 10A to 10C are a top view and cross-sectional views illustrating a method for manufacturing a transistor.

FIGS. 11A to 11C are a top view and cross-sectional views illustrating a method for manufacturing a transistor.

FIGS. 12A to 12C are a top view and cross-sectional views illustrating the method for manufacturing a transistor.

FIGS. 13A to 13C are a top view and cross-sectional views illustrating a method for manufacturing a transistor.

FIGS. 14A to 14C are a top view and cross-sectional views illustrating the method for manufacturing a transistor.

FIGS. 15A to 15C are a top view and cross-sectional views illustrating a method for manufacturing a transistor.

FIGS. 16A to 16C are a top view and cross-sectional views illustrating a method for manufacturing a transistor.

FIGS. 17A to 17C are a top view and cross-sectional views illustrating a method for manufacturing a transistor.

FIGS. 18A to 18C are a top view and cross-sectional views illustrating the method for manufacturing a transistor.

FIGS. 19A to 19C are a top view and cross-sectional views illustrating the method for manufacturing a transistor.

FIGS. 20A to 20C are a top view and cross-sectional views illustrating the method for manufacturing a transistor.

FIGS. 21A to 21C are a top view and cross-sectional views illustrating a method for manufacturing a transistor.

FIGS. 22A to 22C are a top view and cross-sectional views illustrating a method for manufacturing a transistor.

FIGS. 23A to 23C are a top view and cross-sectional views illustrating a method for manufacturing a transistor.

FIG. 24A is a top view of a transistor, and FIGS. 24B and 24C are cross-sectional views thereof.

FIG. 25A is a top view of a transistor, and FIGS. 25B and 25C are cross-sectional views thereof.

FIG. 26A is a top view of a transistor, and FIGS. 26B and 26C are cross-sectional views thereof.

FIGS. 27A to 27C are a top view and cross-sectional views illustrating the method for manufacturing a transistor.

FIG. 28A is a top view of a transistor, and FIGS. 28B and 28C are cross-sectional views thereof.

FIGS. 29A to 29E are Cs-corrected high-resolution TEM images of a cross section of a CAAC-OS and a cross-sectional schematic view of a CAAC-OS.

FIGS. 30A to 30E are Cs-corrected high-resolution TEM images of a plane of a CAAC-OS.

FIGS. 31A to 31D show structural analysis of a CAAC-OS and a single crystal oxide semiconductor layer by XRD.

FIGS. 32A and 32B show electron diffraction patterns of a CAAC-OS.

FIG. 33 shows a change in crystal part of an In—Ga—Zn oxide induced by electron irradiation.

FIGS. 34A to 34D are cross-sectional views and circuit diagrams of a semiconductor device.

FIGS. 35A to 35C are cross-sectional views and circuit diagrams of a semiconductor device.

FIG. 36 is a cross-sectional view of a semiconductor device.

FIG. 37 is a cross-sectional view of a semiconductor device.

FIG. 38 is a cross-sectional view of a semiconductor device.

FIGS. 39A and 39B are plan views of an imaging device.

FIGS. 40A and 40B are plan views of pixels of an imaging device.

FIGS. 41A and 41B are cross-sectional views of an imaging device.

FIGS. 42A and 42B are cross-sectional views of an imaging device.

FIGS. 43A to 43C are circuit diagrams and a timing chart illustrating a semiconductor device according to one embodiment of the present invention.

FIGS. 44A to 44C are a graph and circuit diagrams illustrating a semiconductor device of one embodiment of the present invention.

FIGS. 45A and 45B are a circuit diagram and a timing chart illustrating a semiconductor device of one embodiment of the present invention.

FIGS. 46A and 46B are a circuit diagram and a timing chart illustrating a semiconductor device of one embodiment of the present invention.

FIGS. 47A to 47E are a block diagram, circuit diagrams, and waveform diagrams for illustrating one embodiment of the present invention.

FIGS. 48A and 48B are a circuit diagram and a timing chart illustrating one embodiment of the present invention.

FIGS. 49A and 49B are circuit diagrams for illustrating one embodiment of the present invention.

FIGS. 50A to 50C are circuit diagrams for illustrating one embodiment of the present invention.

FIG. 51 illustrates a configuration example of an RF tag.

FIG. 52 illustrates a configuration example of a CPU.

FIG. 53 is a circuit diagram of a memory element.

FIGS. 54A to 54C illustrate a configuration example of a display device and circuit diagrams of pixels.

FIGS. 55A and 55B are a top view and a cross-sectional view of a liquid crystal display device.

FIGS. 56A and 56B are a top view and a cross-sectional view of a light-emitting device.

FIG. 57 illustrates a display module.

FIG. 58A is a perspective view illustrating a cross-sectional structure of a package using a lead frame interposer, and FIG. 58B is a plan view illustrating a structure of a module of a mobile phone.

FIGS. 59A to 59E illustrate electronic devices.

FIGS. 60A to 60D illustrate electronic devices.

FIGS. 61A to 61C illustrate electronic devices.

FIGS. 62A to 62F illustrate electronic devices.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments will be described in detail with reference to the drawings. Note that the present invention is not limited to the following description. It will be readily appreciated by those skilled in the art that modes and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. The present invention therefore should not be construed as being limited to the following description of the embodiments. In structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and the description thereof is not repeated in some cases. The same components are denoted by different hatching patterns in different drawings, or the hatching patterns are omitted in some cases.

<Notes on Description for Drawings>

In this specification, terms for describing arrangement, such as “over” and “under,” are used for convenience to describe a positional relation between components with reference to drawings. Furthermore, the positional relation between components is changed as appropriate in accordance with a direction in which each component is described. Thus, there is no limitation on terms used in this specification, and description can be made appropriately depending on the situation.

The term “over” or “under” does not necessarily mean that a component is placed directly over or directly under and directly in contact with another component. For example, the expression “electrode B over insulating layer A” does not necessarily mean that the electrode B is over and in direct contact with the insulating layer A and can mean the case where another component is provided between the insulating layer A and the electrode B.

In this specification, trigonal and rhombohedral crystal systems are included in a hexagonal crystal system.

In drawings, the size, the layer thickness, or the region is determined arbitrarily for description convenience. Therefore, the size, the layer thickness, or the region is not limited to the illustrated scale. Note that the drawings are schematically shown for clarity, and embodiments of the present invention are not limited to shapes or values shown in the drawings.

In drawings such as a top view (also referred to as a plan view or a layout view) and a perspective view, some of components might not be illustrated for clarity of the drawings.

<Notes on Expressions that can be Rephrased>

In this specification, in description of connections of a transistor, expressions “one of a source and a drain” (or a first electrode or a first terminal) and “the other of the source and the drain” (or a second electrode or a second terminal) are used. This is because a source and a drain of a transistor are interchangeable depending on the structure, operation conditions, or the like of the transistor. Note that the source or the drain of the transistor can also be referred to as a source (or drain) terminal, a source (or drain) electrode, or the like as appropriate depending on the situation.

In this specification, the term of “electrode” or “wiring” does not limit the function of components. For example, an “electrode” is sometimes used as part of a “wiring”, and vice versa. Furthermore, the term “electrode” or “wiring” can include the case where a plurality of “electrodes” or “wirings” is formed in an integrated manner.

In this specification, a transistor is an element having at least three terminals of a gate, a drain, and a source. The transistor has a channel formation region between the drain (a drain terminal, a drain region, or a drain electrode) and the source (a source terminal, a source region, or a source electrode), and current can flow through the drain, the channel formation region, and the source.

Here, since the source and the drain of the transistor are interchangeable depending on the structure, the operating condition, or the like of the transistor, it is difficult to define which is a source or a drain. Thus, a portion that functions as a source or a portion that functions as a drain is not referred to as a source or a drain in some cases. In that case, one of the source and the drain might be referred to as a first electrode, and the other of the source and the drain might be referred to as a second electrode.

Note that in this specification, ordinal numbers such as “first”, “second”, and “third” are used in order to avoid confusion among components, and the terms do not limit the components numerically.

In this specification, the terms “film” and “layer” can be interchanged depending on the case or circumstances. For example, the term “conductive layer” can be changed into the term “conductive film” in some cases. Also, the term “insulating film” can be changed into the term “insulating layer” in some cases.

The expression “being the same” in this specification may refer to having the same area or having the same shape. Note that the expression “being the same” include a case of “being substantially the same” because a manufacturing process might cause some differences.

Note that what is described (or part thereof) in an embodiment in this specification can be applied to, combined with, or replaced with another content in the same embodiment and/or what is described (or part thereof) in another embodiment or other embodiments.

In addition, by combining a diagram (or part thereof) described in one embodiment in this specification with another part of the diagram, a different diagram (or part thereof) described in the same embodiment, and/or a diagram (or part thereof) described in another or other embodiments, much more diagrams can be formed.

Notes on Definitions of Terms and Other Matters

The following are definitions of the terms mentioned in the above embodiments and other matters.

In this specification, the term “parallel” indicates that the angle formed between two straight lines is greater than or equal to −10° and less than or equal to 10°, and accordingly also includes the case where the angle is greater than or equal to −5° and less than or equal to 5°. A term “substantially parallel” indicates that the angle formed between two straight lines is greater than or equal to −30° and less than or equal to 30°. Furthermore, the term “perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and accordingly also includes the case where the angle is greater than or equal to 85° and less than or equal to 95°. In addition, the term “substantially perpendicular” indicates that an angle formed between two straight lines is greater than or equal to 60° and less than or equal to 120°.

In this specification, the term “trench” or “groove” refers to a depression with a narrow belt shape.

Furthermore, in this specification, an explicit description “X and Y are connected” means that X and Y are directly connected, X and Y are electrically connected, and X and Y are functionally connected. Accordingly, without being limited to a connection relationship shown in drawings or specifications, another connection relationship is included therein.

Here, each of X and Y denotes an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer).

Examples of the case where X and Y are directly connected include the case where an element that enables electrical connection between X and Y (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display element, a light-emitting element, or a load) is not connected between X and Y, and the case where X and Y are connected without the element that enables electrical connection between X and Y provided therebetween.

For example, in the case where X and Y are electrically connected, one or more elements that enable electrical connection between X and Y (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display element, a light-emitting element, or a load) can be connected between X and Y. Note that the switch is controlled to be turned on or off. That is, the switch is conducting or not conducting (is turned on or off) to determine whether current flows therethrough or not. Alternatively, the switch has a function of selecting and changing a current path. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected.

For example, in the case where X and Y are functionally connected, one or more circuits that enable functional connection between X and Y (e.g., a logic circuit such as an inverter, a NAND circuit, or a NOR circuit; a signal converter circuit such as a D/A converter circuit, an A/D converter circuit, or a gamma correction circuit; a potential level converter circuit such as a power supply circuit (e.g., a step-up circuit or a step-down circuit) or a level shifter circuit for changing the potential level of a signal; a voltage source; a current source; a switching circuit; an amplifier circuit such as a circuit that can increase signal amplitude, the amount of current, or the like, an operational amplifier, a differential amplifier circuit, a source follower circuit, or a buffer circuit; a signal generation circuit; a memory circuit; or a control circuit) can be connected between X and Y. Note that for example, in the case where a signal output from X is transmitted to Y even when another circuit is provided between X and Y, X and Y are functionally connected. The case where X and Y are functionally connected includes the case where X and Y are directly connected and X and Y are electrically connected.

Note that in this specification and the like, an explicit description “X and Y are electrically connected” means that X and Y are electrically connected (i.e., the case where X and Y are connected with another element or another circuit provided therebetween), X and Y are functionally connected (i.e., the case where X and Y are functionally connected with another circuit provided therebetween), and X and Y are directly connected (i.e., the case where X and Y are connected without another element or another circuit provided therebetween). That is, in this specification and the like, the explicit description “X and Y are electrically connected” is the same as the explicit description “X and Y are connected”.

For example, the case where a source (or a first terminal or the like) of a transistor is electrically connected to X through (or not through) Z1 and a drain (or a second terminal or the like) of the transistor is electrically connected to Y through (or not through) Z2, or the case where a source (or a first terminal or the like) of a transistor is directly connected to part of Z1 and another part of Z1 is directly connected to X while a drain (or a second terminal or the like) of the transistor is directly connected to part of Z2 and another part of Z2 is directly connected to Y, can be expressed by using any of the following expressions.

Examples of the expressions include, “X, Y, a source (or a first terminal or the like) of a transistor, and a drain (or a second terminal or the like) of the transistor are electrically connected to each other, and X, the source (or the first terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor, and Y are electrically connected to each other in this order”, “a source (or a first terminal or the like) of a transistor is electrically connected to X, a drain (or a second terminal or the like) of the transistor is electrically connected to Y, and X, the source (or the first terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor, and Y are electrically connected to each other in this order”, and “X is electrically connected to Y through a source (or a first terminal or the like) and a drain (or a second terminal or the like) of a transistor, and X, the source (or the first terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor, and Y are provided to be connected in this order”. When the connection order in a circuit configuration is defined by an expression similar to the above examples, a source (or a first terminal or the like) and a drain (or a second terminal or the like) of a transistor can be distinguished from each other to specify the technical scope.

Other examples of the expressions include “a source (or a first terminal or the like) of a transistor is electrically connected to X through at least a first connection path, the first connection path does not include a second connection path, the second connection path is a path between the source (or the first terminal or the like) of the transistor and a drain (or a second terminal or the like) of the transistor, Z1 is on the first connection path, the drain (or the second terminal or the like) of the transistor is electrically connected to Y through at least a third connection path, the third connection path does not include the second connection path, and Z2 is on the third connection path”. It is also possible to use the expression “a source (or a first terminal or the like) of a transistor is electrically connected to X through at least Z1 on a first connection path, the first connection path does not include a second connection path, the second connection path includes a connection path through the transistor, a drain (or a second terminal or the like) of the transistor is electrically connected to Y through at least Z2 on a third connection path, and the third connection path does not include the second connection path”. Still another example of the expressions is “a source (or a first terminal or the like) of a transistor is electrically connected to X through at least Z1 on a first electrical path, the first electrical path does not include a second electrical path, the second electrical path is an electrical path from the source (or the first terminal or the like) of the transistor to a drain (or a second terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor is electrically connected to Y through at least Z2 on a third electrical path, the third electrical path does not include a fourth electrical path, and the fourth electrical path is an electrical path from the drain (or the second terminal or the like) of the transistor to the source (or the first terminal or the like) of the transistor”. When the connection path in a circuit configuration is defined by an expression similar to the above examples, a source (or a first terminal or the like) and a drain (or a second terminal or the like) of a transistor can be distinguished from each other to specify the technical scope.

Note that these expressions are examples and there is no limitation on the expressions. Here, X, Y, Z1, and Z2 each denote an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer).

Even when independent components are electrically connected to each other in a circuit diagram, one component has functions of a plurality of components in some cases. For example, when part of a wiring also functions as an electrode, one conductive film functions as the wiring and the electrode. Thus, the term “electrical connection” in this specification also means such a case where one conductive film has functions of a plurality of components.

In this specification and the like, a structure in which a flexible printed circuit (FPC), a tape carrier package (TCP), or the like is attached to a substrate of a display panel, or a structure in which an integrated circuit (IC) is directly mounted on a substrate by a chip on glass (COG) method is referred to as a display device in some cases.

Embodiment 1

In this embodiment, a transistor of one embodiment of the present invention and a manufacturing method thereof will be described with reference to drawings.

<Structure of Transistor 10>

FIGS. 1A to 1C are a top view and cross-sectional views of a transistor 10 of one embodiment of the present invention. FIG. 1A is a top view and FIGS. 1B and 1C are cross-sectional views taken along dashed-dotted line A1-A2 and dashed-dotted line A3-A4 in FIG. 1A, respectively. Note that for simplification of the drawing, some components are increased or reduced in size, or omitted in FIG. 1A. In some cases, the direction of dashed-dotted line A1-A2 is referred to as a channel length direction, and the direction of dashed-dotted line A3-A4 is referred to as a channel width direction.

The transistor 10 includes a substrate 100, an insulating layer 110, an oxide insulating layer 121, an oxide semiconductor layer 122, an oxide insulating layer 123, a source electrode layer 130, a drain electrode layer 140, a gate insulating layer 150, a gate electrode layer 160, an insulating layer 175, an insulating layer 180, a conductive layer 190, and a conductive layer 195.

The insulating layer 110 is provided over the substrate 100.

The oxide insulating layer 121 is provided over the insulating layer 110.

The oxide semiconductor layer 122 is provided over the oxide insulating layer 121.

In a cross section in the channel width direction (see FIG. 1C), a value obtained by dividing the length of a bottom surface of the oxide semiconductor layer 122 in the channel width direction by the length (height) of the oxide semiconductor layer 122 in the film thickness direction is preferably less than or equal to 2.

The length (height) of the oxide semiconductor layer 122 is preferably less than or equal to 40 nm, further preferably 30 nm, and still further preferably 20 nm.

At least one of corners of the oxide semiconductor layer 122 in the channel width direction is rounded.

The oxide insulating layer 123 is provided over the oxide semiconductor layer 122. When seen in the channel width direction, the oxide insulating layer 123 preferably includes a region that is in contact with a side surface of the oxide semiconductor layer 122. Accordingly, the side surface of the oxide semiconductor layer 122 can be protected and thus the electrical characteristics of the transistor 10 can be stabilized.

<Oxide Insulating Layer>

An oxide insulating layer (e.g., the oxide insulating layers 121 and 123) refers to a layer which basically has an insulating property and in which current can flow through the interface with a semiconductor including a channel formation region and the vicinity thereof when a gate electric field or a drain electric field of a transistor is increased, for example.

The source electrode layer 130 and the drain electrode layer 140 are provided over and electrically connected to the oxide semiconductor layer 122.

The gate insulating layer 150 is provided over the oxide insulating layer 123.

The gate electrode layer 160 is provided over the gate insulating layer 150. Note that the gate electrode layer 160, the gate insulating layer 150, and the oxide insulating layer 123 are provided over and overlap with the oxide semiconductor layer 122.

The insulating layer 175 is provided over the insulating layer 110, the source electrode layer 130, and the drain electrode layer 140. The insulating layer 175 includes a region that is in contact with side surfaces of the oxide insulating layer 121 and the oxide semiconductor layer 122. The insulating layer 175 has a groove 174 which reaches a top surface of the oxide semiconductor layer 122.

The insulating layer 180 is provided over the oxide insulating layer 123, the gate insulating layer 150, the gate electrode layer 160, and the insulating layer 175.

The conductive layers 190 are provided over the source electrode layer 130 and the drain electrode layer 140. The source electrode layer 130 and the drain electrode layer 140 each include a region electrically connected to the conductive layer 190.

The conductive layer 195 is provided over the conductive layer 190. The conductive layer 195 includes a region electrically connected to the conductive layer 190.

With the above structure, parasitic capacitance between the gate and the source and/or parasitic capacitance between the gate and the drain of the transistor 10 can be reduced. Thus, the cutoff frequency characteristics of the transistor 10 are improved, for example, and therefore the transistor 10 can operate at high speed.

Furthermore, the gate, the source, and the drain of the transistor 10 can be formed in a self-aligned manner; thus, a miniaturized semiconductor device with high alignment accuracy can be easily manufactured.

When seen in the channel width direction, the transistor 10 includes a region where the gate electrode layer 160 faces the side surface of the oxide semiconductor layer 122 with the oxide insulating layer 123 and the gate insulating layer 150 interposed therebetween as illustrated in FIG. 1C. In other words, the oxide semiconductor layer 122 is surrounded by an electric field of the gate electrode layer 160 in the channel width direction when voltage is applied to the gate electrode layer 160. The transistor structure in which the semiconductor including a channel formation region is surrounded by the electric field of the gate electrode layer 160 is referred to as a surrounded channel (s-channel) structure. Moreover, in the s-channel structure, the bottom surface of the oxide semiconductor layer 122 is located at a higher level than that of the gate electrode layer 160.

In the transistor 10 of one embodiment of the present invention in an on state, a channel formation region is formed in the entire oxide semiconductor layer 122 (bulk); thus, the on-state current is increased as compared with that of a transistor with no s-channel structure. On the other hand, in an off state, the difference in electron affinity between the oxide semiconductor layer 122 and the oxide insulating layers 121 and 123 causes a potential barrier (the details will be described later); thus, the off-state current can be decreased as compared with that of a transistor in which the oxide insulating layer 121 and/or the oxide insulating layer 123 is not included.

<Channel Length>

Note that the channel length of a transistor refers to, for example, in a top view of the transistor, a distance between a source (a source region or a source electrode) and a drain (a drain region or a drain electrode) in a region where a semiconductor including a channel formation region (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other or a region where a channel is formed. In one transistor, channel lengths in all regions are not necessarily the same. In other words, the channel length of one transistor is not limited to one value in some cases. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

<SCW>

Therefore, in this specification, in a top view of a transistor, an apparent channel width in a region where a semiconductor including a channel formation region and a gate electrode overlap with each other is referred to as a surrounded channel width (SCW) in some cases. Furthermore, in this specification, in the case where the term “channel width” is simply used, it may denote a surrounded channel width and an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width (the details will be described later). Note that the values of a channel length, a channel width, an effective channel width, an apparent channel width, a surrounded channel width, and the like can be determined by obtaining and analyzing a cross-sectional TEM image and the like.

Note that in the case where field-effect mobility, a current value per channel width, and the like of a transistor are obtained by calculation, a surrounded channel width may be used for the calculation. In that case, the values may be different from those calculated using an effective channel width in some cases.

<Channel Width>

Note that the channel width of a transistor refers to, for example, the length of a region where a semiconductor including a channel formation region (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other. In one transistor, channel widths in all regions are not necessarily the same. In other words, the channel width of one transistor is not limited to one value in some cases. Therefore, in this specification, a channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

Note that depending on transistor structures, a channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) is different from an apparent channel width shown in the top view of the transistor in some cases. For example, in a three-dimensional structure of a transistor, an effective channel width is greater than an apparent channel width, and its influence cannot be ignored in some cases. For example, in a miniaturized transistor having a three-dimensional structure, the proportion of a channel region formed in a side surface of a semiconductor is high in some cases. In that case, an effective channel width obtained when a channel is actually formed is greater than an apparent channel width shown in the top view of the transistor.

In a transistor having a three-dimensional structure, an effective channel width is difficult to measure in some cases. For example, to estimate an effective channel width from a design value, it is necessary to know the shape of a semiconductor including a channel formation region. Therefore, in the case where the shape of the semiconductor is not known accurately, measuring an effective channel width accurately is difficult.

<Improvement in Electrical Characteristics of Miniaturized Transistor>

High integration of a semiconductor device requires miniaturization of a transistor. However, it is known that miniaturization of a transistor causes deterioration of electrical characteristics of the transistor.

However, in the transistor 10 of one embodiment of the present invention shown in FIGS. 1A to 1C, as described above, when seen from the channel width direction, the oxide insulating layer 123 is formed to cover the oxide semiconductor layer 122 where a channel region is formed and the channel formation region is not in contact with the gate insulating layer 150. Accordingly, scattering of carriers at the interface between the channel formation region and the gate insulating layer 150 can be reduced and the on-state current of the transistor can be increased.

The transistor 10 of one embodiment of the present invention has an s-channel structure in which the gate electrode layer 160 is formed to electrically surround the oxide semiconductor layer 122 including a channel formation region in the channel width direction. Therefore, a gate electric field is applied to the oxide semiconductor layer 122 in the side surface direction in addition to the top surface direction. Furthermore, the bottom surface of the oxide semiconductor layer 122 is located at a higher level than that of the gate electrode layer 160 and thus a gate electric field is also applied to the bottom surface of the oxide semiconductor layer 122. In other words, a gate electric field is applied to the oxide semiconductor layer 122 entirely, so that current flows in the whole of the oxide semiconductor layer 122. In this manner, the transistor 10 of one embodiment of the present invention can have increased on-state current by having the s-channel structure.

Since the transistor 10 of one embodiment of the present invention has an s-channel structure, the effect of the gate electric field on the oxide semiconductor layer 122 is very strong. Therefore, the influence of a drain electric field on the oxide semiconductor layer 122 can be relatively decreased and occurrence of a short-channel effect can be significantly suppressed. Therefore, the transistor can have favorable electrical characteristics even when miniaturized.

Alternatively, when the transistor 10 of one embodiment of the present invention includes a wide band gap material as the oxide semiconductor layer 122 including a channel formation region, the transistor can have high source-drain breakdown voltage and stable electrical characteristics in various temperature environments.

Although an example where an oxide semiconductor layer or the like is used in a channel formation region or the like is described in this embodiment, one embodiment of the present invention is not limited thereto. For example, depending on circumstances or conditions, a channel formation region, the vicinity of the channel formation region, a source region, a drain region, or the like may be formed using a material containing silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like.

<Components of Transistor>

Components of a transistor of this embodiment will be described below.

<<Substrate 100>>

A glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used as the substrate 100. Alternatively, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon, silicon carbide, or the like, a compound semiconductor substrate made of silicon germanium or the like, a silicon-on-insulator (SOI) substrate, or the like may be used. Still alternatively, any of these substrates provided with a semiconductor element may be used.

The substrate 100 is not limited to a simple supporting substrate, and may be a substrate where a device such as a transistor is formed. In that case, at least one of the gate, the source, and the drain of the transistor may be electrically connected to the device.

Alternatively, a flexible substrate may be used as the substrate 100. As a method for providing the transistor over a flexible substrate, there is a method in which the transistor is formed over a non-flexible substrate and then the transistor is separated and transferred to the substrate 100 that is a flexible substrate. In that case, a separation layer is preferably provided between the non-flexible substrate and the transistor. As the substrate 100, a sheet, a film, or a foil containing a fiber may be used, for example. The substrate 100 may have elasticity. The substrate 100 may have a property of returning to its original shape when bending or pulling is stopped. Alternatively, the substrate 100 may have a property of not returning to its original shape. The thickness of the substrate 100 is, for example, greater than or equal to 5 μm and less than or equal to 700 μm, preferably greater than or equal to 10 μm and less than or equal to 500 μm and further preferably greater than or equal to 15 μm and less than or equal to 300 μm. When the substrate 100 has a small thickness, the weight of the semiconductor device can be reduced. When the substrate 100 has a small thickness, even in the case of using glass or the like, the substrate 100 might have elasticity or a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device over the substrate 100, which is caused by dropping or the like, can be reduced. That is, a durable semiconductor device can be provided.

For the substrate 100 which is a flexible substrate, metal, an alloy, resin, glass, or fiber thereof can be used, for example. The flexible substrate 100 preferably has a lower coefficient of linear expansion because deformation due to an environment is suppressed. The flexible substrate 100 is formed using, for example, a material whose coefficient of linear expansion is lower than or equal to 1×10−3/K, lower than or equal to 5×10−5/K, or lower than or equal to 1×10−5/K. Examples of the resin include polyester, polyolefin, polyamide (e.g., nylon or aramid), polyimide, polycarbonate, acrylic, and polytetrafluoroethylene (PTFE). In particular, aramid is preferably used for the flexible substrate 100 because of its low coefficient of linear expansion.

<<Insulating Layer 110>>

As the insulating layer 110, an insulating film containing one or more of silicon (Si), nitrogen (N), oxygen (O), fluorine (F), hydrogen (H), aluminum (Al), gallium (Ga), germanium (Ge), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (Hf), and tantalum (Ta) can be used.

The insulating layer 110 can have a function of supplying oxygen to the oxide semiconductor layer 122 as well as a function of preventing diffusion of impurities from the substrate 100. For this reason, the insulating layer 110 is preferably an insulating film containing oxygen, further preferably an insulating film having an oxygen content higher than that in the stoichiometric composition. The insulating layer 110 is, for example, a film in which the amount of released oxygen when converted into oxygen atoms is greater than or equal to 1.0×1019 atoms/cm3 in thermal desorption spectroscopy (TDS) analysis. Note that the temperature of the film surface in the TDS analysis is preferably higher than or equal to 100° C. and lower than or equal to 700° C., or higher than or equal to 100° C. and lower than or equal to 500° C. In the case where the substrate 100 is provided with another device as described above, the insulating layer 110 also functions as an interlayer insulating film. In that case, the insulating layer 110 is preferably subjected to planarization treatment such as chemical mechanical polishing (CMP) treatment so as to have a flat surface.

When the insulating layer 110 contains fluorine, fluorine gasified from the insulating layer 110 can stabilize an oxygen vacancy in the oxide semiconductor layer 122.

<<Oxide Insulating Layer 121, Oxide Semiconductor Layer 122, and Oxide Insulating Layer 123>>

An oxide which can be used for the oxide semiconductor layer 122, the oxide insulating layer 121, and the oxide insulating layer 123 of one embodiment of the present invention is described below.

An oxide preferably contains at least indium or zinc. In particular, indium and zinc are preferably contained. In addition, aluminum, gallium, yttrium, tin, or the like is preferably contained. Furthermore, one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like may be contained.

Here, the case where an oxide contains indium, an element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, or the like. Alternatively, the element M can be boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like. Note that two or more of the above elements may be used in combination as the element M.

First, preferred ranges of the atomic ratio of indium, the element M, and zinc contained in an oxide according to an embodiment of the present invention are described with reference to FIGS. 2A to 2C. Note that the proportion of oxygen atoms is not illustrated in FIGS. 2A to 2C. The terms of the atomic ratio of indium, the element M, and zinc contained in the oxide are denoted by [In], [M], and [Zn], respectively.

In FIGS. 2A to 2C, broken lines indicate a line where the atomic ratio of [In]:[M]:[Zn] is (1+α):(1−α):1, where −1≦α≦1, a line where the atomic ratio of [In]:[M]:[Zn] is (1+α):(1−α):2, a line where the atomic ratio of [In]:[M]:[Zn] is (1+α):(1−α):3, a line where the atomic ratio of [In]:[M]:[Zn:] is (1+α):(1−α):4, and a line where the atomic ratio of [In]:[M]:[Zn] is (1+α):(1−α):5.

Dashed-dotted lines indicate a line where the atomic ratio [In]:[M]:[Zn] is 1:1:β, where β≧0, a line where the atomic ratio [In]:[M]:[Zn] is 1:2:β, a line where the atomic ratio [In]:[M]:[Zn] is 1:3:β, a line where the atomic ratio [In]:[M]:[Zn] is 1:4:β, a line where the atomic ratio [In]:[M]:[Zn] is 2:1:β, and a line where the atomic ratio [In]:[M]:[Zn] is 5:1:β.

FIGS. 2A and 2B show examples of the preferred ranges of the atomic ratio of indium, the element M, and zinc contained in an oxide in one embodiment of the present invention.

FIG. 3 shows an example of the crystal structure of InMZnO4 whose atomic ratio [In]:[M]:[Zn] is 1:1:1. The crystal structure shown in FIG. 3 is InMZnO4 observed from a direction parallel to a b-axis. Note that a metal element in a layer that contains M, Zn, and oxygen (hereinafter, this layer is referred to as an “(M,Zn) layer”) in FIG. 3 represents the element M or zinc. In that case, the proportion of the element M is the same as the proportion of zinc. The element M and zinc can be replaced with each other, and their arrangement is random.

InMZnO4 has a layered crystal structure (also referred to as a layered structure) and includes one layer that contains indium and oxygen (hereinafter referred to as an In layer) for every two (M,Zn) layers that contain the element M, zinc, and oxygen, as shown in FIG. 3.

Indium and the element M can be replaced with each other. Therefore, when the element M in the (M,Zn) layer is replaced with indium, the layer can also be referred to as an (In,M,Zn) layer. In that case, a layered structure that contains one In layer for every two (In,M,Zn) layers is obtained.

An oxide whose atomic ratio [In]:[M]:[Zn] is 1:1:2 has a layered structure that contains one In layer for every three (M,Zn) layers. In other words, if [Zn] is larger than [In] and [M], the proportion of the (M,Zn) layer to the In layer becomes higher when the oxide is crystallized.

Note that in the case where the number of (M,Zn) layers with respect to one In layer is not an integer in the oxide, the oxide might have plural kinds of layered structures where the number of (M,Zn) layers with respect to one In layer is an integer. For example, in the case of [In]:[M]:[Zn]=1:1:1.5, the oxide might have the following layered structures: a layered structure of one In layer for every two (M,Zn) layers and a layered structure of one In layer for every three (M,Zn) layers.

For example, in the case where the oxide is deposited with a sputtering apparatus, a film having an atomic ratio deviated from the atomic ratio of a target is formed. In particular, [Zn] in the film might be smaller than [Zn] in the target depending on the substrate temperature in deposition.

A plurality of phases (e.g., two phases or three phases) exist in the oxide in some cases. For example, with an atomic ratio [In]:[M]:[Zn] that is close to 0:2:1, two phases of a spinel crystal structure and a layered crystal structure are likely to exist. In addition, with an atomic ratio [In]:[M]:[Zn] that is close to 1:0:0, two phases of a bixbyite crystal structure and a layered crystal structure are likely to exist. In the case where a plurality of phases exist in the oxide, a grain boundary might be formed between different crystal structures.

In addition, the oxide containing indium in a higher proportion can have high carrier mobility (electron mobility). This is because in an oxide containing indium, the element M, and zinc, the s orbital of heavy metal mainly contributes to carrier transfer, and when the indium content in the oxide is increased, overlaps of the s orbitals of indium atoms are increased; therefore, an oxide having a high content of indium has higher carrier mobility than an oxide having a low content of indium.

In contrast, when the indium content and the zinc content in an oxide become lower, carrier mobility becomes lower. Thus, with an atomic ratio of [In]:[M]:[Zn]=0:1:0 and the vicinity thereof (e.g., a region C in FIG. 2C), insulation performance becomes better.

Accordingly, an oxide of one embodiment of the present invention preferably has an atomic ratio represented by a region A in FIG. 2A. With the atomic ratio, a layered structure with high carrier mobility and a few grain boundaries is easily obtained.

A region B in FIG. 2B represents an atomic ratio of [In]:[M]:[Zn]=4:2:3 or 4:2:4.1 and the vicinity thereof. The vicinity includes an atomic ratio of [In]:[M]:[Zn]=5:3:4. An oxide with an atomic ratio represented by the region B is an excellent oxide that has particularly high crystallinity and high carrier mobility.

Note that a condition where an oxide forms a layered structure is not uniquely determined by an atomic ratio. There is a difference in the degree of difficulty in forming a layered structure among atomic ratios. Even with the same atomic ratio, whether a layered structure is formed or not depends on a formation condition. Therefore, the illustrated regions each represent an atomic ratio with which an oxide has a layered structure, and boundaries of the regions A to C are not clear.

Next, the case where the oxide is used for a transistor is described.

Note that when the oxide is used for a transistor, carrier scattering or the like at a grain boundary can be reduced; thus, the transistor can have high field-effect mobility. In addition, the transistor can have high reliability.

An oxide with low carrier density is preferably used for the transistor. For example, an oxide whose carrier density is lower than 8×1011/cm3, preferably lower than 1×1011/cm3, more preferably lower than 1×1010/cm3, and greater than or equal to 1×10−9/cm3 is used.

A highly purified intrinsic or substantially highly purified intrinsic oxide has few carrier generation sources and thus can have a low carrier density. The highly purified intrinsic or substantially highly purified intrinsic oxide has a low density of defect states and accordingly has a low density of trap states in some cases.

Charge trapped by the trap states in the oxide takes a long time to be released and may behave like fixed charge. Thus, a transistor whose channel region is formed in an oxide having a high density of trap states has unstable electrical characteristics in some cases.

In order to obtain stable electrical characteristics of the transistor, it is effective to reduce the concentration of impurities in the oxide. In addition, in order to reduce the concentration of impurities in the oxide, the concentration of impurities in a film that is adjacent to the oxide is preferably reduced. Examples of impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, and silicon.

Here, the influence of impurities in the oxide is described.

When silicon or carbon that is one of Group 14 elements is contained in the oxide, defect states are formed. Thus, the concentration of silicon or carbon in the oxide and around an interface with the oxide (measured by secondary ion mass spectrometry (SIMS)) is set lower than or equal to 2×1018 atoms/cm3, and preferably lower than or equal to 2×1017 atoms/cm3.

When the oxide contains alkali metal or alkaline earth metal, defect states are formed and carriers are generated, in some cases. Thus, a transistor including an oxide that contains alkali metal or alkaline earth metal is likely to be normally-on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide. Specifically, the concentration of alkali metal or alkaline earth metal of the oxide, which is measured by SIMS, is set lower than or equal to 1×1018 atoms/cm3, and preferably lower than or equal to 2×1016 atoms/cm3.

When the oxide contains nitrogen, the oxide easily becomes n-type by generation of electrons serving as carriers and an increase of carrier density. Thus, a transistor whose semiconductor includes an oxide that contains nitrogen is likely to be normally-on. For this reason, nitrogen in the oxide is preferably reduced as much as possible; the nitrogen concentration of the oxide, which is measured by SIMS, is set, for example, lower than 5×1019 atoms/cm3, preferably lower than or equal to 5×1018 atoms/cm3, further preferably lower than or equal to 1×1018 atoms/cm3, and still further preferably lower than or equal to 5×1017 atoms/cm3.

Hydrogen contained in an oxide reacts with oxygen bonded to a metal atom to be water, and thus causes an oxygen vacancy, in some cases. Due to entry of hydrogen into the oxygen vacancy, an electron serving as a carrier is generated in some cases. Furthermore, in some cases, bonding of part of hydrogen to oxygen bonded to a metal atom causes generation of an electron serving as a carrier. Thus, a transistor including an oxide that contains hydrogen is likely to be normally-on. Accordingly, it is preferable that hydrogen in the oxide be reduced as much as possible. Specifically, the hydrogen concentration of the oxide, which is measured by SIMS, is set lower than 1×1020 atoms/cm3, preferably lower than 1×1019 atoms/cm3, further preferably lower than 5×1018 atoms/cm3, and still further preferably lower than 1×1018 atoms/cm3.

When an oxide with sufficiently reduced impurity concentration is used for a channel formation region in a transistor, the transistor can have stable electrical characteristics.

Next, the case where the oxide has a two-layer structure or a three-layer structure is described. A band diagram of insulators that are in contact with a stacked-layer structure of the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 and a band diagram of insulators that are in contact with a stacked-layer structure of the oxide semiconductor layer 122 and the oxide insulating layer 123 are described with reference to FIGS. 4A and 4B.

FIG. 4A is an example of the band diagram of a stacked-layer structure including an insulator I1, the oxide insulating layer 121, the oxide semiconductor layer 122, the oxide insulating layer 123, and an insulator I2 in a film thickness direction. FIG. 4B is an example of the band diagram of a stacked-layer structure including the insulator I1, the oxide semiconductor layer 122, the oxide insulating layer 123, and the insulator I2 in a film thickness direction. Note that for easy understanding, the band diagrams show the energy level of the conduction band minimum (Ec) of each of the insulator I1, the oxide insulating layer 121, the oxide semiconductor layer 122, the oxide insulating layer 123, and the insulator I2.

The energy level of the conduction band minimum of each of the oxide insulating layers 121 and 123 is closer to the vacuum level than that of the oxide semiconductor layer 122. Typically, a difference in the energy level between the conduction band minimum of the oxide semiconductor layer 122 and the conduction band minimum of each of the oxide insulating layers 121 and 123 is preferably greater than or equal to 0.15 eV or greater than or equal to 0.5 eV, and less than or equal to 2 eV or less than or equal to 1 eV. In other words, it is preferable that the electron affinity of the oxide semiconductor layer 122 be greater than or equal to that of each of the oxide insulating layer 121 and the oxide insulating layer 123, and that the difference in electron affinity between the oxide semiconductor layer 122 and each of the oxide insulating layer 121 and the oxide insulating layer 123 be greater than or equal to 0.15 eV, preferably greater than or equal to 0.5 eV, and less than or equal to 2 eV, preferably less than or equal to 1 eV.

As shown in FIGS. 4A and 4B, the energy level of the conduction band minimum of each of the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 is gradually varied. In other words, the energy level of the conduction band minimum is continuously varied or continuously connected. In order to obtain such a band diagram, the density of defect states in a mixed layer formed at the interface between the oxide insulating layer 121 and the oxide semiconductor layer 122 or the interface between the oxide semiconductor layer 122 and the oxide insulating layer 123 is preferably made low.

Specifically, when the oxide insulating layer 121 and the oxide semiconductor layer 122 or the oxide semiconductor layer 122 and the oxide insulating layer 123 contain the same element (as a main component) in addition to oxygen, a mixed layer with a low density of defect states can be formed. For example, in the case where the oxide semiconductor layer 122 is an In—Ga—Zn oxide, it is preferable to use an In—Ga—Zn oxide, a Ga—Zn oxide, gallium oxide, or the like as each of the oxide insulating layers 121 and 123.

At this time, the oxide semiconductor layer 122 serves as a main carrier path. Since the density of defect states at the interface between the oxide insulating layer 121 and the oxide semiconductor layer 122 and the interface between the oxide semiconductor layer 122 and the oxide insulating layer 123 can be made low, the influence of interface scattering on carrier conduction is small, and high on-state current can be obtained.

When an electron is trapped in a trap state, the trapped electron behaves like fixed charge; thus, the threshold voltage of the transistor shifts in a positive direction. The oxide insulating layers 121 and 123 can make the trap state apart from the oxide semiconductor layer 122. This structure can prevent the positive shift of the threshold voltage of the transistor.

A material whose conductivity is sufficiently lower than that of the oxide semiconductor layer 122 is used for the oxide insulating layers 121 and 123. In that case, the oxide semiconductor layer 122, the interface between the oxide insulating layer 121 and the oxide semiconductor layer 122, and the interface between the oxide semiconductor layer 122 and the oxide insulating layer 123 mainly function as a channel region. For example, an oxide with high insulation performance and the atomic ratio represented by the region C in FIG. 2C may be used as the oxide insulating layers 121 and 123. The region C in FIG. 2C shows the atomic ratio of [In]:[M]:[Zn]=0:1:0 or a neighborhood thereof.

In the case where an oxide with the atomic ratio represented by the region A in FIG. 2A is used as the oxide semiconductor layer 122, it is particularly preferable to use an oxide with an atomic ratio where [M]/[In] is greater than or equal to 1, preferably greater than or equal to 2 as each of the oxide insulating layers 121 and 123. In addition, it is suitable to use an oxide with sufficiently high insulation performance and an atomic ratio where [M]/([Zn]+[In]) is greater than or equal to 1 as the oxide insulating layer 123.

<<Source Electrode Layer 130 and Drain Electrode Layer 140>>

The source electrode layer 130 and the drain electrode layer 140 can include materials such as aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), copper (Cu), yttrium (Y), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), silver (Ag), tantalum (Ta), tungsten (W), gold (Au), platinum (Pt), palladium (Pd), silicon (Si), iridium (Ir), iron (Fe), manganese (Mn), nitrogen (N), and oxygen (O). Each of the source electrode layer 130 and the drain electrode layer 140 can have a stacked layer structure. When a stacked-layer structure is employed, the above materials may be combined with a material containing nitrogen, such as a nitride of any of the above materials. In addition, tantalum nitride is preferable because it has an effect of suppressing diffusion of hydrogen and oxygen (a barrier property) and shows high resistance to oxidation.

<<Gate Insulating Layer 150>>

The gate insulating layer 150 can contain oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (Hf), tantalum (Ta), titanium (Ti), or the like. For example, the gate insulating layer 150 can contain one or more of aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride oxide (SiNxOy), silicon nitride (SiNx), gallium oxide (GaOx), germanium oxide (GeOx), yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx), neodymium oxide (NdOx), hafnium oxide (HfOx), and tantalum oxide (TaOx). The gate insulating layer 150 may be a stack of any of the above materials. The gate insulating layer 150 may contain lanthanum (La), nitrogen (N), zirconium (Zr), or the like as an impurity. Note that in this specification, oxynitride contains more oxygen than nitrogen, and nitride oxide contains more nitrogen than oxygen.

The gate insulating layer 150 preferably contains a large amount of oxygen. Oxygen contained in the gate insulating layer 150 reaches the oxide semiconductor layer 122 through the oxide insulating layer 123 by heat treatment. Accordingly, oxygen vacancies in the oxide semiconductor layer 122 can be reduced.

An example of a material of the gate insulating layer 150 will be described. The gate insulating layer 150 contains, for example, oxygen, nitrogen, silicon, or hafnium. Specifically, the gate insulating layer 150 preferably contains hafnium oxide, and silicon oxide or silicon oxynitride.

Hafnium oxide has higher dielectric constant than silicon oxide and silicon oxynitride. Therefore, the gate insulating layer 150 using hafnium oxide can have larger thickness than the gate insulating layer 150 using silicon oxide, so that leakage current due to tunnel current can be reduced. That is, it is possible to provide a transistor with a low off-state current. Moreover, hafnium oxide with a crystalline structure has higher dielectric constant than hafnium oxide with an amorphous structure. Therefore, it is preferable to use hafnium oxide with a crystalline structure in order to provide a transistor with a low off-state current. Examples of the crystalline structure include a monoclinic crystal structure and a cubic crystal structure. Note that one embodiment of the present invention is not limited to the above examples.

A surface over which the hafnium oxide having a crystal structure is formed might have interface states due to defects. The interface state serves as a trap center in some cases. Therefore, in the case where the hafnium oxide is provided close to the channel formation region of the transistor, the electrical characteristics of the transistor might deteriorate owing to the adverse effect of carrier traps on the interface state. In order to reduce the adverse effect of carrier traps on the interface state, in some cases, it is preferable to separate the channel formation region of the transistor and the hafnium oxide from each other by providing another film therebetween. The film has a buffer function. The film having a buffer function may be a film including a material included in the gate insulating layer 150 or a film including a material included in the oxide semiconductor layer 122. For example, the film having a buffer function can be formed using silicon oxide, silicon oxynitride, an oxide semiconductor, or the like. Note that the film having a buffer function is formed using, for example, a semiconductor or an insulator having a larger energy gap than a semiconductor including a channel formation region. Alternatively, the film having a buffer function is formed using, for example, a semiconductor or an insulator having lower electron affinity than a semiconductor including a channel formation region. Further alternatively, for example, an insulator or a semiconductor having larger ionization energy than a semiconductor including a channel formation region is used for the film having a buffering function.

In some cases, the threshold voltage of a transistor can be controlled by trapping an electric charge in an interface state (trap center) at the surface over which the hafnium oxide with a crystalline structure is formed. In order to make the electric charge exist stably, for example, an insulator having a larger energy gap than hafnium oxide may be provided between the channel formation region and the hafnium oxide. Alternatively, a semiconductor or an insulator having smaller electron affinity than the hafnium oxide is provided. Alternatively, a semiconductor or an insulator having smaller ionization energy than the hafnium oxide is provided. Use of such a semiconductor or an insulator inhibits discharge of the charge trapped by the interface states, so that the charge can be retained for a long time.

Examples of such an insulator include silicon oxide and silicon oxynitride. In order to make the interface state in the gate insulating layer 150 trap an electric charge, an electron is transferred from the oxide semiconductor layer 122 toward the gate electrode layer 160. As a specific example, a positive potential which is higher than the potential of a source or a drain is applied to the gate electrode layer 160 for one millisecond or longer at high temperatures (e.g., a temperature higher than or equal to 125° C. and lower than or equal to 450° C., typically higher than or equal to 150° C. and lower than or equal to 300° C.).

The threshold voltage of a transistor in which a predetermined amount of electrons are trapped in interface states in the gate insulating layer 150 or the like shifts in the positive direction. The amount of electrons to be trapped (the amount of change in threshold voltage) can be controlled by adjusting a voltage applied to the gate electrode layer 160 or time in which the voltage is applied. Note that a location in which an electric charge is trapped is not necessarily limited to the inside of the gate insulating layer 150. An electron may be trapped in another insulating layer using a film having a similar structure.

<<Gate Electrode Layer 160>>

The gate electrode layer 160 can contain a material such as aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), copper (Cu), yttrium (Y), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), silver (Ag), tantalum (Ta), tungsten (W), gold (Au), platinum (Pt), palladium (Pd), or silicon (Si). The gate electrode layer 160 may have a stacked-layer structure. When a stacked-layer structure is employed, the above materials may be combined with a material containing nitrogen, such as a nitride of any of the above materials. In addition, tantalum nitride is preferable because it has an effect of suppressing diffusion of hydrogen and oxygen (a barrier property) and shows high resistance to oxidation.

<<Insulating Layer 180>>

The insulating layer 180 can be formed using a material similar to that of the gate insulating layer 150.

The insulating layer 180 may be a stack. The insulating layer 180 preferably contains oxygen more than that in the stoichiometric composition. Oxygen released from the insulating layer 180 can be diffused into the channel formation region in the oxide semiconductor layer 122 through the gate insulating layer 150, so that oxygen vacancies formed in the channel formation region can be filled with the oxygen. As a result, oxygen vacancies in the oxide semiconductor layer 122 are reduced, whereby stable electrical characteristics of a transistor can be obtained.

<<Conductive Layer 190>>

The conductive layer 190 can be formed using a material similar to that of the gate electrode layer 160.

<<Conductive Layer 195>>

The conductive layer 195 can be formed using a material similar to that of the gate electrode layer 160.

<Method for Manufacturing Transistor>

Next, a manufacturing method of a transistor of this embodiment will be described with reference to FIGS. 5A to 5D, FIGS. 6A and 6B, FIGS. 7A to 7C, FIGS. 8A to 8C, FIGS. 9A to 9C, FIGS. 10A to 10C, FIGS. 11A to 11C, FIGS. 12A to 12C, FIGS. 13A to 13C, FIGS. 14A to 14C, FIGS. 15A to 15C, FIGS. 16A to 16C, FIGS. 17A to 17C, and FIGS. 18A to 18C. Note that the same parts as those in the above transistor structure are not described here. The direction of A1-A2 and that of A3-A4 in FIGS. 5A to 18C are respectively referred to as a channel length direction as in FIGS. 1A and 1B and a channel width direction as in FIGS. 1A and 1C in some cases.

In this embodiment, the layers included in the transistor (i.e., the insulating layer, the oxide semiconductor layer, the conductive layer, and the like) can be formed by any of a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, and a pulsed laser deposition (PLD) method. Alternatively, a coating method or a printing method can be used. Although the sputtering method and a plasma CVD method are typical examples of the film formation method, a thermal CVD method may be used. As the thermal CVD method, a metal organic chemical vapor deposition (MOCVD) method or an atomic layer deposition (ALD) method may be used, for example. As the sputtering method, a combination of a long throw sputtering method and a collimated sputtering method is employed, whereby the embeddability can be improved.

<Thermal CVD Method>

A thermal CVD method has an advantage that no defect due to plasma damage is generated since it does not utilize plasma for forming a film.

Deposition by a thermal CVD method may be performed in such a manner that a source gas and an oxidizer are supplied to a chamber at the same time, the pressure in the chamber is set to an atmospheric pressure or a reduced pressure, and reaction is caused in the vicinity of the substrate or over the substrate.

The variety of films such as the metal film, the semiconductor film, and the inorganic insulating film which have been disclosed in the above embodiment can be formed by a thermal CVD method such as a MOCVD method or an ALD method. For example, in the case where an In—Ga—Zn—O film is formed, trimethylindium, trimethylgallium, and dimethylzinc can be used. Note that the chemical formula of trimethylindium is In(CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3. The chemical formula of dimethylzinc is Zn(CH3)2. Without limitation to the above combination, triethylgallium (chemical formula: Ga(C2H5)3) can be used instead of trimethylgallium and diethylzinc (chemical formula: Zn(C2H5)2) can be used instead of dimethylzinc.

<ALD Method>

In a conventional deposition apparatus utilizing a CVD method, one or more kinds of source gases (precursors) for reaction are supplied to a chamber at the same time at the time of deposition. In a deposition apparatus utilizing an ALD method, precursors for reaction are sequentially introduced into a chamber, and then the sequence of the gas introduction is repeated. For example, two or more kinds of precursors are sequentially supplied to the chamber by switching respective switching valves (also referred to as high-speed valves). For example, a first precursor is introduced, an inert gas (e.g., argon or nitrogen) or the like is introduced after the introduction of the first precursor so that the plural kinds of precursors are not mixed, and then a second precursor is introduced. Alternatively, the first precursor may be exhausted by vacuum evacuation instead of the introduction of the inert gas, and then the second precursor may be introduced.

FIGS. 5A to 5D illustrate a deposition process by an ALD method. First precursors 601 are adsorbed onto a substrate surface (see FIG. 5A), whereby a first monolayer is formed (see FIG. 5B). At this time, metal atoms and the like included in the precursors can be bonded to hydroxyl groups that exist at the substrate surface. The metal atoms may be bonded to alkyl groups such as methyl groups or ethyl groups. The first monolayer reacts with second precursors 602 introduced after the first precursors 601 are evacuated (see FIG. 5C), whereby a second monolayer is stacked over the first monolayer. Thus, a thin film is formed (see FIG. 5D). For example, in the case where an oxidizer is included in the second precursors, the oxidizer chemically reacts with metal atoms included in the first precursors or an alkyl group bonded to metal atoms, whereby an oxide film can be formed.

An ALD method is a deposition method based on a surface chemical reaction, by which precursors are adsorbed onto a surface and adsorbing is stopped by a self-terminating mechanism, whereby a layer is formed. For example, precursors such as trimethylaluminum react with hydroxyl groups (OH groups) that exist at the surface. At this time, only a surface reaction due to heat occurs; therefore, the precursors come into contact with the surface and metal atoms or the like in the precursors can be adsorbed onto the surface through thermal energy. The precursors have characteristics of, for example, having a high vapor pressure, being thermally stable before being deposited and not dissolving, and being chemically adsorbed onto a substrate at a high speed. Since the precursors are introduced in a state of a gas, when the precursors, which are alternately introduced, have enough time to be diffused, a film can be formed with good coverage even onto a region having unevenness with a high aspect ratio.

In an ALD method, the sequence of the gas introduction is repeated a plurality of times until a desired thickness is obtained, whereby a thin film with excellent step coverage can be formed. The thickness of the thin film can be adjusted by the number of repetition times of the sequence of the gas introduction; therefore, an ALD method makes it possible to accurately adjust a thickness. The deposition rate can be increased and the impurity concentration in the film can be further reduced by improving the evacuation capability.

ALD methods include an ALD method using heating (thermal ALD method) and an ALD method using plasma (plasma ALD method). In the thermal ALD method, precursors react using thermal energy, and in the plasma ALD method, precursors react in a state of a radical.

When a film is deposited by an ALD method, an extremely thin film can be deposited with high accuracy. In addition, even the coverage of an uneven surface with the film can be improved by forming a film with an ALD method.

<Plasma ALD>

When the plasma ALD method is employed, the film can be formed at a lower temperature than when an ALD method without using plasma is employed. With a plasma ALD method, for example, the film can be formed without decreasing the deposition rate even at 100° C. or lower. Moreover, in a plasma ALD method, plasma can render nitrogen a radical; thus, a nitride film as well as an oxide film can be formed.

In addition, oxidizability of an oxidizer can be enhanced by the plasma ALD method. By the plasma ALD method, precursors remaining in the film or organic components released from precursors can be reduced. In addition, carbon, chlorine, hydrogen, and the like in the film can be reduced. Therefore, a film with low impurity concentration can be formed.

In the case of using a plasma ALD method, plasma can be generated from a place apart from the substrate like inductively coupled plasma (ICP) or the like, so that plasma damage to the substrate or a protective film of the substrate can be inhibited.

As described above, with the plasma ALD method, the process temperature can be lowered and the coverage of the surface can be increased as compared with other deposition methods.

<ALD Apparatus>

FIG. 6A illustrates an example of a deposition apparatus utilizing an ALD method. The deposition apparatus utilizing an ALD method includes a deposition chamber (chamber 1701), source material supply portions 1711a and 1711b, high-speed valves 1712a and 1712b which are flow rate controllers, source material introduction ports 1713a and 1713b, a source material exhaust port 1714, and an evacuation unit 1715. The source material introduction ports 1713a and 1713b provided in the chamber 1701 are connected to the source material supply portions 1711a and 1711b, respectively, through supply tubes and valves. The source material exhaust port 1714 is connected to the evacuation unit 1715 through an exhaust tube, a valve, and a pressure controller.

A substrate holder 1716 with a heater is provided in the chamber, and a substrate 1700 over which a film is deposited is provided over the substrate holder 1716.

In the source material supply portions 1711a and 1711b, a precursor is formed from a solid source material or a liquid source material by using a vaporizer, a heating unit, or the like. Alternatively, the source material supply portions 1711a and 1711b may supply a precursor in a gas state.

Although two source material supply portions 1711a and 1711b are provided in FIG. 6A, the number of source material supply portions is not limited thereto, and three or more source material supply portions may be provided. The high-speed valves 1712a and 1712b can be accurately controlled by time, and supply one of a precursor and an inert gas. The high-speed valves 1712a and 1712b are flow rate controllers for a precursor, and can also be referred to as flow rate controllers for an inert gas.

In the deposition apparatus illustrated in FIG. 6A, a thin film is formed over a surface of the substrate 1700 in the following manner: the substrate 1700 is transferred to be put on the substrate holder 1716, the chamber 1701 is sealed, the substrate 1700 is heated to a desired temperature (e.g., higher than or equal to 100° C. or higher than or equal to 150° C.) by heating the substrate holder 1716 with a heater; and supply of a precursor, evacuation with the evacuation unit 1715, supply of an inert gas, and evacuation with the evacuation unit 1715 are repeated.

In the deposition apparatus illustrated in FIG. 6A, an insulating layer formed using an oxide (including a composite oxide) containing one or more elements selected from hafnium, aluminum, tantalum, zirconium, and the like can be deposited by selecting as appropriate a source material (e.g., a volatile organometallic compound) used for the source material supply portions 1711a and 1711b. Specifically, it is possible to deposit an insulating layer including hafnium oxide, an insulating layer including aluminum oxide, an insulating layer including hafnium silicate, or an insulating layer including aluminum silicate. Alternatively, a thin film, e.g., a metal layer such as a tungsten layer or a titanium layer, or a nitride layer such as a titanium nitride layer can be deposited by selecting as appropriate a source material (e.g., a volatile organometallic compound) used for the source material supply portions 1711a and 1711b.

For example, in the case where a hafnium oxide layer is formed with a deposition apparatus using an ALD method, two kinds of gases, i.e., ozone (O3) as an oxidizer and a precursor which is obtained by vaporizing liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide or hafnium amide such as tetrakis(dimethylamide)hafnium (TDMAH)), are used. In this case, the first precursor supplied from the source material supply portion 1711a is TDMAH, and the second precursor supplied from the source material supply portion 1711b is ozone. Note that the chemical formula of tetrakis(dimethylamide)hafnium is Hf[N(CH3)2]4. Examples of another material include tetrakis(ethylmethylamide)hafnium. Note that nitrogen has a function of eliminating charge trap states. Therefore, when the precursor contains nitrogen, a hafnium oxide film having low density of charge trap states can be deposited.

For example, in the case where an aluminum oxide layer is formed with a deposition apparatus utilizing an ALD method, two kinds of gases, i.e., H2O as an oxidizer and a precursor which is obtained by vaporizing liquid containing a solvent and an aluminum precursor compound (e.g., trimethylaluminum (TMA)), are used. In this case, the first precursor supplied from the source material supply portion 1711a is TMA, and the second precursor supplied from the source material supply portion 1711b is H2O. Note that the chemical formula of trimethylaluminum is Al(CH3)3. Examples of another material liquid include tris(dimethylamide)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate).

For example, in the case where a silicon oxide film is formed with a deposition apparatus using an ALD method, hexachlorodisilane is adsorbed on a surface where a film is to be formed, chlorine contained in the adsorbate is removed, and radicals of an oxidizing gas (e.g., O3 or dinitrogen monoxide) are supplied to react with the adsorbate.

For example, in the case where a tungsten film is deposited using a deposition apparatus employing ALD, a WF6 gas and a B2H6 gas are sequentially introduced plural times to form an initial tungsten film, and then a WF6 gas and an H2 gas are sequentially introduced plural times to form a tungsten film. Note that an SiH4 gas may be used instead of a B2H6 gas.

For example, in the case where an oxide semiconductor film, e.g., an In—Ga—Zn—O film is deposited using a deposition apparatus employing ALD, an In(CH3)3 gas and an O3 gas are sequentially introduced plural times to form an In—O layer, a Ga(CH3)3 gas and an O3 gas are sequentially introduced plural times to form a GaO layer, and then a Zn(CH3)2 gas and an O3 gas are sequentially introduced plural times to form a ZnO layer. Note that the order of these layers is not limited to this example. A mixed compound layer such as an In—Ga—O layer, an In—Zn—O layer, or a Ga—Zn—O layer may be formed by mixing these gases. Although an H2O gas which is obtained by bubbling water with an inert gas such as Ar may be used instead of an O3 gas, it is preferable to use an O3 gas, which does not contain H. Instead of an In(CH3)3 gas, an In(C2H5)3 gas may be used.

<Multi-Chamber Deposition Apparatus>

FIG. 6B illustrates an example of a multi-chamber manufacturing apparatus including at least one deposition apparatus illustrated in FIG. 6A.

In the manufacturing apparatus illustrated in FIG. 6B, a stack of films can be successively deposited without exposure to the air, and entry of impurities is prevented and throughput is improved.

The manufacturing apparatus illustrated in FIG. 6B includes at least a load chamber 1702, a transfer chamber 1720, a pretreatment chamber 1703, a chamber 1701 which is a deposition chamber, and an unload chamber 1706. Note that in order to prevent attachment of moisture, the chambers of the manufacturing apparatus (including a load chamber, a transfer chamber, a pretreatment chamber, a deposition chamber, an unload chamber, and the like) are preferably filled with an inert gas (such as a nitrogen gas) whose dew point is controlled and further preferably maintain reduced pressure.

Chambers 1704 and 1705 may be deposition apparatuses utilizing an ALD method like the chamber 1701, deposition apparatuses utilizing a plasma CVD method, deposition apparatuses utilizing a sputtering method, or deposition apparatuses utilizing a MOCVD method.

For example, an example in which a stack of films is formed in the case where the chamber 1704 is a deposition apparatus utilizing a plasma CVD method and the chamber 1705 is a deposition apparatus utilizing an MOCVD method is described below.

Although FIG. 6B illustrates an example in which a top view of the transfer chamber 1720 is a hexagon, a manufacturing apparatus in which the top surface shape is set to a polygon having more than six corners and more chambers are connected depending on the number of layers of a stack may be used. The top surface shape of the substrate is rectangular in FIG. 6B; however, there is no particular limitation on the top surface shape of the substrate. Although FIG. 6B illustrates an example of the single wafer type, a batch-type deposition apparatus in which films are deposited on a plurality of substrates at a time may be used.

<Formation of Insulating Layer 110>

First, the insulating layer 110 is deposited over the substrate 100. The insulating layer 110 can be formed by a plasma CVD method, a thermal CVD method (an MOCVD method, or an ALD method), a sputtering method, or the like using an oxide insulating film of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon oxyfluoride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, or the like, a nitride insulating film of silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, or the like, or a mixed material of any of these. Alternatively, a stack of the above materials may be used.

The use of a material that contains no hydrogen or a material that contains hydrogen 1 at % or lower for the insulating layer 110 can prevent oxygen vacancies from being generated in the oxide semiconductor, leading to stable operation of the transistor.

As the insulating layer 110, for example, a 100-nm-thick silicon oxynitride film formed by a plasma CVD method can be used.

Next, first heat treatment may be performed to release water, hydrogen, or the like contained in the insulating layer 110. As a result, the concentration of water, hydrogen, or the like contained in the insulating layer 110 can be reduced. The heat treatment can reduce the amount of water, hydrogen, or the like diffused into a first oxide insulating film that is to be formed later.

The temperature of the first heat treatment is higher than or equal to 250° C. and lower than the strain point of the substrate, preferably higher than or equal to 300° C. and lower than or equal to 650° C., further preferably higher than or equal to 350° C. and lower than or equal to 550° C.

The first heat treatment is preferably performed under an inert gas atmosphere containing nitrogen or a rare gas such as helium, neon, argon, xenon, or krypton. Further, after heat treatment performed in an inert gas atmosphere, heat treatment may be additionally performed in an oxygen atmosphere or a dry air atmosphere (air whose dew point is lower than or equal to −80° C., preferably lower than or equal to −100° C. and further preferably lower than or equal to −120° C.). The treatment may be performed under reduced pressure. Note that it is preferable that hydrogen, water, and the like not be contained in an inert gas and oxygen, like the dry air, and the dew point is lower than or equal to −80° C. and preferably lower than or equal to −100° C. The treatment time is preferably 30 seconds to 24 hours.

In the first heat treatment, instead of an electric furnace, any device for heating an object by heat conduction or heat radiation from a heating element, such as a resistance heating element, may be used. For example, an RTA (rapid thermal annealing) apparatus, such as a GRTA (gas rapid thermal annealing) apparatus or an LRTA (lamp rapid thermal annealing) apparatus, can be used. The LRTA apparatus is an apparatus for heating an object to be processed by radiation of light (an electromagnetic wave) emitted from a lamp, such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. The GRTA apparatus is an apparatus for the heat treatment using a high-temperature gas. As the high-temperature gas, an inert gas, such as nitrogen or a rare gas like argon, is used.

<Formation of First Oxide Insulating Film and Oxide Semiconductor Film>

Then, the first oxide insulating film 121a to be the oxide insulating layer 121 later and the oxide semiconductor film 122a to be the oxide semiconductor layer 122 later are deposited over the insulating layer 110 (see FIGS. 7A to 7C). The first oxide insulating film 121a and the oxide semiconductor film 122a can be formed by a sputtering method, an MOCVD method, a PLD method, or the like, and especially, a sputtering method is preferable. As a sputtering method, an RF sputtering method, a DC sputtering method, an AC sputtering method, or the like can be used. In addition, a facing-target-type sputtering method (also referred to as a counter-electrode-type sputtering method, a gas phase sputtering method, and a vapor deposition sputtering (VDSP) method) is used, whereby plasma damage at the deposition can be reduced.

When the oxide semiconductor film 122a is formed by a sputtering method, for example, it is preferable that each chamber of the sputtering apparatus be able to be evacuated to a high vacuum (approximately 5×10−7 Pa to 1×10−4 Pa) by an adsorption vacuum pump such as a cryopump, and that the chamber be able to heat a substrate over which a film is to be deposited to 100° C. or higher, preferably 400° C. or higher, so that water and the like acting as impurities in the oxide semiconductor layer 122 can be removed as much as possible. Alternatively, a combination of a turbo molecular pump and a cold trap is preferably used to prevent back-flow of a gas containing a carbon component, moisture, or the like from an exhaust system into the chamber. Alternatively, a combination of a turbo molecular pump and a cryopump may be used as an exhaust system.

Not only high vacuum evacuation in a chamber but also high purity of a sputtering gas is desirable to obtain a highly purified intrinsic oxide semiconductor layer 122. As an oxygen gas or an argon gas used as a sputtering gas, a highly purified gas having a dew point of −40° C. or lower, preferably −80° C. or lower and further preferably −100° C. or lower, is used, whereby moisture or the like can be prevented from entering an oxide semiconductor film 122a as much as possible.

As a sputtering gas, a rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen can be used as appropriate.

Note that for example, in the case where the oxide semiconductor film 122a is formed by a sputtering method at a substrate temperature higher than or equal to 20° C. and lower than or equal to 750° C., preferably higher than or equal to 150° C. and lower than or equal to 450° C. and further preferably higher than or equal to 200° C. and lower than or equal to 420° C., the oxide semiconductor film 122a can be a CAAC-OS (c-axis-aligned crystalline oxide semiconductor) film.

The material for the first oxide insulating film 121a is desirably selected so that the first oxide insulating film 121a can have a lower electron affinity than the oxide semiconductor film 122a.

For example, when a sputtering method is used to form the first oxide insulating film 121a and the oxide semiconductor film 122a, the first oxide insulating film 121a and the oxide semiconductor film 122a can be successively formed without being exposed to the air with the use of a multi-chamber sputtering apparatus. In that case, entry of unnecessary impurities and the like into the interface between the first oxide insulating film 121a and the oxide semiconductor film 122a can be prevented and interface states can be reduced accordingly. Thus, the electrical characteristics of a transistor 10 can be stabilized, particularly after the reliability test.

If the insulating layer 110 is damaged, the oxide semiconductor layer 122, which is a main conduction path of the transistor 10, can keep a distance from the damaged part owing to the existence of the oxide insulating layer 121. Thus, carrier traps in the damaged part can be suppressed. Thus, the electrical characteristics of the transistor 10 particularly after a reliability test can be stabilized.

For example, as the first oxide insulating film 121a, a 20-nm-thick insulating film formed by a sputtering method using a target having an atomic ratio of In:Ga:Zn=1:3:4 can be used. In addition, as the oxide semiconductor film 122a, a 15-nm-thick oxide semiconductor film formed by a sputtering method using a target having an atomic ratio of In:Ga:Zn=1:1:1 can be used.

Note that the amount of oxygen vacancies in the oxide semiconductor film 122a can be reduced by performing second heat treatment after the first oxide insulating film 121a and the oxide semiconductor film 122a are deposited.

The temperature of the second heat treatment is higher than or equal to 250° C. and lower than the strain point of the substrate, preferably higher than or equal to 300° C. and lower than or equal to 650° C., and further preferably higher than or equal to 350° C. and lower than or equal to 550° C.

The second heat treatment can be performed in a manner similar to the first heat treatment. For example, after heat treatment is performed at 450° C. in a nitrogen atmosphere for one hour, heat treatment is performed at 450° C. in an oxygen atmosphere for one hour.

Note that the second heat treatment may be performed after etching for forming the oxide insulating layer 121 and the oxide semiconductor layer 122 described later.

Through the above-described steps, oxygen vacancies or impurities such as hydrogen and water in the oxide semiconductor film 122a can be reduced. The oxide semiconductor film 122a can have low density of localized states.

Note that high-density plasma irradiation using oxygen can have an effect equivalent to that of the heat treatment. Irradiation time is longer than or equal to 1 minute and shorter than or equal to 3 hours, preferably longer than or equal to 3 minutes and shorter than or equal to 2 hours, and further preferably longer than or equal to 5 minutes and shorter than or equal to 1 hour.

<Formation of Insulating Layer 115>

Next, a first insulating film to be the insulating layer 115 is formed over the oxide semiconductor film 122a. The first insulating film can be formed using a material and a method similar to those of the insulating layer 110. The insulating layer 115 can be formed using an appropriate material without limitations to an insulating material as long as the insulating layer 115 has an etching rate higher than that of a conductive layer 130b which is described later.

Next, a resist mask is formed over the first insulating film by a lithography process. Note that the lithography process may be performed after an organic film is formed over the first insulating film by coating or an organic film is formed over the resist by coating. The organic film can contain propylene glycolmonomethyl ether, ethyl lactate, or the like. The use of the organic film leads to, in addition to an anti-reflection effect during light exposure, an improvement in adhesion between a resist and a film (the first insulating film or the organic film), an improvement in resolution, and the like. The organic film can also be used in another process.

With the use of the resist mask, the first insulating film is processed by a dry etching method until the oxide semiconductor film 122a is exposed. As a result of the processing, the insulating layer 115 is formed (see FIGS. 8A to 8C).

Note that a side surface of the insulating layer 115 is preferably perpendicular to a top surface of the substrate 100. In that case, the oxide semiconductor layer 122 with a minute shape can be formed stably in the subsequent steps.

Note that the processing method of the insulating layer 115 is not limited to the above method. For example, not only the resist mask but also a hard mask may be used, or a half-tone mask may be used in a lithography process to control the shape of the resist mask. Alternatively, the shape of the mask may be controlled by nanoimprint lithography or the like. The nanoimprint lithography can be used in another process.

After the formation of the insulating layer 115, the resist mask is removed.

<Formation of Conductive Layer 130b>

Next, a first conductive film 130a which is used as a hard mask is formed over the oxide semiconductor film 122a and the insulating layer 115 (see FIGS. 9A to 9C).

The first conductive film 130a is preferably formed by a chemical vapor deposition (CVD) method such as a metal CVD method or an ALD method. With use of the above method, the first conductive film 130a can be formed uniformly over top and side surfaces of the insulating layer 115 and a top surface of the oxide semiconductor film 122a.

The thickness of the first conductive film 130a is preferably greater than or equal to 4 nm and less than or equal to 40 nm.

The first conductive film 130a preferably includes at least one of aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), copper (Cu), yttrium (Y), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), silver (Ag), tantalum (Ta), tungsten (W), gold (Au), platinum (Pt), palladium (Pd), silicon (Si), iridium (Ir), iron (Fe), and manganese (Mn). The first conductive film 130a may contain nitrogen (N) or oxygen (O). The first conductive film 130a can be a single layer or a stacked layer of a conductive film containing any of the above materials, an alloy thereof, or a compound containing any of the above materials as a main component.

For example, a 20-nm-thick tungsten film can be formed by an ALD method as the first conductive film 130a.

Next, the entire surface of the first conductive film 130a is subjected to etching treatment, whereby the conductive layer 130b is formed (see FIGS. 10A to 10C). Here, the conductive layer 130b is formed along and in contact with the side surface of the insulating layer 115, so that the conductive layer 130b has a shape like a frame when seen from above. The etching treatment (etch-back treatment) is preferably performed by a dry etching method.

In the case where the conductive layer 130b is formed by the above method, the width of the conductive layer 130b can be controlled with the thickness of the first conductive film 130a. Therefore, minute processing and uniformity can be easily achieved. Through the above process, the conductive layer 130b can be formed extremely easily. With the above method, the conductive layer 130b with a width smaller than the minimum feature size can be formed. In the case of using the above method, the conductive layer 130b is formed to be in contact with a side surface of the insulating layer 115 as illustrated in FIG. 10C. Therefore, even when the width of the conductive layer 130b is thin, the conductive layer 130b does not collapse because of the support of insulating layer 115. Note that at least one of the corners of the conductive layer 130b formed at this time is rounded.

Next, the insulating layer 115 is removed by etching treatment (see FIGS. 11A to 11C). The etching treatment is preferably performed by a dry etching method

Next, a resist mask is formed over the conductive layer 130b through a lithography process. The conductive layer 130b is etched using the resist mask, so that the conductive layer 130c having an island shape is formed (see FIGS. 12A to 12C). Dry etching is preferably employed for the etching treatment. The treatment can be omitted as long as the conductive layer 130b is connected to a wiring layer as appropriate in a manufacturing process of the transistor 10. As illustrated in FIG. 12C, in the channel width direction, the conductive layer 130c has a shape the same as that of the conductive layer 130b.

<Formation of Oxide Insulating Layer 121 and Oxide Semiconductor Layer 122>

Next, the oxide semiconductor film 122a and the first oxide insulating film 121a are selectively etched using the conductive layer 130c as a hard mask, whereby the oxide semiconductor layer 122 and the oxide insulating layer 121 are formed (see FIGS. 13A to 13C). Dry etching is preferably used as the etching method.

For example, the first oxide insulating film 121a and the oxide semiconductor film 122a are selectively etched using a resist mask and a hard mask with a methane gas and an argon gas as an etching gas, whereby the oxide insulating layer 121 and the oxide semiconductor layer 122 can be formed.

Note that the use of the conductive layer 130c as a hard mask for etching of the oxide semiconductor film 122a can reduce edge roughness of the oxide semiconductor layer 122 that has been etched as compared with the case of etching with a resist mask.

<Formation of Groove Portion 174>

First, a second insulating film to be the insulating layer 175 is formed over the insulating layer 110, the oxide semiconductor layer 122, and the conductive layer 130c. The second insulating film can be formed using a material and a method similar to those of the insulating layer 110.

Then, planarization treatment is performed on the second insulating film, so that the insulating layer 175b is formed (see FIGS. 14A and 14B). The planarization treatment can be performed by a chemical mechanical polishing (CMP) method, a dry etching method, a reflow method, or the like. In the case where the CMP method is used, a film whose composition is different from that of the second insulating film is formed over the second insulating film, whereby the thickness of the insulating layer 175b in the substrate surface after the CMP treatment can be uniform.

Next, a resist mask is formed over the planarized insulating layer 175b by a lithography process. Not only the resist mask but also a hard mask may be formed.

Note that in the case where a transistor having an extremely short channel length is formed, etching is performed using a resist mask that is processed by a method suitable for micropatterning, such as electron beam exposure, liquid immersion exposure, or extreme ultraviolet (EUV) exposure. Note that in the case of forming the resist mask by electron beam exposure, a positive resist mask is used, so that an exposed region can be minimized and throughput can be improved. In the above manner, a transistor with a channel length of 100 nm or less, further, 30 nm or less, still further, 20 nm or less can be formed. Alternatively, minute processing may be performed by an exposure technology which uses X-rays or the like.

With the use of the resist mask, groove processing is performed on the insulating layer 175b by a dry etching method until the conductive layer 130c is exposed. As a result of the processing, the insulating layer 175 and the groove portion 174 are formed over the conductive layer 130c.

Note that a side surface of the groove portion 174 is preferably perpendicular to the top surface of the substrate 100.

<Formation of Source Electrode Layer 130 and Drain Electrode Layer 140>

Next, the exposed conductive layer 130c is etched by a dry etching method, whereby the source electrode layer 130 and the drain electrode layer 140 are formed (see FIGS. 15A to 15C). As illustrated in FIG. 15C, in the channel width direction, the oxide semiconductor layer 122 has a shape affected by a shape of the conductive layer 130c. Therefore, at least one of the corners of the oxide semiconductor layer 122 is rounded.

Note that heat treatment may be performed after the source electrode layer 130 and the drain electrode layer 140 are formed. The heat treatment can be performed under conditions similar to those of the second heat treatment.

<Formation of Oxide Insulating Layer 123, Gate Insulating Layer 150, and Gate Electrode Layer 160>

Next, a second oxide insulating film 123a to be the oxide insulating layer 123 is formed over the oxide semiconductor layer 122, the insulating layer 110, and the insulating layer 175. The second oxide insulating film 123a can be formed in a manner similar to that of the oxide semiconductor film 122a and the first oxide insulating film 121a. The materials can be selected such that the electron affinity of the second oxide insulating film 123a is smaller than that of the oxide semiconductor film 122a.

For example, as the second oxide semiconductor film 123a, a 5-nm-thick oxide semiconductor film which is formed by a sputtering method using a target having an atomic ratio of In:Ga:Zn=1:3:2 can be used.

Next, an insulating film 150a to be the gate insulating layer 150 is formed over the second oxide insulating film 123a. The insulating film 150a can be formed by a sputtering method, a CVD method (e.g., a plasma CVD method, an MOCVD method, or an ALD method), an MBE method, or the like. The insulating film 150a can be formed by a method similar to that of the insulating layer 110 as appropriate.

As the insulating layer 150a, for example, a 10-nm-thick silicon oxynitride film formed by a plasma CVD method can be used.

Next, the conductive film 160a to be the gate electrode layer 160 is formed over the insulating film 150a (see FIGS. 16A to 16C). The conductive film 160a can be formed by a sputtering method, a CVD method (e.g., a plasma CVD method, an MOCVD method, or an ALD method), an MBE method, an evaporation method, a plating method, or the like. The conductive film 160a may be formed using a conductive film containing nitrogen or a stack including the above conductive film and a conductive film containing nitrogen.

For example, a stack of 10-nm-thick titanium nitride deposited by an ALD method and 150-nm-thick tungsten deposited by a metal CVD method can be used for the conductive film 160a.

Then, planarization treatment is performed. The planarization treatment can be performed by a CMP method, a dry etching method, or the like. The planarization treatment may be terminated at the time when the insulating film 150a is exposed, or may be terminated at the time when the insulating layer 175 is exposed. Accordingly, the gate electrode layer 160, the gate insulating layer 150, and the oxide insulating layer 123 can be formed (see FIGS. 17A to 17C).

Next, a third insulating film to be the insulating layer 180 is formed over the insulating layer 175, the oxide insulating layer 123, the gate insulating layer 150, and the gate electrode layer 160. The third insulating film can be formed in a manner similar to that of the insulating layer 110. It is preferable to perform planarization after the formation of the third insulating film.

After that, the third insulating film is etched by a dry etching method to form an opening.

Then, a second conductive film to be the conductive layer 190 is formed in the opening, and then planarization treatment is performed, whereby the conductive layer 190 is formed.

Next, a third conductive film to be the conductive layer 195 is formed over the conductive layer 190. To form the third conductive film, the conductive layer 195 is processed by a photolithography method, a nanoimprinting method, or the like (see FIGS. 18A to 18C).

Accordingly, with one embodiment of the present invention, an extremely miniaturized transistor whose channel length is less than or equal to 30 nm, less than or equal to 20 nm, or less than or equal to 10 nm can be manufactured stably.

Note that heat treatment may be performed at any time as required in each step.

<Formation Method 2 of Oxide Semiconductor Layer 122>

Note that minute processing can be performed on the oxide insulating layer 121 and the oxide semiconductor layer 122 as illustrated in FIGS. 19A to 19C, FIGS. 20A to 20C, FIGS. 21A to 21C, FIGS. 22A to 22C, FIGS. 23A to 23C, and FIGS. 24A to 24C on the basis of the method shown in FIGS. 8A to 8C, FIGS. 9A to 9C, FIGS. 10A to 10C, FIGS. 11A to 11C, FIGS. 12A to 12C, and FIGS. 13A to 13C.

First, an insulating layer 117 is formed (see FIGS. 19A to 19C). The insulating layer 117 can be formed using a material similar to that of the insulating layer 115. The insulating layer 117 has a shape like a frame when seen from above, for example.

Next, the first conductive film 130a is formed over the oxide semiconductor film 122a and the insulating layer 117 (see FIGS. 20A to 20C).

Next, etching treatment is performed on the first conductive film 130a. The first conductive film 130a over the oxide semiconductor film 122a and the insulating layer 117 is removed by the etching treatment, whereby the conductive layer 130b is formed to have two frame-like shapes when seen from the top surface (see FIGS. 21A to 21C). After the conductive layer 130b is formed, the insulating layer 117 is removed by a dry etching method. At this time, corners of the conductive layer 130b are slightly etched to have round shapes (see FIGS. 22A to 22C).

Next, a resist mask is formed over the oxide semiconductor film 122a and the conductive layer 130b. The conductive layer 130b is subjected to dry etching treatment using the resist mask. Part of the conductive layer 130b is removed by the etching treatment, whereby the conductive layer 130c is formed to have four linear shapes when seen from above (see FIGS. 23A to 23C).

Next, the oxide semiconductor film 122a and the first oxide insulating film 121a are processed by a dry etching method using the conductive layer 130c as a hard mask, whereby the oxide semiconductor layer 122 and the oxide insulating layer 121 can be formed (see FIGS. 24A to 24C).

The density of a minute pattern can be increased with the above method. Accordingly, the density of transistors can be further increased.

<Modification Example 1 of Transistor 10: Transistor 11>

A transistor 11 with a shape different from that of the transistor 10 illustrated in FIGS. 1A to 1C will be described with reference to FIGS. 25A to 25C.

FIGS. 25A to 25C are a top view and cross-sectional views of the transistor 11. FIG. 25A is a top view of the transistor 11, FIG. 25B is a cross-sectional view taken along dashed-dotted line B1-B2 in FIG. 25A, and FIG. 25C is a cross-sectional view taken along dashed-dotted line B3-B4 in FIG. 25A.

The transistor 11 is different from the transistor 10 in that the source electrode layer 130 and the drain electrode layer 140 each have a region in contact with side surfaces of the oxide insulating layer 121 and the oxide semiconductor layer 122 and the insulating layer 110. Note that the oxide semiconductor layer 122 may have a low resistance region. Alternatively, both the oxide semiconductor layer 122 and the oxide insulating layer 123 may have low-resistance regions.

With the structure of the transistor 11, side surface portions of the oxide insulating layer 121 and the oxide semiconductor layer 122 in the channel length direction can be protected. With the structure, the on-state current can be improved. Moreover, the reliability of the transistor can be improved.

<Modification Example 2 of Transistor 10: Transistor 12>

A transistor 12 with a shape different from that of the transistor 10 illustrated in FIGS. 1A to 1C will be described with reference to FIGS. 26A to 26C.

FIGS. 26A to 26C are a top view and cross-sectional views of the transistor 12. FIG. 26A is a top view of the transistor 12, FIG. 26B is a cross-sectional view taken along dashed-dotted line C1-C2 in FIG. 26A, and FIG. 26C is a cross-sectional view taken along dashed-dotted line C3-C4 in FIG. 26A.

The transistor 12 is different from the transistor 10 in that a conductive layer 165 is provided.

<<Conductive Layer 165>>

The conductive layer 165 can be formed using a material similar to that of the gate electrode layer 160. Note that the conductive layer 165 may be a single layer or a stacked layer.

The conductive layer 165 can have a function similar to that of the gate electrode layer 160. The conductive layer 165 and the gate electrode layer 160 may be configured to be applied with the same potential or different potentials.

In the transistor 12 including the conductive layer 165, the insulating layer 110 can have a structure and a function similar to those of the gate insulating layer 150.

With the structure of the transistor 12, electrical characteristics (e.g., threshold voltage) of a transistor can be controlled.

<Modification Example 3 of Transistor 10: Transistor 13>

A transistor 13 with a shape different from that of the transistor 10 illustrated in FIGS. 1A to 1C will be described with reference to FIGS. 27A to 27C.

FIGS. 27A to 27C are a top view and cross-sectional views of the transistor 13. FIG. 27A is a top view of the transistor 13, FIG. 27B is a cross-sectional view taken along dashed-dotted line D1-D2 in FIG. 27A, and FIG. 27C is a cross-sectional view taken along dashed-dotted line D3-D4 in FIG. 27A.

The transistor 13 is different from the transistor 10 in that insulating layers 170 and 172 are provided.

<<Insulating Layer 170>>

The insulating layer 170 can contain oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (Hf), tantalum (Ta), titanium (Ti), or the like. For example, an insulating film containing one or more of aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride oxide (SiNxOy), silicon nitride (SiNx), gallium oxide (GaOx), germanium oxide (GeOx), yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx), neodymium oxide (NdOx), hafnium oxide (HfOx), and tantalum oxide (TaOx) can be used.

An aluminum oxide (AlOx) film is preferably included in the insulating layer 170. The aluminum oxide film can prevent the passage of both oxygen and impurities such as hydrogen and moisture. Accordingly, during and after the manufacturing process of the transistor, the aluminum oxide film can be suitably used as a protective film that has an effect of preventing entry of impurities such as hydrogen and moisture, which cause variations in the electrical characteristics of the transistor, into the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123, and an effect of preventing release of oxygen from the oxide insulating layer 121, the oxide semiconductor layer 122, the oxide insulating layer 123, and the insulating layer 110.

The insulating layer 170 is preferably a film having oxygen supply capability. A mixed layer is formed at an interface with the insulating layer 175 when the insulating layer 170 is formed, and oxygen is supplied to the mixed layer or the insulating layer 175. Then, the oxygen is diffused into the oxide semiconductor layer 122 by the heat treatment, whereby the oxygen vacancies in the oxide semiconductor layer 122 are filled with oxygen. Accordingly, the electrical characteristics of the transistor can be stabilized.

Furthermore, the insulating layer 170 may be a single layer or a stacked layer. For example, the insulating layer 170 can be formed using an insulating film containing one or more of magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The insulating layer 170 preferably contains oxygen more than that in the stoichiometric composition. Oxygen released from the insulating layer 170 can be diffused into the channel formation region in the oxide semiconductor layer 122 through the insulating layer 175, so that oxygen vacancies in the channel formation region can be filled with oxygen. In this manner, stable electrical characteristics of the transistor can be achieved.

<<Insulating Layer 172>>

The insulating layer 172 can contain oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (Hf), tantalum (Ta), titanium (Ti), or the like. For example, the insulating layer 172 can contain one or more of aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride oxide (SiNxOy), silicon nitride (SiNx), gallium oxide (GaOx), germanium oxide (GeOx), yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx), neodymium oxide (NdOx), hafnium oxide (HfOx), and tantalum oxide (TaOx). The insulating layer 172 may be a stack of any of the above materials.

An aluminum oxide (AlOx) film is preferably included in the insulating layer 172. The aluminum oxide film can prevent the passage of both oxygen and impurities such as hydrogen and moisture. Accordingly, during and after the manufacturing process of the transistor, the aluminum oxide film can suitably function as a protective film that has effects of preventing entry of impurities such as hydrogen and moisture, which cause variations in the electrical characteristics of the transistor, into the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123, preventing release of oxygen from the oxide insulating layer 121, the oxide semiconductor layer 122, the oxide insulating layer 123, and the insulating layer 110.

The insulating layer 172 can function as a protective film. The insulating layer 172 can protect the gate insulating layer 150 against plasma damage in the formation of the insulating layer 170. Accordingly, the electrical characteristics of the transistor can be stabilized.

<Manufacturing Method of Transistor 13>

Part of a manufacturing method of the transistor 13 will be described with reference to FIGS. 27A to 27C. In the manufacturing method of the transistor 10 (FIGS. 7A to 18C), steps shown in FIGS. 7A to 17C are similar to those in the manufacturing method of the transistor 13. For the description of the manufacturing method of the transistor 13, the description of steps similar to those in manufacturing the transistor 10 (FIGS. 7A to 17C) is referred to. The manufacturing method of the transistor 13 described below relates to the manufacturing method performed after the steps shown in FIGS. 17A to 17C.

<Formation of Insulating Layer 172>

The insulating layer 172 is formed over the oxide insulating layer 123, the gate insulating layer 150, and the gate electrode layer 160. The insulating layer 172 is preferably deposited by a metal organic chemical vapor deposition (MOCVD) method and an atomic layer deposition (ALD) method. Accordingly, damage to the oxide insulating layer 123 and the gate insulating layer 150 can be inhibited and oxidation of the gate electrode layer 160 can be inhibited.

The thickness of the insulating layer 172 is preferably greater than or equal to 1 nm and less than or equal to 30 nm, and further preferably greater than or equal to 3 nm and less than or equal to 10 nm.

The insulating layer 172 may be used as deposited or may be processed by a lithography method, a nanoimprinting method, a dry etching method, or the like.

<Formation of Insulating Layer 170>

Next, the insulating layer 170 is formed over the insulating layer 172. The insulating layer 170 may be a single layer or a stacked layer. The insulating layer 170 can be formed using a material, a method, and the like similar to those of the insulating layer 110.

The insulating layer 170 is preferably an aluminum oxide film formed by a sputtering method. Sputtering gas used for forming the aluminum oxide film preferably contains oxygen gas. The oxygen gas is contained at 1 vol % or more and 100 vol % or less, preferably 4 vol % or more and 100 vol % or less and further preferably 10 vol % or more and 100 vol % or less. When oxygen is contained at 1 vol. % or more, excess oxygen can be supplied to the insulating layer 175 in contact with the insulating layer 170. In the heat treatment, excess oxygen can be added to the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 which are in contact with the insulating layer 175.

For example, the insulating layer 170 having a thickness from 5 nm to 40 nm can be deposited by a sputtering method using aluminum oxide as a target and an oxygen gas at 50 vol %.

Next, heat treatment is preferably performed. The temperature of the heat treatment is typically higher than or equal to 150° C. and lower than the strain point of the substrate, preferably higher than or equal to 250° C. and lower than or equal to 500° C. and further preferably higher than or equal to 300° C. and lower than or equal to 450° C. By the heat treatment, oxygen 173 (exO173) added to the insulating layer 170, the insulating layer 175, the insulating layer 110, and the like is diffused and moved to the oxide semiconductor layer 122, and oxygen vacancies in the oxide semiconductor layer 122 can be filled with the oxygen (see FIGS. 28A to 28C).

For example, the heat treatment can be performed at 400° C. in an oxygen atmosphere for one hour.

Note that heat treatment may be performed in other processes. The heat treatment is performed to repair defects in the oxide semiconductor layer 122 and the gate insulating layer 150, for example. For example, the interface states between the oxide semiconductor layer 122 and the oxide insulating layer 123 can be reduced, for example.

<Oxygen Addition>

Oxygen is not necessarily added through the insulating layer 170. Oxygen may be added to the insulating layer 110, the first oxide insulating film 121a, and the oxide insulating layer 123, or another insulating layer. As the oxygen that is added, at least one selected from oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, and the like is used. As a method for adding the oxygen, an ion doping method, an ion implantation method, a plasma immersion ion implantation method, or the like can be used.

In the case of using an ion implantation method as the method for adding oxygen, oxygen atomic ions or oxygen molecular ions can be used. The use of oxygen molecular ions can reduce damage to a film to which oxygen is added as compared to the case where oxygen atomic ions are used. Oxygen molecular ions are broken down into oxygen atomic ions at the surface of the film to which oxygen is added, and the oxygen atomic ions are added. Since energy for breaking oxygen molecular ions down into oxygen atom ions is used, the energy per oxygen atomic ion in the case of adding oxygen molecular ions is lower than that in the case of adding oxygen atomic ions. Therefore, damage to the film to which oxygen is added can be reduced.

By using oxygen molecular ions, the energy per oxygen atomic ion injected to the film to which oxygen is added is lowered, which makes the injected oxygen atomic ion be positioned in a shallow region in the film. Therefore, oxygen atomic ions easily move from the film by heat treatment later, whereby more oxygen can be supplied to the oxide semiconductor layer 122.

In the case of injecting oxygen molecular ions, the energy per oxygen atomic ion is low as compared with the case of injecting oxygen atomic ions. Thus, by using oxygen molecular ions for injection, the acceleration voltage in injection can be increased as compared with the case where oxygen atomic ions are used. Moreover, by using oxygen molecular ions for injection, the dose required for injection can be half of the amount that is necessary in the case of using oxygen atomic ions. Accordingly, the time required for oxygen addition treatment is reduced, whereby throughput can be increased.

In the case of adding oxygen to the film to which oxygen is added, it is preferable that oxygen be added to the film to which oxygen is added so that a peak of the concentration profile of oxygen atomic ions is located in the film to which oxygen is added. In that case, the acceleration voltage in injection can be lowered as compared with the case where oxygen atomic ions are injected without using the above condition, and damage to the film to which oxygen is added can be reduced. In other words, defects in the film to which oxygen is added can be reduced, suppressing variations in electrical characteristics of the transistor. Specifically, in the case where oxygen is added to the film to which oxygen is added so that the amount of added oxygen atoms at the interface between the insulating layer 110 and the oxide insulating layer 121 is less than 1×1021 atoms/cm3, less than 1×1020 atoms/cm3, or less than 1×1019 atoms/cm3, the amount of oxygen added to the insulating layer 110 can be reduced. As a result, damage to the film to which oxygen is added can be reduced, suppressing variations in electrical characteristics of the transistor.

Plasma treatment (plasma immersion ion implantation method) in which the film to which oxygen is added is exposed to plasma generated in an atmosphere containing oxygen may be performed. As the oxygen-containing atmosphere, an atmosphere containing an oxidation gas such as oxygen, ozone, dinitrogen monoxide, or nitrogen dioxide can be given. Note that it is preferable that the film to which oxygen is added be exposed to the plasma in a state where bias is applied on the substrate 100 side because the amount of oxygen added to the film can be increased. As an example of an apparatus with which such plasma treatment is performed, an ashing apparatus or the like is given.

The above process is applicable to the transistor 10 and other transistors.

In this manner, the density of localized states of the oxide semiconductor layer 122 is lowered, and thus a transistor with excellent electrical characteristics can be manufactured. Furthermore, transistors with less variation in electrical characteristics can be manufactured. In addition, a highly reliable transistor with a small variation in electrical characteristics with time or due to a stress test can be manufactured.

Note that this embodiment can be combined with any of the other embodiments in this specification as appropriate.

Embodiment 2

<Structure of Oxide Semiconductor>

The structure of an oxide semiconductor is described below.

An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of a non-single-crystal oxide semiconductor include a CAAC-OS, a polycrystalline oxide semiconductor, a nanocrystalline oxide semiconductor (nc-OS), an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor.

From another perspective, an oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.

An amorphous structure is generally thought to be isotropic and have no non-uniform structure, to be metastable and not have fixed positions of atoms, to have a flexible bond angle, and to have a short-range order but have no long-range order, for example.

In other words, a stable oxide semiconductor cannot be regarded as a completely amorphous oxide semiconductor. Moreover, an oxide semiconductor that is not isotropic (e.g., an oxide semiconductor that has a periodic structure in a microscopic region) cannot be regarded as a completely amorphous oxide semiconductor. In contrast, an a-like OS, which is not isotropic, has an unstable structure that contains a void. Because of its instability, an a-like OS has physical properties similar to those of an amorphous oxide semiconductor.

<CAAC-OS>

First, a CAAC-OS is described.

A CAAC-OS is one of oxide semiconductors having a plurality of c-axis aligned crystal parts (also referred to as pellets).

Analysis of a CAAC-OS by X-ray diffraction (XRD) is described. For example, when the structure of a CAAC-OS including an InGaZnO4 crystal that is classified into the space group R-3m is analyzed by an out-of-plane method, a peak appears at a diffraction angle (2θ) of around 31° as shown in FIG. 29A. This peak is derived from the (009) plane of the InGaZnO4 crystal, which indicates that crystals in the CAAC-OS have c-axis alignment, and that the c-axes are aligned in a direction substantially perpendicular to a surface over which the CAAC-OS film is formed (also referred to as a formation surface) or the top surface of the CAAC-OS film. Note that a peak sometimes appears at a 2θ of around 36° in addition to the peak at a 2θ of around 31°. The peak at a 2θ of around 36° is derived from a crystal structure that is classified into the space group Fd-3m; thus, this peak is preferably not exhibited in a CAAC-OS.

On the other hand, in structural analysis of the CAAC-OS by an in-plane method in which an X-ray is incident on the CAAC-OS in a direction parallel to the formation surface, a peak appears at a 2θ of around 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. When analysis (φ scan) is performed with 2θ fixed at around 56° and with the sample rotated using a normal vector to the sample surface as an axis (φ axis), as shown in FIG. 29B, a peak is not clearly observed. In contrast, in the case where single crystal InGaZnO4 is subjected to φ scan with 2θ fixed at around 56°, as shown in FIG. 29C, six peaks which are derived from crystal planes equivalent to the (110) plane are observed. Accordingly, the structural analysis using XRD shows that the directions of a-axes and b-axes are irregularly oriented in the CAAC-OS.

Next, a CAAC-OS analyzed by electron diffraction is described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO4 crystal in a direction parallel to the formation surface of the CAAC-OS, a diffraction pattern (also referred to as a selected-area electron diffraction pattern) shown in FIG. 29D can be obtained. In this diffraction pattern, spots derived from the (009) plane of an InGaZnO4 crystal are included. Thus, the electron diffraction also indicates that pellets included in the CAAC-OS have c-axis alignment and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS. Meanwhile, FIG. 29E shows a diffraction pattern obtained in such a manner that an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. As shown in FIG. 29E, a ring-like diffraction pattern is observed. Thus, the electron diffraction using an electron beam with a probe diameter of 300 nm also indicates that the a-axes and b-axes of the pellets included in the CAAC-OS do not have regular orientation. The first ring in FIG. 29E is derived from the (010) plane, the (100) plane, and the like of the InGaZnO4 crystal. The second ring in FIG. 29E is derived from the (110) plane and the like.

In a combined analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of a CAAC-OS, which is obtained using a transmission electron microscope (TEM), a plurality of pellets can be observed. However, even in the high-resolution TEM image, a boundary between pellets, that is, a grain boundary is not clearly observed in some cases. Thus, in the CAAC-OS, a reduction in electron mobility due to the grain boundary is less likely to occur.

FIG. 30A shows a high-resolution TEM image of a cross section of the CAAC-OS which is observed from a direction substantially parallel to the sample surface. The high-resolution TEM image is obtained with a spherical aberration corrector function. The high-resolution TEM image obtained with a spherical aberration corrector function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be observed with, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

FIG. 30A shows pellets in which metal atoms are arranged in a layered manner. FIG. 30A proves that the size of a pellet is greater than or equal to 1 nm or greater than or equal to 3 nm. Therefore, the pellet can also be referred to as a nanocrystal (nc). Furthermore, the CAAC-OS can also be referred to as an oxide semiconductor including c-axis aligned nanocrystals (CANC). A pellet reflects unevenness of a formation surface or a top surface of the CAAC-OS, and is parallel to the formation surface or the top surface of the CAAC-OS.

FIGS. 30B and 30C show Cs-corrected high-resolution TEM images of a plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface. FIGS. 30D and 30E are images obtained through image processing of FIGS. 30B and 30C. The method of image processing is as follows. The images in FIGS. 30B and 30C are subjected to fast Fourier transform (FFT), so that FFT images are obtained. Then, mask processing is performed such that a range of from 2.8 nm−1 to 5.0 nm−1 from the origin in the obtained FFT images remains. After the mask processing, the FFT images are processed by inverse fast Fourier transform (IFFT) to obtain processed images. The images obtained in this manner are called FFT filtering images. The FFT filtering images are Cs-corrected high-resolution TEM images from which a periodic component is extracted, and show a lattice arrangement.

In FIG. 30D, a portion where a lattice arrangement is broken is denoted with a dashed line. A region surrounded by a dashed line is one pellet. The portion denoted with the dashed line is a junction of pellets. The dashed line draws a hexagon, which means that the pellet has a hexagonal shape. Note that the shape of the pellet is not always a regular hexagon but is a non-regular hexagon in many cases.

In FIG. 30E, a dotted line denotes a portion between a region where a lattice arrangement is well aligned and another region where a lattice arrangement is well aligned. A clear crystal grain boundary cannot be observed even in the vicinity of the dotted line. When a lattice point in the vicinity of the dotted line is regarded as a center and surrounding lattice points are joined, a distorted hexagon, pentagon, and/or heptagon can be formed, for example. That is, a lattice arrangement is distorted so that formation of a crystal grain boundary is inhibited. This is probably because the CAAC-OS can tolerate distortion owing to a low density of arrangement of oxygen atoms in the a-b plane direction, an interatomic bond distance changed by substitution of a metal element, and the like.

As described above, the CAAC-OS has c-axis alignment, its pellets (nanocrystals) are connected in an a-b plane direction, and the crystal structure has distortion. For this reason, the CAAC-OS can also be referred to as an oxide semiconductor including a c-axis-aligned a-b-plane-anchored (CAA) crystal.

The CAAC-OS is an oxide semiconductor with high crystallinity. Entry of impurities, formation of defects, or the like might decrease the crystallinity of an oxide semiconductor. This means that the CAAC-OS has small amounts of impurities and defects (e.g., oxygen vacancies).

Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element (specifically, silicon or the like) having higher strength of bonding to oxygen than a metal element included in an oxide semiconductor extracts oxygen from the oxide semiconductor, which results in disorder of the atomic arrangement and reduced crystallinity of the oxide semiconductor. A heavy metal such as iron or nickel, argon, carbon dioxide, or the like has a large atomic radius (or molecular radius), and thus disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.

<nc-OS>

Next, an nc-OS is described.

Analysis of an nc-OS by XRD is described. When the structure of an nc-OS is analyzed by an out-of-plane method, a peak indicating orientation does not appear. That is, a crystal of an nc-OS does not have orientation.

For example, when an electron beam with a probe diameter of 50 nm is incident on a 34-nm-thick region of thinned nc-OS including an InGaZnO4 crystal in a direction parallel to the formation surface, a ring-shaped diffraction pattern (a nanobeam electron diffraction pattern) shown in FIG. 31A is observed. FIG. 31B shows a diffraction pattern obtained when an electron beam with a probe diameter of 1 nm is incident on the same sample. As shown in FIG. 31B, a plurality of spots are observed in a ring-like region. In other words, ordering in an nc-OS is not observed with an electron beam with a probe diameter of 50 nm but is observed with an electron beam with a probe diameter of 1 nm.

Furthermore, an electron diffraction pattern in which spots are arranged in an approximately regular hexagonal shape is observed in some cases as shown in FIG. 31C when an electron beam having a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm. This means that an nc-OS has a well-ordered region, i.e., a crystal, in the range of less than 10 nm in thickness. Note that an electron diffraction pattern having regularity is not observed in some regions because crystals are aligned in various directions.

FIG. 31D shows a Cs-corrected high-resolution TEM image of a cross section of an nc-OS observed from the direction substantially parallel to the formation surface. In a high-resolution TEM image, an nc-OS has a region in which a crystal part is observed, such as the part indicated by additional lines in FIG. 31D, and a region in which a crystal part is not clearly observed. In most cases, the size of a crystal part included in the nc-OS is greater than or equal to 1 nm and less than or equal to 10 nm, in particular, greater than or equal to 1 nm and less than or equal to 3 nm. Note that an oxide semiconductor including a crystal part whose size is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor. In a high-resolution TEM image of the nc-OS, for example, a grain boundary is not clearly observed in some cases. Note that there is a possibility that the origin of the nanocrystal is the same as that of a pellet in a CAAC-OS. Therefore, a crystal part of the nc-OS may be referred to as a pellet in the following description.

As described above, in the nc-OS, a microscopic region (e.g., a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. There is no regularity of crystal orientation between different pellets in the nc-OS. Thus, the orientation of the whole film is not ordered. Accordingly, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor, depending on an analysis method.

Since there is no regularity of crystal orientation between the pellets (nanocrystals) as mentioned above, the nc-OS can also be referred to as an oxide semiconductor including random aligned nanocrystals (RANC) or an oxide semiconductor including non-aligned nanocrystals (NANC).

The nc-OS is an oxide semiconductor that has high regularity as compared to an amorphous oxide semiconductor. Therefore, the nc-OS is likely to have a lower density of defect states than an a-like OS and an amorphous oxide semiconductor. Note that there is no regularity of crystal orientation between different pellets in the nc-OS. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

<a-Like OS>

An a-like OS has a structure intermediate between those of the nc-OS and the amorphous oxide semiconductor.

FIGS. 32A and 32B are high-resolution cross-sectional TEM images of an a-like OS. FIG. 32A is the high-resolution cross-sectional TEM image of the a-like OS at the start of the electron irradiation. FIG. 32B is the high-resolution cross-sectional TEM image of a-like OS after the electron (e) irradiation at 4.3×108 e/nm2. FIGS. 32A and 32B show that stripe-like bright regions extending vertically are observed in the a-like OS from the start of the electron irradiation. It can be also found that the shape of the bright region changes after the electron irradiation. Note that the bright region is presumably a void or a low-density region.

The a-like OS has an unstable structure because it contains a void. To verify that an a-like OS has an unstable structure as compared to a CAAC-OS and an nc-OS, a change in structure caused by electron irradiation is described below.

An a-like OS, an nc-OS, and a CAAC-OS are prepared as samples. Each of the samples is an In—Ga—Zn oxide.

First, a high-resolution cross-sectional TEM image of each sample is obtained. The high-resolution cross-sectional TEM images show that all the samples have crystal parts.

It is known that a unit cell of an InGaZnO4 crystal has a structure in which nine layers including three In—O layers and six Ga—Zn—O layers are stacked in the c-axis direction. The distance between the adjacent layers is equivalent to the lattice spacing on the (009) plane (also referred to as d value). The value is calculated to be 0.29 nm from crystal structural analysis. Accordingly, a portion where the spacing between lattice fringes is greater than or equal to 0.28 nm and less than or equal to 0.30 nm is regarded as a crystal part of InGaZnO4 in the following description. Each of lattice fringes corresponds to the a-b plane of the InGaZnO4 crystal.

FIG. 33 shows change in the average size of crystal parts (at 22 points to 30 points) in each sample. Note that the crystal part size corresponds to the length of a lattice fringe. FIG. 33 indicates that the crystal part size in the a-like OS increases with an increase in the cumulative electron dose in obtaining TEM images, for example. As shown in FIG. 33, a crystal part of approximately 1.2 nm (also referred to as an initial nucleus) at the start of TEM observation grows to a size of approximately 1.9 nm at a cumulative electron (e) dose of 4.2×108 e/nm2. In contrast, the crystal part size in the nc-OS and the CAAC-OS shows little change from the start of electron irradiation to a cumulative electron dose of 4.2×108 e/nm2. As shown in FIG. 33, the crystal part sizes in an nc-OS and a CAAC-OS are approximately 1.3 nm and approximately 1.8 nm, respectively, regardless of the cumulative electron dose. For the electron beam irradiation and TEM observation, a Hitachi H-9000NAR transmission electron microscope was used. The conditions of electron beam irradiation were as follows: the accelerating voltage was 300 kV; the current density was 6.7×105 e/(nm2·s); and the diameter of irradiation region was 230 nm.

In this manner, growth of the crystal part in the a-like OS is sometimes induced by electron irradiation. In contrast, in the nc-OS and the CAAC-OS, growth of the crystal part is hardly induced by electron irradiation. Therefore, the a-like OS has an unstable structure as compared to the nc-OS and the CAAC-OS.

The a-like OS has a lower density than the nc-OS and the CAAC-OS because it contains a void. Specifically, the density of the a-like OS is higher than or equal to 78.6% and lower than 92.3% of the density of the single crystal oxide semiconductor having the same composition. The density of each of the nc-OS and the CAAC-OS is higher than or equal to 92.3% and lower than 100% of the density of the single crystal oxide semiconductor having the same composition. Note that it is difficult to deposit an oxide semiconductor having a density of lower than 78% of the density of the single crystal oxide semiconductor.

For example, in the case of an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of single crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g/cm3. Accordingly, in the case of the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of the a-like OS is higher than or equal to 5.0 g/cm3 and lower than 5.9 g/cm3. For example, in the case of the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of each of the nc-OS and the CAAC-OS is higher than or equal to 5.9 g/cm3 and lower than 6.3 g/cm3.

Note that in the case where an oxide semiconductor having a certain composition does not exist in a single crystal structure, single crystal oxide semiconductors with different compositions are combined at an adequate ratio, which makes it possible to calculate density equivalent to that of a single crystal oxide semiconductor with the desired composition. The density of a single crystal oxide semiconductor having the desired composition can be calculated using a weighted average according to the combination ratio of the single crystal oxide semiconductors with different compositions. Note that it is preferable to use as few kinds of single crystal oxide semiconductors as possible to calculate the density.

As described above, oxide semiconductors have various structures and various properties. Note that an oxide semiconductor may be a stacked layer film including two or more films of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.

Embodiment 3

In this embodiment, an example of a circuit including the transistor of one embodiment of the present invention is described with reference to the drawings.

<Cross-Sectional Structure>

FIG. 34A is a cross-sectional view of a semiconductor device of one embodiment of the present invention. In FIG. 34A, X1-X2 direction and Y1-Y2 direction represent a channel length direction and a channel width direction, respectively. The semiconductor device illustrated in FIG. 34A includes a transistor 2200 containing a first semiconductor material in a lower portion and a transistor 2100 containing a second semiconductor material in an upper portion. In FIG. 34A, an example is illustrated in which the transistor described in the above embodiment as an example is used as the transistor 2100 containing the second semiconductor material. A cross-sectional view of the transistors in the channel length direction is on the left side of a dashed-dotted line, and a cross-sectional view of the transistors in the channel width direction is on the right side of the dashed-dotted line.

Here, the first semiconductor material and the second semiconductor material are preferably materials having different band gaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (examples of such a semiconductor material include silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, and an organic semiconductor), and the second semiconductor material can be an oxide semiconductor. A transistor using a material other than an oxide semiconductor, such as single crystal silicon, can operate at a high speed easily. In contrast, a transistor using an oxide semiconductor and described in the above embodiment as an example can have a small subthreshold value (S value) and a minute structure. Furthermore, the transistor can operate at a high speed because of its high switching speed and has low leakage current because of its low off-state current.

The transistor 2200 may be either an n-channel transistor or a p-channel transistor, and an appropriate transistor may be used in accordance with a circuit. Furthermore, the specific structure of the semiconductor device, such as the material or the structure used for the semiconductor device, is not necessarily limited to those described here except for the use of the transistor of one embodiment of the present invention which uses an oxide semiconductor.

FIG. 34A illustrates a structure in which the transistor 2100 is provided over the transistor 2200 with an insulator 2201 and an insulator 2207 provided therebetween. A plurality of wirings 2202 are provided between the transistor 2200 and the transistor 2100. Furthermore, wirings and electrodes provided over and under the insulators are electrically connected to each other through a plurality of plugs 2203 embedded in the insulators. An insulator 2204 covering the transistor 2100 and a wiring 2205 over the insulator 2204 are provided.

The stack of the two kinds of transistors reduces the area occupied by the circuit, allowing a plurality of circuits to be highly integrated.

Here, in the case where a silicon-based semiconductor material is used for the transistor 2200 provided in a lower portion, hydrogen in an insulator provided in the vicinity of the semiconductor film of the transistor 2200 terminates dangling bonds of silicon; accordingly, the reliability of the transistor 2200 can be improved. Meanwhile, in the case where an oxide semiconductor is used for the transistor 2100 provided in an upper portion, hydrogen in an insulator provided in the vicinity of the semiconductor film of the transistor 2100 becomes a factor of generating carriers in the oxide semiconductor; thus, the reliability of the transistor 2100 might be decreased. Therefore, in the case where the transistor 2100 using an oxide semiconductor is provided over the transistor 2200 using a silicon-based semiconductor material, it is particularly effective that the insulator 2207 having a function of preventing diffusion of hydrogen is provided between the transistors 2100 and 2200. The insulator 2207 makes hydrogen remain in the lower portion, thereby improving the reliability of the transistor 2200. In addition, since the insulator 2207 suppresses diffusion of hydrogen from the lower portion to the upper portion, the reliability of the transistor 2100 also can be improved.

The insulator 2207 can be, for example, formed using aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or yttria-stabilized zirconia (YSZ).

Furthermore, a blocking film having a function of preventing diffusion of hydrogen is preferably formed over the transistor 2100 to cover the transistor 2100 including an oxide semiconductor film. For the blocking film, a material that is similar to that of the insulator 2207 can be used, and in particular, an aluminum oxide film is preferably used. The aluminum oxide film has a high shielding (blocking) effect of preventing transmission of both oxygen and impurities such as hydrogen and moisture. Thus, by using the aluminum oxide film as the blocking film covering the transistor 2100, release of oxygen from the oxide semiconductor film included in the transistor 2100 can be prevented and entry of water and hydrogen into the oxide semiconductor film can be prevented. Note that as the block film, the insulator 2204 having a stacked-layer structure may be used, or the block film may be provided under the insulator 2204.

Note that the transistor 2200 can be a transistor of various types without being limited to a planar type transistor. For example, the transistor 2200 can be a fin-type transistor, a tri-gate transistor, or the like. An example of a cross-sectional view in this case is shown in FIG. 34D. An insulator 2212 is provided over a semiconductor substrate 2211. The semiconductor substrate 2211 includes a projecting portion with a thin tip (also referred to as a fin). Note that an insulator may be provided over the projecting portion. The projecting portion does not necessarily have the thin tip; a projecting portion with a cuboid-like projecting portion and a projecting portion with a thick tip are permitted, for example. A gate insulator 2214 is provided over the projecting portion of the semiconductor substrate 2211, and a gate electrode 2213 is provided over the gate insulator 2214. Source and drain regions 2215 are formed in the semiconductor substrate 2211. Note that here is shown an example in which the semiconductor substrate 2211 has the projecting portion; however, the semiconductor device of one embodiment of the present invention is not limited thereto. For example, a semiconductor region having a projecting portion may be formed by processing an SOI substrate.

Circuit Configuration Example

In the above structure, electrodes of the transistor 2100 and the transistor 2200 can be connected as appropriate; thus, a variety of circuits can be formed. Examples of circuit configurations which can be achieved by using a semiconductor device of one embodiment of the present invention are shown below.

<CMOS Inverter Circuit>

A circuit diagram in FIG. 34B shows a configuration of a so-called CMOS inverter in which the p-channel transistor 2200 and the n-channel transistor 2100 are connected to each other in series and in which gates of them are connected to each other.

<CMOS Analog Switch>

A circuit diagram in FIG. 34C shows a configuration in which sources of the transistors 2100 and 2200 are connected to each other and drains of the transistors 2100 and 2200 are connected to each other. In FIG. 34A, X1-X2 direction represents a channel length direction, and Y1-Y2 direction represents a channel width direction. With such a configuration, the transistors can function as a so-called CMOS analog switch.

Memory Device Example

An example of a semiconductor device (memory device) which includes the transistor of one embodiment of the present invention, which can retain stored data even when not powered, and which has an unlimited number of write cycles is shown in FIGS. 35A to 35C.

The semiconductor device illustrated in FIG. 35A includes a transistor 3200 using a first semiconductor material, a transistor 3300 using a second semiconductor material, and a capacitor 3400. As the transistor 3300, the transistor described in Embodiment 1 can be used.

FIG. 35B is a cross-sectional view of the semiconductor device illustrated in FIG. 35A. The semiconductor device in the cross-sectional view has a structure in which the transistor 3300 is provided with a back gate; however, a structure without a back gate may be employed.

The transistor 3300 is a transistor in which a channel region is formed in a semiconductor including an oxide semiconductor. Since the off-state current of the transistor 3300 is low, stored data can be retained for a long period. In other words, power consumption can be sufficiently reduced because a semiconductor device (memory device) in which refresh operation is unnecessary or the frequency of refresh operation is extremely low can be provided.

In FIG. 35A, a first wiring 3001 is electrically connected to a source electrode of the transistor 3200. A second wiring 3002 is electrically connected to a drain electrode of the transistor 3200. A third wiring 3003 is electrically connected to one of a source electrode and a drain electrode of the transistor 3300. A fourth wiring 3004 is electrically connected to a gate electrode of the transistor 3300. A gate electrode of the transistor 3200 is electrically connected to the other of the source electrode and the drain electrode of the transistor 3300 and a first terminal of the capacitor 3400. The fifth wiring 3005 is electrically connected to a second terminal of the capacitor 3400. Although the capacitor 3400 is provided over the transistor 3300 in FIG. 35B, the capacitor 3400 may be provided between the transistor 3200 and the transistor 3300 (see FIG. 36 and FIG. 37).

The third wiring can be used as a first terminal of the capacitor 3400. Accordingly, an additional wiring layer is not necessarily provided for forming the capacitor 3400 and the third wiring can be formed over the transistor 3300, whereby the manufacturing process of the semiconductor device can be shortened (see FIG. 38).

The semiconductor device in FIG. 35A has a feature that the potential of the gate electrode of the transistor 3200 can be retained, and thus enables writing, retaining, and reading of data as follows.

Writing and holding of data are described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned on, so that the transistor 3300 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to the gate electrode of the transistor 3200 and the capacitor 3400. That is, a predetermined charge is supplied to the gate of the transistor 3200 (writing). Here, one of two kinds of charges providing different potential levels (hereinafter referred to as a low-level charge and a high-level charge) is supplied. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off, so that the transistor 3300 is turned off. Thus, the charge supplied to the gate of the transistor 3200 is retained (retaining).

Since the off-state current of the transistor 3300 is extremely low, the charge of the gate of the transistor 3200 is retained for a long time.

Next, reading of data is described. An appropriate potential (a reading potential) is supplied to the fifth wiring 3005 while a predetermined potential (a constant potential) is supplied to the first wiring 3001, whereby the potential of the second wiring 3002 varies depending on the amount of charge retained in the gate electrode of the transistor 3200. This is because in the case of using an n-channel transistor as the transistor 3200, an apparent threshold voltage Vth_H at the time when the high-level charge is given to the gate electrode of the transistor 3200 is lower than an apparent threshold voltage Vth_L at the time when the low-level charge is given to the gate electrode of the transistor 3200. Here, an apparent threshold voltage refers to the potential of the fifth wiring 3005 which is needed to turn on the transistor 3200. Thus, the potential of the fifth wiring 3005 is set to a potential V0 which is between Vth_H and Vth_L, whereby charge supplied to the gate of the transistor 3200 can be determined. For example, in the case where the high-level charge is supplied to the gate of the transistor 3200 in writing and the potential of the fifth wiring 3005 is V0 (>Vth_H), the transistor 3200 is turned on. In the case where the low-level charge is supplied to the gate of the transistor 3200 in writing, even when the potential of the fifth wiring 3005 is V0 (<Vth_L), the transistor 3200 remains off. Thus, the data retained in the gate electrode of the transistor 3200 can be read by determining the potential of the second wiring 3002.

Note that in the case where memory cells are arrayed to be used, it is necessary that only data of a desired memory cell be able to be read. For example, the fifth wiring 3005 of memory cells from which data is not read may be supplied with a potential at which the transistor 3200 is turned off regardless of the potential supplied to the gate electrode, that is, a potential lower than Vth_H, whereby only data of a desired memory cell can be read. Alternatively, the fifth wiring 3005 of the memory cells from which data is not read may be supplied with a potential at which the transistor 3200 is turned on regardless of the potential supplied to the gate electrode, that is, a potential higher than Vth_L, whereby only data of a desired memory cell can be read.

The semiconductor device illustrated in FIG. 35C is different from the semiconductor device illustrated in FIG. 35A in that the transistor 3200 is not provided. Also in this case, writing and retaining of data can be performed in a manner similar to the above.

Next, reading of data is described. When the transistor 3300 is turned on, the third wiring 3003 which is in a floating state and the capacitor 3400 are electrically connected to each other, and the charge is redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 is changed. The amount of change in the potential of the third wiring 3003 varies depending on the potential of a first terminal of the capacitor 3400 (or the charge accumulated in the capacitor 3400).

For example, the potential of the third wiring 3003 after the charge redistribution is (CB×VB0+C×V)/(CB+C), where V is the potential of the first terminal of the capacitor 3400, C is the capacitance of the capacitor 3400, CB is the capacitance component of the third wiring 3003, and VB0 is the potential of the third wiring 3003 before the charge redistribution. Thus, it can be found that, assuming that the memory cell is in either of two states in which the potential of the first terminal of the capacitor 3400 is V1 and V0 (V1>V0), the potential of the third wiring 3003 in the case of retaining the potential V1 (=(CB×VB0+C×V1)/(CB+C)) is higher than the potential of the third wiring 3003 in the case of retaining the potential V0 (=(CB×VB0+C×V0)/(CB+C)).

Then, by comparing the potential of the third wiring 3003 with a predetermined potential, data can be read.

In this case, a transistor including the first semiconductor material may be used for a driver circuit for driving a memory cell, and a transistor including the second semiconductor material may be stacked over the driver circuit as the transistor 3300.

When including a transistor in which a channel formation region is formed using an oxide semiconductor and which has an extremely small off-state current, the semiconductor device described in this embodiment can retain stored data for an extremely long time. In other words, refresh operation becomes unnecessary or the frequency of the refresh operation can be extremely low, which leads to a sufficient reduction in power consumption. Moreover, stored data can be retained for a long time even when power is not supplied (note that a potential is preferably fixed).

Furthermore, in the semiconductor device described in this embodiment, high voltage is not needed for writing data and there is no problem of deterioration of elements. Unlike in a conventional nonvolatile memory, for example, it is not necessary to inject and extract electrons into and from a floating gate; thus, a problem such as deterioration of a gate insulating layer is not caused. That is, the semiconductor device according to one embodiment of the present invention does not have a limit on the number of rewriting, which has been a problem of a conventional nonvolatile memory, and thus has significantly improved reliability. Furthermore, data is written depending on the state of the transistor (on or off), whereby high-speed operation can be easily achieved.

With the use of the semiconductor device described in this embodiment, a memory device with low power consumption and high capacity (e.g., 1 terabit or more) can be fabricated.

<Imaging Device>

An imaging device of one embodiment of the present invention is described below.

FIG. 39A is a plan view illustrating an example of an imaging device 200 of one embodiment of the present invention. The imaging device 200 includes a pixel portion 210 and peripheral circuits for driving the pixel portion 210 (a peripheral circuit 260, a peripheral circuit 270, a peripheral circuit 280, and a peripheral circuit 290). The pixel portion 210 includes a plurality of pixels 211 arranged in a matrix with p rows and q columns (p and q are each an integer of 2 or more). The peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 are each connected to the plurality of pixels 211, and a signal for driving the plurality of pixels 211 is supplied. In this specification and the like, in some cases, a “peripheral circuit” or a “driver circuit” indicate all of the peripheral circuits 260, 270, 280, and 290. For example, the peripheral circuit 260 can be regarded as part of the peripheral circuit.

The peripheral circuit includes at least one of a logic circuit, a switch, a buffer, an amplifier circuit, and a converter circuit. The peripheral circuit may be formed over a substrate where the pixel portion 210 is formed. A semiconductor device such as an IC chip may be used as part or the whole of the peripheral circuit. Note that as the peripheral circuit, one or more of the peripheral circuits 260, 270, 280, and 290 may be omitted.

As illustrated in FIG. 39B, the pixels 211 may be provided to be inclined in the pixel portion 210 included in the imaging device 200. When the pixels 211 are obliquely arranged, the distance between pixels (pitch) can be shortened in the row direction and the column direction. Accordingly, the quality of an image taken with the imaging device 200 can be improved.

<Configuration Example 1 of Pixel>

The pixel 211 included in the imaging device 200 is formed with a plurality of subpixels 212, and each subpixel 212 is combined with a filter (color filter) which transmits light in a specific wavelength band, whereby data for achieving color image display can be obtained.

FIG. 40A is a plan view showing an example of the pixel 211 with which a color image is obtained. The pixel 211 illustrated in FIG. 40A includes a subpixel 212 provided with a color filter that transmits light in a red (R) wavelength band (also referred to as a subpixel 212R), a subpixel 212 provided with a color filter that transmits light in a green (G) wavelength band (also referred to as a subpixel 212G), and a subpixel 212 provided with a color filter that transmits light in a blue (B) wavelength band (also referred to as a subpixel 212B). The subpixel 212 can function as a photosensor.

The subpixel 212 (the subpixel 212R, the subpixel 212G, and the subpixel 212B) is electrically connected to a wiring 231, a wiring 247, a wiring 248, a wiring 249, and a wiring 250. In addition, the subpixel 212R, the subpixel 212G, and the subpixel 212B are connected to respective wirings 253 which are independently provided. In this specification and the like, for example, the wiring 248 and the wiring 249 that are connected to the pixel 211 in the n-th row are referred to as a wiring 248[n] and a wiring 249[n]. For example, the wiring 253 connected to the pixel 211 in the m-th column is referred to as a wiring 253[m]. Note that in FIG. 40A, the wirings 253 connected to the subpixel 212R, the subpixel 212G, and the subpixel 212B in the pixel 211 in the m-th column are referred to as a wiring 253[m]R, a wiring 253[m]G, and a wiring 253[m]B. The subpixels 212 are electrically connected to the peripheral circuit through the above wirings.

The imaging device 200 has a structure in which the subpixel 212 is electrically connected to the subpixel 212 in an adjacent pixel 211 which is provided with a color filter transmitting light in the same wavelength band as the subpixel 212, via a switch. FIG. 40B shows a connection example of the subpixels 212: the subpixel 212 in the pixel 211 arranged in the n-th (n is an integer greater than or equal to 1 and less than or equal to p) row and the m-th (m is an integer greater than or equal to 1 and less than or equal to q) column and the subpixel 212 in the adjacent pixel 211 arranged in an (n+1)-th row and the m-th column. In FIG. 40B, the subpixel 212R arranged in the n-th row and the m-th column and the subpixel 212R arranged in the (n+1)-th row and the m-th column are connected to each other via a switch 201. The subpixel 212G arranged in the n-th row and the m-th column and the subpixel 212G arranged in the (n+1)-th row and the m-th column are connected to each other via a switch 202. The subpixel 212B arranged in the n-th row and the m-th column and the subpixel 212B arranged in the (n+1)-th row and the m-th column are connected to each other via a switch 203.

The color filter used in the subpixel 212 is not limited to red (R), green (G), and blue (B) color filters, and color filters that transmit light of cyan (C), yellow (Y), and magenta (M) may be used. By provision of the subpixels 212 that sense light in three different wavelength bands in one pixel 211, a full-color image can be obtained.

The pixel 211 including the subpixel 212 provided with a color filter transmitting yellow (Y) light may be provided, in addition to the subpixels 212 provided with the color filters transmitting red (R), green (G), and blue (B) light. The pixel 211 including the subpixel 212 provided with a color filter transmitting blue (B) light may be provided, in addition to the subpixels 212 provided with the color filters transmitting cyan (C), yellow (Y), and magenta (M) light. When the subpixels 212 sensing light in four different wavelength bands are provided in one pixel 211, the reproducibility of colors of an obtained image can be increased.

For example, in FIG. 40A, in regard to the subpixel 212R sensing light in a red wavelength band, the subpixel 212G sensing light in a green wavelength band, and the subpixel 212B sensing light in a blue wavelength band, the pixel number ratio (or the light receiving area ratio) thereof is not necessarily 1:1:1. For example, the Bayer arrangement in which the pixel number ratio (the light receiving area ratio) is set at red:green:blue=1:2:1 may be employed. Alternatively, the pixel number ratio (the light receiving area ratio) of red and green to blue may be 1:6:1.

Although the number of subpixels 212 provided in the pixel 211 may be one, two or more subpixels are preferably provided. For example, when two or more subpixels 212 sensing light in the same wavelength band are provided, the redundancy is increased, and the reliability of the imaging device 200 can be increased.

When an infrared (IR) filter that transmits infrared light and absorbs or reflects visible light is used as the filter, the imaging device 200 that senses infrared light can be achieved.

Furthermore, when a neutral density (ND) filter (dark filter) is used, output saturation which occurs when a large amount of light enters a photoelectric conversion element (light-receiving element) can be prevented. With a combination of ND filters with different dimming capabilities, the dynamic range of the imaging device can be increased.

Besides the above-described filter, the pixel 211 may be provided with a lens. An arrangement example of the pixel 211, a filter 254, and a lens 255 is described with cross-sectional views in FIGS. 41A and 41B. With the lens 255, the photoelectric conversion element can receive incident light efficiently. Specifically, as illustrated in FIG. 41A, light 256 enters a photoelectric conversion element 220 through the lens 255, the filter 254 (a filter 254R, a filter 254G, and a filter 254B), a pixel circuit 230, and the like which are provided in the pixel 211.

As indicated by a region surrounded with dashed dotted lines, however, part of the light 256 indicated by arrows might be blocked by some wirings 257. Thus, a preferable structure is such that the lens 255 and the filter 254 are provided on the photoelectric conversion element 220 side as illustrated in FIG. 41B, whereby the photoelectric conversion element 220 can efficiently receive the light 256. When the light 256 enters the photoelectric conversion element 220 from the photoelectric conversion element 220 side, the imaging device 200 with high sensitivity can be provided.

As the photoelectric conversion element 220 illustrated in FIGS. 41A and 41B, a photoelectric conversion element in which a p-n junction or a p-i-n junction is formed may be used.

The photoelectric conversion element 220 may be formed using a substance that has a function of absorbing a radiation and generating electric charges. Examples of the substance that has a function of absorbing a radiation and generating electric charges include selenium, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, and cadmium zinc alloy.

For example, when selenium is used for the photoelectric conversion element 220, the photoelectric conversion element 220 can have a light absorption coefficient in a wide wavelength band, such as visible light, ultraviolet light, infrared light, X-rays, and gamma rays.

One pixel 211 included in the imaging device 200 may include the subpixel 212 with a first filter in addition to the subpixel 212 illustrated in FIGS. 40A and 40B.

<Configuration Example 2 of Pixel>

An example of a pixel including a transistor including silicon and a transistor including an oxide semiconductor is described below.

FIGS. 42A and 42B are each a cross-sectional view of an element included in an imaging device.

The imaging device illustrated in FIG. 42A includes a transistor 351 including silicon on a silicon substrate 300, a transistor 353 which includes an oxide semiconductor and is stacked over the transistor 351, and a photodiode 360 provided in a silicon substrate 300 and including an anode 361 and a cathode 362. The transistors and the photodiode 360 are electrically connected to various plugs 370 and wirings 371, 372, and 373. In addition, an anode 361 of the photodiode 360 is electrically connected to the plug 370 through a low-resistance region 363.

The imaging device includes a layer310 including the transistor 351 and the photodiode 360 provided on the silicon substrate 300, a layer 320 which is in contact with the layer 310 and includes the wirings 371, a layer 330 which is in contact with the layer 320 and includes the transistor 353 and an insulating layer 380, and a layer 340 which is in contact with the layer 330 and includes the wiring 372 and the wiring 373.

In the example of the cross-sectional view in FIG. 42A, a light-receiving surface of the photodiode 360 is provided on the side opposite to a surface of the silicon substrate 300 where the transistor 351 is formed. With this structure, a light path can be secured without an influence of the transistors and the wirings. Thus, a pixel with a high aperture ratio can be formed. Note that the light-receiving surface of the photodiode 360 can be the same as the surface where the transistor 351 is formed.

In the case where a pixel is formed with use of only transistors including an oxide semiconductor, the layer 310 may include the transistor including an oxide semiconductor. Alternatively, the layer 310 may be omitted, and the pixel may include only transistors including an oxide semiconductor.

In the cross-sectional view in FIG. 42A, the photodiode 360 in the layer 310 and the transistor 353 in the layer 330 can be formed so as to overlap with each other. Thus, the degree of integration of pixels can be increased. In other words, the resolution of the imaging device can be increased.

An imaging device illustrated in FIG. 42B includes a photodiode 365 in the layer 340 and over the transistor. In FIG. 42B, the layer 310 includes the transistor 351 using silicon, the layer 320 includes the wiring 371, the layer 330 includes the transistor 353 using an oxide semiconductor and the insulating layer 380, and the layer 340 includes the photodiode 365. The photodiode 365 is electrically connected to the wiring 373 and a wiring 374 through the plug 370.

The element structure shown in FIG. 42B can increase the aperture ratio.

Alternatively, a PIN diode element formed using an amorphous silicon film, a microcrystalline silicon film, or the like may be used as the photodiode 365. In the photodiode 365, an n-type semiconductor 368, an i-type semiconductor 367, and a p-type semiconductor 366 are stacked in this order. The i-type semiconductor 367 is preferably formed using amorphous silicon. The p-type semiconductor 366 and the n-type semiconductor 368 can each be formed using amorphous silicon, microcrystalline silicon, or the like which includes a dopant imparting the corresponding conductivity type. The photodiode 365 in which a photoelectric conversion layer is formed using amorphous silicon has high sensitivity in a visible light wavelength region, and therefore can easily sense weak visible light.

Note that this embodiment can be combined with any of the other embodiments in this specification as appropriate.

Embodiment 4

In this embodiment, circuit configuration examples to which the transistors including oxide semiconductor layers (OS transistors) described in the above embodiment can be applied will be described with reference to FIGS. 43A to 43C, FIGS. 44A to 44C, FIGS. 45A and 45B, and FIGS. 46A and 46B.

FIG. 43A is a circuit diagram of an inverter applicable to a memory, an FPGA, a CPU, or the like. An inverter 2800 outputs a signal whose logic is inverted from the logic of a signal supplied to an input terminal IN to an output terminal OUT. The inverter 2800 includes a plurality of OS transistors. A signal SBG can switch electrical characteristics of the OS transistors.

FIG. 43B is a circuit diagram illustrating an example of the inverter 2800. The inverter 2800 includes OS transistors 2810 and 2820. The inverter 2800 can be formed using n-channel transistors and can have a circuit configuration in which all the transistors have the same conductivity. With the circuit configuration in which all the transistors have the same conductivity, the inverter can be formed at lower cost than an inverter formed using a complementary metal oxide semiconductor (i.e., a CMOS inverter).

Note that the inverter 2800 including the OS transistors can be provided over a CMOS circuit including Si transistors. Since the inverter 2800 can be provided so as to overlap with the CMOS circuit, no additional area is required for the inverter 2800, and thus, an increase in the circuit area can be suppressed.

Each of the OS transistors 2810 and 2820 includes a first gate functioning as a front gate, a second gate functioning as a back gate, a first terminal functioning as one of a source and a drain, and a second terminal functioning as the other of the source and the drain.

The first gate of the OS transistor 2810 is connected to its second terminal. The second gate of the OS transistor 2810 is connected to a wiring that transmits the signal SBG. The first terminal of the OS transistor 2810 is connected to a wiring that supplies a voltage VDD. The second terminal of the OS transistor 2810 is connected to the output terminal OUT.

The first gate of the OS transistor 2820 is connected to the input terminal IN. The second gate of the OS transistor 2820 is connected to the input terminal IN. The first terminal of the OS transistor 2820 is connected to the output terminal OUT. The second terminal of the OS transistor 2820 is connected to a wiring that supplies a voltage VSS.

FIG. 43C is a timing chart illustrating the operation of the inverter 2800. The timing chart in FIG. 43C illustrates changes of a signal waveform of the input terminal IN, a signal waveform of the output terminal OUT, a signal waveform of the signal SBG, and the threshold voltage of the OS transistor 2810.

The signal SBG supplied to the second gate of the OS transistor 2810 can control the threshold voltage of the OS transistor 2810.

The signal SBG includes a voltage VBG_A for shifting the threshold voltage in the negative direction and a voltage VBG_B for shifting the threshold voltage in the positive direction. The threshold voltage of the OS transistor 2810 can be shifted in the negative direction to be a threshold voltage VTH_A when the voltage VBG_A is applied to the second gate. The threshold voltage of the OS transistor 2810 can be shifted in the positive direction to be a threshold voltage VTH_B when the voltage VBG_B is applied to the second gate.

To visualize the above description, FIG. 44A shows a Vg-Id curve, which is one of the electrical characteristics of a transistor.

When a high voltage such as the voltage VBG_A is applied to the second gate, the electrical characteristics of the OS transistor 2810 can be shifted to match a curve shown by a dashed line 2840 in FIG. 44A. When a low voltage such as the voltage VBG_B is applied to the second gate, the electrical characteristics of the OS transistor 2810 can be shifted to match a curve shown by a solid line 2841 in FIG. 44A. As shown in FIG. 44A, switching the signal SBG between the voltage VBG_A and the voltage VBG_B enables the threshold voltage of the OS transistor 2810 to be shifted in the positive direction or the negative direction.

The shift of the threshold voltage of the transistor 2810 in the positive direction toward the threshold voltage VTH_B can make current less likely to flow in the OS transistor 2810. FIG. 44B visualizes the state. As illustrated in FIG. 44B, a current IB that flows in the OS transistor 2810 can be extremely low. Thus, when a signal supplied to the input terminal IN is at a high level and the OS transistor 2820 is on (ON), the voltage of the output terminal OUT can drop sharply.

Since a state in which current is less likely to flow in the OS transistor 2810 as illustrated in FIG. 44B can be obtained, a signal waveform 2831 of the output terminal OUT in the timing chart in FIG. 43C can be made steep. Shoot-through current between the wiring that supplies the voltage VDD and the wiring that supplies the voltage VSS can be low, leading to low-power operation.

The shift of the threshold voltage of the OS transistor 2810 in the negative direction toward the threshold voltage VTH_A can make current flow easily in the OS transistor 2810. FIG. 44C visualizes the state. As illustrated in FIG. 44C, a current IA flowing in the OS transistor 2810 at this time can be higher than at least the current IB. Thus, when a signal supplied to the input terminal IN is at a low level and the OS transistor 2820 is off (OFF), the voltage of the output terminal OUT can be increased sharply.

Since a state in which current is likely to flow in the OS transistor 2810 as illustrated in FIG. 44C can be obtained, a signal waveform 2832 of the output terminal OUT in the timing chart in FIG. 43C can be made steep. Shoot-through current between the wiring that supplies the voltage VDD and the wiring that supplies the voltage VSS can be low, leading to low-power operation.

Note that the threshold voltage of the OS transistor 2810 is preferably controlled by the signal SBG before the state of the OS transistor 2820 is switched, i.e., before Time T1 or T2. For example, as in FIG. 43C, it is preferable that the threshold voltage of the OS transistor 2810 be switched from the threshold voltage VTH_A to the threshold voltage VTH_B before Time T1 at which the level of the signal supplied to the input terminal IN is switched to a high level. Moreover, as in FIG. 43C, it is preferable that the threshold voltage of the OS transistor 2810 be switched from the threshold voltage VTH_B to the threshold voltage VTH_A before Time T2 at which the level of the signal supplied to the input terminal IN is switched to a low level.

Although the timing chart in FIG. 43C illustrates the configuration in which the level of the signal SBG is switched in accordance with the signal supplied to the input terminal IN, a different configuration may be employed in which voltage for controlling the threshold voltage is held by the second gate of the OS transistor 2810 in a floating state, for example. FIG. 45A illustrates an example of such a circuit configuration.

The circuit configuration in FIG. 45A is the same as that in FIG. 43B, except that an OS transistor 2850 is added. A first terminal of the OS transistor 2850 is connected to the second gate of the OS transistor 2810. A second terminal of the OS transistor 2850 is connected to a wiring that supplies the voltage VBG_B (or the voltage VBG_A). A first gate of the OS transistor 2850 is connected to a wiring that supplies a signal SF. A second gate of the OS transistor 2850 is connected to the wiring that supplies the voltage VBG_B (or the voltage VBG_A).

The operation with the circuit configuration in FIG. 45A is described with reference to the timing chart in FIG. 45B.

The voltage for controlling the threshold voltage of the OS transistor 2810 is supplied to the second gate of the OS transistor 2810 before Time T3 at which the level of the signal supplied to the input terminal IN is switched to a high level. The signal SF is set to a high level and the OS transistor 2850 is turned on, so that the voltage VBG_B for controlling the threshold voltage of the OS transistor 2810 is supplied to a node NBG.

The OS transistor 2850 is turned off after the voltage of the node NBG becomes VBG_B. Since the off-state current of the OS transistor 2850 is extremely low, the voltage VBG_B held by the node NBG can be retained while the OS transistor 2850 remains off. Therefore, the number of times the voltage VBG_B is supplied to the second gate of the OS transistor 2850 can be reduced and accordingly, the power consumption for rewriting the voltage VBG_B can be reduced.

Although FIG. 43B and FIG. 45A each illustrate the case where the voltage is supplied to the second gate of the OS transistor 2810 by control from the outside, a different configuration may be employed in which voltage for controlling the threshold voltage of the OS transistor 2810 is generated on the basis of the signal supplied to the input terminal IN and supplied to the second gate of the OS transistor 2810, for example. FIG. 46A illustrates an example of such a circuit configuration.

The circuit configuration in FIG. 46A is the same as that in FIG. 43B, except that a CMOS inverter 2860 is provided between the input terminal IN and the second gate of the OS transistor 2810. An input terminal of the CMOS inverter 2860 is connected to the input terminal IN. An output terminal of the CMOS inverter 2860 is connected to the second gate of the OS transistor 2810.

The operation with the circuit configuration in FIG. 46A is described with reference to a timing chart in FIG. 46B. The timing chart in FIG. 46B illustrates changes of a signal waveform of the input terminal IN, a signal waveform of the output terminal OUT, an output waveform IN_B of the CMOS inverter 2860, and a threshold voltage of the OS transistor 2810.

The output waveform IN_B which corresponds to a signal whose logic is inverted from the logic of the signal supplied to the input terminal IN can be used as a signal that controls the threshold voltage of the OS transistor 2810. Therefore, the threshold voltage of the OS transistor 2810 can be controlled as described with reference to FIGS. 44A to 44C. For example, the signal supplied to the input terminal IN is at a high level and the OS transistor 2820 is turned on at Time T4 in FIG. 46B. At this time, the output waveform IN_B is at a low level. Accordingly, current can be made less likely to flow in the OS transistor 2810; thus, the voltage of the output terminal OUT can be sharply decreased.

Moreover, the signal supplied to the input terminal IN is at a low level and the OS transistor 2820 is turned off at Time T5 in FIG. 46B. At this time, the output waveform IN_B is at a high level. Accordingly, current can easily flow in the OS transistor 2810; thus, a rise in the voltage of the output terminal OUT can be made steep.

As described above, in the configuration of the inverter including the OS transistor in this embodiment, the voltage of the back gate of the OS transistor is switched in accordance with the logic of the signal supplied to the input terminal IN. In such a configuration, the threshold voltage of the OS transistor can be controlled. The control of the threshold voltage of the OS transistor by the signal supplied to the input terminal IN can make a change in the voltage of the output terminal OUT steep. Moreover, shoot-through current between the wirings that supply power supply voltages can be reduced. Thus, power consumption can be reduced.

Embodiment 5

In this embodiment, examples of a semiconductor device which includes a plurality of circuits including OS transistors and described in the above embodiment are described with reference to FIGS. 47A to 47E, FIGS. 48A and 48B, FIGS. 49A and 49B, and FIGS. 50A to 50C.

FIG. 47A is a block diagram of a semiconductor device 900. The semiconductor device 900 includes a power supply circuit 901, a circuit 902, a voltage generation circuit 903, a circuit 904, a voltage generation circuit 905, and a circuit 906.

The power supply circuit 901 is a circuit that generates a voltage VORG used as a reference. The voltage VORG is not necessarily one voltage and can be a plurality of voltages. The voltage VORG can be generated on the basis of a voltage V0 supplied from the outside of the semiconductor device 900. The semiconductor device 900 can generate the voltage VORG on the basis of one power supply voltage supplied from the outside. Thus, the semiconductor device 900 can operate without supply of a plurality of power supply voltages from the outside.

The circuits 902, 904, and 906 operate with different power supply voltages. For example, the power supply voltage of the circuit 902 is a voltage based on the voltage VORG and the voltage VSS (VORG>VSS), the power supply voltage of the circuit 904 is a voltage based on a voltage VPOG and the voltage VSS (VPOG>VORG), and the power supply voltages of the circuit 906 are voltages based on the voltage VORG, the voltage VSS, and a voltage VNEG (VORG>VSS>VNEG). When the voltage VSS is set to a ground potential (GND), the kinds of voltages generated by the power supply circuit 901 can be reduced.

The voltage generation circuit 903 is a circuit that generates the voltage VPOG. The voltage generation circuit 903 can generate the voltage VPOG on the basis of the voltage VORG supplied from the power supply circuit 901. Thus, the semiconductor device 900 including the circuit 904 can operate on the basis of one power supply voltage supplied from the outside.

The voltage generation circuit 905 is a circuit that generates the voltage VNEG. The voltage generation circuit 905 can generate the voltage VNEG on the basis of the voltage VORG supplied from the power supply circuit 901. Thus, the semiconductor device 900 including the circuit 906 can operate on the basis of one power supply voltage supplied from the outside.

FIG. 47B illustrates an example of the circuit 904 that operates with the voltage VPOG and FIG. 47C illustrates an example of a waveform of a signal for operating the circuit 904.

FIG. 47B illustrates a transistor 911. A signal supplied to a gate of the transistor 911 is generated on the basis of, for example, the voltage VPOG and the voltage VSS. The signal is generated on the basis of the voltage VPOG to turn on the transistor 911 and on the basis of the voltage VSS to turn off the transistor 911. As illustrated in FIG. 47C, the voltage VPOG is higher than the voltage VORG. Thus, a source (S) and a drain (D) of the transistor 911 can be electrically connected to each other without fail. As a result, the frequency of malfunction of the circuit 904 can be reduced.

FIG. 47D illustrates an example of the circuit 906 that operates with the voltage VNEG and FIG. 47E illustrates an example of a waveform of a signal for operating the circuit 906.

FIG. 47D illustrates a transistor 912 having a back gate. A signal supplied to a gate of the transistor 912 is generated on the basis of, for example, the voltage VORG and the voltage VSS. The signal is generated on the basis of the voltage VORG to turn on the transistor 912 and on the basis of the voltage VSS to turn off the transistor 912. A signal supplied to the back gate of the transistor 912 is generated on the basis of the voltage VNEG. As illustrated in FIG. 47E, the voltage VNEG is lower than the voltage VSS (GND). Thus, the threshold voltage of the transistor 912 can be controlled to shift in the positive direction. Thus, the transistor 912 can be turned off without fail and a current flowing between a source (S) and a drain (D) can be reduced. As a result, the frequency of malfunction of the circuit 906 can be reduced and power consumption thereof can be reduced.

The voltage VNEG may be directly supplied to the back gate of the transistor 912. Alternatively, a signal supplied to the gate of the transistor 912 may be generated on the basis of the voltage VORG and the voltage VNEG and the generated signal may also be supplied to the back gate of the transistor 912.

FIGS. 48A and 48B illustrate a modification example of FIGS. 47D and 47E.

In a circuit diagram illustrated in FIG. 48A, a transistor 922 whose on/off state can be controlled by a control circuit 921 is provided between the voltage generation circuit 905 and the circuit 906. The transistor 922 is an n-channel OS transistor. The control signal SBG output from the control circuit 921 is a signal for controlling the on/off state of the transistor 922. Transistors 912A and 912B included in the circuit 906 are OS transistors like the transistor 922.

A timing chart in FIG. 48B shows changes in a potential of the control signal SBG and a potential of a node NBG. The potential of the node NBG indicates the states of potentials of back gates of the transistors 912A and 912B. When the control signal SBG is at a high level, the transistor 922 is turned on and the voltage of the node NBG becomes the voltage VNEG. Then, when the control signal SBG is at a low level, the node NBG is brought into an electrically floating state. Since the transistor 922 is an OS transistor, its off-state current is small. Accordingly, even when the node NBG is in an electrically floating state, the voltage VNEG which has been supplied can be held.

FIG. 49A illustrates an example of a circuit configuration applicable to the above-described voltage generation circuit 903. The voltage generation circuit 903 illustrated in FIG. 49A is a five-stage charge pump including diodes D1 to D5, capacitors C1 to C5, and an inverter INV. A clock signal CLK is supplied to the capacitors C1 to C4 directly or through the inverter INV. When a power supply voltage of the inverter INV is a voltage based on the voltage VORG and the voltage VSS, the voltage VPOG can be obtained by increasing the voltage VORG by a voltage five times a potential difference between the voltage VORG and the voltage VSS. Note that the forward voltage of the diodes D1 to D5 is 0 V. The number of stages of the charge pump can be changed to obtain a desired voltage VPOG.

FIG. 49B illustrates an example of a circuit configuration applicable to the above-described voltage generation circuit 905. The voltage generation circuit 905 illustrated in FIG. 49B is a four-stage charge pump including the diodes D1 to D5, the capacitors C1 to C5, and the inverter INV. The clock signal CLK is supplied to the capacitors C1 to C4 directly or through the inverter INV. When a power supply voltage of the inverter INV is a voltage applied on the basis of the voltage VORG and the voltage VSS, the voltage VNEG can be obtained by decreasing the ground voltage, i.e., the voltage VSS by a voltage four times the potential difference between the voltage VORG and the voltage VSS with the application of the clock signal CLK. Note that the forward voltage of the diodes D1 to D5 is 0 V. The number of stages of the charge pump can be changed to obtain a desired voltage VNEG.

The circuit configuration of the voltage generation circuit 903 is not limited to the configuration in the circuit diagram illustrated in FIG. 49A. Modification examples of the voltage generation circuit 903 are illustrated in FIGS. 50A to 50C. Note that further modification examples of the voltage generation circuit 905 can be realized by changing voltages supplied to wirings or arrangement of elements in voltage generation circuits 903A to 903C illustrated in FIGS. 50A to 50C

The voltage generation circuit 903A illustrated in FIG. 50A includes transistors M1 to M10, capacitors C11 to C14, and an inverter INV1. The clock signal CLK is supplied to gates of the transistors M1 to M10 directly or through the inverter INV1. By application of the clock signal CLK, the voltage VPOG, which has been increased to a positive voltage having a positively quadrupled value of the voltage VORG, can be obtained. The number of stages can be changed to obtain a desired voltage VPOG. In the voltage generation circuit 903A in FIG. 50A, the off-state current of each of the transistors M1 to M10 can be small when the transistors M1 to M10 are OS transistors, and the leakage of charge held in the capacitors C11 to C14 can be reduced. Accordingly, the voltage VORG can be efficiently increased to the voltage VPOG.

The voltage generation circuit 903B illustrated in FIG. 50B includes transistors M11 to M14, capacitors C15 and C16, and an inverter INV2. The clock signal CLK is supplied to gates of the transistors M11 to M14 directly or through the inverter INV2. By application of the clock signal CLK, the voltage VPOG, which has been increased to a positive voltage having a positively doubled value of the voltage VORG, can be obtained. In the voltage generation circuit 903B in FIG. 50B, off-state current of each of the transistors M11 to M14 can be small when the transistors M11 to M14 are OS transistors, and leakage of charge held in the capacitors C15 and C16 can be suppressed. Accordingly, the voltage VORG can be efficiently increased to the voltage VPOG.

A voltage generation circuit 903C illustrated in FIG. 50C includes an inductor I1, a transistor M15, a diode D6, and a capacitor C17. The on/off state of the transistor M15 is controlled by a control signal EN. Owing to the control signal EN, the voltage VPOG increased from the voltage VORG can be obtained. Since the voltage generation circuit 903C in FIG. 50C increases the voltage using the inductor I1, the voltage can be efficiently increased.

As described above, in any of the structures of this embodiment, a voltage required for circuits included in a semiconductor device can be internally generated. Thus, in the semiconductor device, the number of power supply voltages supplied from the outside can be reduced.

Embodiment 6

<RF Tag>

In this embodiment, an RF tag that includes the transistor described in the above embodiment or the memory device described in the above embodiment will be described with reference to FIG. 51.

The RF tag of this embodiment includes a memory circuit, stores necessary data in the memory circuit, and transmits and receives data to/from the outside by using a contactless means, for example, wireless communication. With these features, the RF tag can be used for an individual authentication system in which an object or the like is recognized by reading the individual information, for example. Note that the RF tag is required to have extremely high reliability in order to be used for this purpose.

A configuration of the RF tag is described with reference to FIG. 51. FIG. 51 is a block diagram illustrating a configuration example of an RF tag.

As shown in FIG. 51, an RF tag 800 includes an antenna 804 that receives a radio signal 803 that is transmitted from an antenna 802 connected to a communication device 801 (also referred to as an interrogator, a reader/writer, or the like). The RF tag 800 includes a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. A transistor having a rectifying function included in the demodulation circuit 807 may be formed using a material which enables a reverse current to be low enough, for example, an oxide semiconductor. This can suppress the phenomenon of a rectifying function becoming weaker due to generation of a reverse current and prevent saturation of the output from the demodulation circuit. In other words, the input to the demodulation circuit and the output from the demodulation circuit can have a relation closer to a linear relation. Note that data transmission methods are roughly classified into the following three methods: an electromagnetic coupling method in which a pair of coils is provided so as to face each other and communicates with each other by mutual induction, an electromagnetic induction method in which communication is performed using an induction field, and a radio wave method in which communication is performed using a radio wave. Any of these methods can be used in the RF tag 800 described in this embodiment.

Next, the structure of each circuit is described. The antenna 804 exchanges the radio signal 803 with the antenna 802 which is connected to the communication device 801. The rectifier circuit 805 generates an input potential by rectification, for example, half-wave voltage doubler rectification of an input alternating signal generated by reception of a radio signal at the antenna 804 and smoothing of the rectified signal with a capacitor provided in a later stage. Note that a limiter circuit may be provided on an input side or an output side of the rectifier circuit 805. The limiter circuit controls electric power so that electric power which is higher than or equal to certain electric power is not input to a circuit in a later stage if the amplitude of the input alternating signal is high and an internal generation voltage is high.

The constant voltage circuit 806 generates a stable power supply voltage from an input potential and supplies it to each circuit. Note that the constant voltage circuit 806 may include a reset signal generation circuit. The reset signal generation circuit is a circuit which generates a reset signal of the logic circuit 809 by utilizing rise of the stable power supply voltage.

The demodulation circuit 807 demodulates the input alternating signal by envelope detection and generates the demodulated signal. Further, the modulation circuit 808 performs modulation in accordance with data to be output from the antenna 804.

The logic circuit 809 analyzes and processes the demodulated signal. The memory circuit 810 holds the input data and includes a row decoder, a column decoder, a memory region, and the like. Further, the ROM 811 stores an identification number (ID) or the like and outputs it in accordance with processing.

Note that the decision whether each circuit described above is provided or not can be made as appropriate as needed.

Here, the memory circuit described in the above embodiment can be used for the memory circuit 810. Since the memory circuit of one embodiment of the present invention can retain data even when not powered, the memory circuit can be favorably used for an RF tag. Furthermore, the memory circuit of one embodiment of the present invention needs power (voltage) needed for data writing significantly lower than that needed in a conventional nonvolatile memory; thus, it is possible to prevent a difference between the maximum communication range in data reading and that in data writing. In addition, it is possible to suppress malfunction or incorrect writing which is caused by power shortage in data writing.

Since the memory circuit of one embodiment of the present invention can be used as a nonvolatile memory, it can also be used as the ROM 811. In this case, it is preferable that a manufacturer separately prepare a command for writing data to the ROM 811 so that a user cannot rewrite data freely. Since the manufacturer gives identification numbers before shipment and then starts shipment of products, instead of putting identification numbers to all the manufactured RF tags, it is possible to put identification numbers to only good products to be shipped. Thus, the identification numbers of the shipped products are in series and customer management corresponding to the shipped products is easily performed.

This embodiment can be combined with any of the other embodiments in this specification as appropriate.

Embodiment 7

In this embodiment, a CPU that includes the memory device described in the above embodiment will be described.

FIG. 52 is a block diagram illustrating a configuration example of a CPU at least partly including the transistor described in the above embodiment as a component.

<CPU>

The CPU illustrated in FIG. 52 includes, over a substrate 1190, an arithmetic logic unit (ALU) 1191, an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198, a rewritable ROM 1199, and a ROM interface 1189. A semiconductor substrate, an SOI substrate, a glass substrate, or the like is used as the substrate 1190. The ROM 1199 and the ROM interface 1189 may be provided over a separate chip. Needless to say, the CPU in FIG. 52 is just an example in which the configuration is simplified, and an actual CPU may have a variety of configurations depending on the application. For example, the CPU may have the following configuration: a structure including the CPU in FIG. 52 or an arithmetic circuit is considered as one core; a plurality of the cores are included; and the cores operate in parallel. The number of bits that the CPU can process in an internal arithmetic circuit or in a data bus can be 8, 16, 32, or 64, for example.

An instruction that is input to the CPU through the bus interface 1198 is input to the instruction decoder 1193 and decoded therein, and then, input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.

The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 conduct various controls in accordance with the decoded instruction. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. While the CPU is executing a program, the interrupt controller 1194 judges an interrupt request from an external input/output device or a peripheral circuit on the basis of its priority or a mask state, and processes the request. The register controller 1197 generates an address of the register 1196, and reads/writes data from/to the register 1196 in accordance with the state of the CPU.

The timing controller 1195 generates signals for controlling operation timings of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generator for generating an internal clock signal on the basis of a reference clock signal, and supplies the internal clock signal to the above circuits.

In the CPU illustrated in FIG. 52, a memory cell is provided in the register 1196. For the memory cell of the register 1196, the transistor described in Embodiment 1 can be used.

In the CPU illustrated in FIG. 52, the register controller 1197 selects operation of retaining data in the register 1196 in accordance with an instruction from the ALU 1191. That is, the register controller 1197 selects whether data is retained by a flip-flop or by a capacitor in the memory cell included in the register 1196. When data retention by the flip-flop is selected, a power supply voltage is supplied to the memory cell in the register 1196. When data retention by the capacitor is selected, the data is rewritten in the capacitor, and supply of power supply voltage to the memory cell in the register 1196 can be stopped.

<Memory Circuit>

FIG. 53 is an example of a circuit diagram of a memory element that can be used as the register 1196. A memory element 1200 includes a circuit 1201 in which stored data is volatile when power supply is stopped, a circuit 1202 in which stored data is nonvolatile even when power supply is stopped, switches 1203 and 1204, a logic element 1206, a capacitor 1207, and a circuit 1220 having a selecting function. The circuit 1202 includes a capacitor 1208 and transistors 1209 and 1210. Note that the memory element 1200 may further include another element such as a diode, a resistor, or an inductor, as needed.

Here, the memory device described in the above embodiment can be used as the circuit 1202. When supply of a power supply voltage to the memory element 1200 is stopped, a ground potential (0 V) or a potential at which the transistor 1209 in the circuit 1202 is turned off continues to be input to a gate of the transistor 1209. For example, a first gate of the transistor 1209 is grounded through a load such as a resistor.

Shown here is an example in which the switch 1203 is a transistor 1213 having one conductivity type (e.g., an n-channel transistor) and the switch 1204 is a transistor 1214 having a conductivity type opposite to the one conductivity type (e.g., a p-channel transistor). A first terminal of the switch 1203 corresponds to one of a source and a drain of the transistor 1213, a second terminal of the switch 1203 corresponds to the other of the source and the drain of the transistor 1213, and conduction or non-conduction between the first terminal and the second terminal of the switch 1203 (i.e., the on/off state of the transistor 1213) is selected by a control signal RD input to a gate of the transistor 1213. A first terminal of the switch 1204 corresponds to one of a source and a drain of the transistor 1214, a second terminal of the switch 1204 corresponds to the other of the source and the drain of the transistor 1214, and conduction or non-conduction between the first terminal and the second terminal of the switch 1204 (i.e., the on/off state of the transistor 1214) is selected by the control signal RD input to a gate of the transistor 1214.

One of a source and a drain of the transistor 1209 is electrically connected to one of a pair of electrodes of the capacitor 1208 and a gate of the transistor 1210. Here, the connection portion is referred to as a node N2. One of a source and a drain of the transistor 1210 is electrically connected to a line which can supply a low power supply potential (e.g., a GND line), and the other thereof is electrically connected to the first terminal of the switch 1203 (the one of the source and the drain of the transistor 1213). The second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is electrically connected to the first terminal of the switch 1204 (the one of the source and the drain of the transistor 1214). The second terminal of the switch 1204 (the other of the source and the drain of the transistor 1214) is electrically connected to a line which can supply a power supply potential VDD. The second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213), the first terminal of the switch 1204 (the one of the source and the drain of the transistor 1214), an input terminal of the logic element 1206, and one of a pair of electrodes of the capacitor 1207 are electrically connected to each other. Here, the connection portion is referred to as a node N1. The other of the pair of electrodes of the capacitor 1207 can be supplied with a constant potential. For example, the other of the pair of electrodes of the capacitor 1207 can be supplied with a low power supply potential (e.g., GND) or a high power supply potential (e.g., VDD). The other of the pair of electrodes of the capacitor 1207 is electrically connected to the line which can supply a low power supply potential (e.g., a GND line). The other of the pair of electrodes of the capacitor 1208 can be supplied with a constant potential. For example, the other of the pair of electrodes of the capacitor 1208 can be supplied with a low power supply potential (e.g., GND) or a high power supply potential (e.g., VDD). The other of the pair of electrodes of the capacitor 1208 is electrically connected to the line which can supply a low power supply potential (e.g., a GND line).

The capacitors 1207 and 1208 are not necessarily provided as long as the parasitic capacitance of the transistor, the wiring, or the like is actively utilized.

A control signal WE is input to the first gate (first gate electrode) of the transistor 1209. As for each of the switch 1203 and the switch 1204, a conduction state or a non-conduction state between the first terminal and the second terminal is selected by the control signal RD which is different from the control signal WE. When the first terminal and the second terminal of one of the switches are in the conduction state, the first terminal and the second terminal of the other of the switches are in the non-conduction state.

Note that the transistor 1209 in FIG. 53 has a structure with a second gate (second gate electrode: back gate). The control signal WE can be input to the first gate and a control signal WE2 can be input to the second gate. The control signal WE2 is a signal having a constant potential. As the constant potential, for example, a ground potential GND or a potential lower than a source potential of the transistor 1209 is selected. The control signal WE2 is a potential signal for controlling the threshold voltage of the transistor 1209, and an off-state current of the transistor 1209 can be further reduced. The control signal WE2 may be a signal having the same potential as the control signal WE. Note that as the transistor 1209, a transistor without a second gate may be used.

A signal corresponding to data retained in the circuit 1201 is input to the other of the source and the drain of the transistor 1209. FIG. 52 illustrates an example in which a signal output from the circuit 1201 is input to the other of the source and the drain of the transistor 1209. The logic value of a signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is inverted by the logic element 1206, and the inverted signal is input to the circuit 1201 through the circuit 1220.

In the example of FIG. 53, a signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is input to the circuit 1201 through the logic element 1206 and the circuit 1220; however, one embodiment of the present invention is not limited thereto. The signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) may be input to the circuit 1201 without its logic value being inverted. For example, in the case where the circuit 1201 includes a node in which a signal obtained by inversion of the logic value of a signal input from the input terminal is retained, the signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) can be input to the node.

In FIG. 53, the transistors included in the memory element 1200 except for the transistor 1209 can each be a transistor in which a channel region is formed in a layer formed using a semiconductor other than an oxide semiconductor or in the substrate 1190. For example, the transistor can be a transistor whose channel region is formed in a silicon layer or a silicon substrate. Alternatively, all the transistors in the memory element 1200 may be a transistor in which a channel region is formed in an oxide semiconductor. Further alternatively, in the memory element 1200, a transistor in which a channel region is formed in an oxide semiconductor can be included besides the transistor 1209, and a transistor in which a channel region is formed in a layer including a semiconductor other than an oxide semiconductor or the substrate 1190 can be used for the rest of the transistors.

As the circuit 1201 in FIG. 53, for example, a flip-flop circuit can be used. As the logic element 1206, for example, an inverter or a clocked inverter can be used.

In a period during which the memory element 1200 is not supplied with the power supply voltage, the semiconductor device of one embodiment of the present invention can retain data stored in the circuit 1201 by the capacitor 1208 which is provided in the circuit 1202.

The off-state current of a transistor in which a channel region is formed in an oxide semiconductor is extremely low. For example, the off-state current of a transistor in which a channel region is formed in an oxide semiconductor is significantly lower than that of a transistor in which a channel region is formed in silicon having crystallinity. Thus, when the transistor is used as the transistor 1209, a signal held in the capacitor 1208 is retained for a long time also in a period during which the power supply voltage is not supplied to the memory element 1200. The memory element 1200 can accordingly retain the stored content (data) also in a period during which the supply of the power supply voltage is stopped.

Since the above-described memory element performs pre-charge operation with the switches 1203 and 1204, it is possible to shorten the time required for the circuit 1201 to retain original data again after the supply of the power supply voltage is restarted.

In the circuit 1202, a signal retained by the capacitor 1208 is input to the gate of the transistor 1210. Therefore, after supply of the power supply voltage to the memory element 1200 is restarted, the state (the on state or the off state) of the transistor 1210 is determined in accordance with the signal retained by the capacitor 1208 and can be read from the circuit 1202. Consequently, an original signal can be accurately read even when a potential corresponding to the signal retained by the capacitor 1208 varies to some degree.

By applying the above-described memory element 1200 to a memory device such as a register or a cache memory included in a processor, data in the memory device can be prevented from being lost owing to the stop of the supply of the power supply voltage. Furthermore, shortly after the supply of the power supply voltage is restarted, the memory device can be returned to the same state as that before the power supply is stopped. Therefore, the power supply can be stopped even for a short time in the processor or one or a plurality of logic circuits included in the processor, resulting in lower power consumption.

Although the memory element 1200 is used in a CPU in this embodiment, the memory element 1200 can also be used in an LSI such as a digital signal processor (DSP), a custom LSI, or a programmable logic device (PLD), and a radio frequency (RF) tag.

This embodiment can be combined as appropriate with any of the other embodiments in this specification.

Embodiment 8

In this embodiment, configuration examples of a display device using a transistor of one embodiment of the present invention will be described.

<Circuit Configuration Example of Display Device>

FIG. 54A is a top view of the display device of one embodiment of the present invention. FIG. 54B is a circuit diagram illustrating a pixel circuit that can be used in the case where a liquid crystal element is used in a pixel in the display device of one embodiment of the present invention. FIG. 54C is a circuit diagram illustrating a pixel circuit that can be used in the case where an organic EL element is used in a pixel in the display device of one embodiment of the present invention.

The transistor in the pixel portion can be formed in accordance with Embodiment 1. The transistor can be easily formed as an n-channel transistor, and thus part of a driver circuit that can be formed using an n-channel transistor can be formed over the same substrate as the transistor of the pixel portion. With the use of the transistor described in the above embodiment for the pixel portion or the driver circuit in this manner, a highly reliable display device can be provided.

FIG. 54A illustrates an example of a top view of an active matrix display device. A pixel portion 701, a first scan line driver circuit 702, a second scan line driver circuit 703, and a signal line driver circuit 704 are formed over a substrate 700 of the display device. In the pixel portion 701, a plurality of signal lines extended from the signal line driver circuit 704 are arranged and a plurality of scan lines extended from the first scan line driver circuit 702 and the second scan line driver circuit 703 are arranged. Note that pixels which include display elements are provided in a matrix in respective regions where the scan lines and the signal lines intersect with each other. The substrate 700 of the display device is connected to a timing control circuit (also referred to as a controller or a controller IC) through a connection portion such as a flexible printed circuit (FPC).

In FIG. 54A, the first scan line driver circuit 702, the second scan line driver circuit 703, and the signal line driver circuit 704 are formed over the substrate 700 where the pixel portion 701 is formed. Accordingly, the number of components which are provided outside, such as a driver circuit, can be reduced, so that a reduction in cost can be achieved. Furthermore, if the driver circuit is provided outside the substrate 700, wirings would need to be extended and the number of wiring connections would increase. When the driver circuit is provided over the substrate 700, the number of wiring connections can be reduced. Consequently, an improvement in reliability or yield can be achieved. One or more of the first scan line driver circuit 702, the second scan line driver circuit 703, and the signal line driver circuit 704 may be mounted on the substrate 700 or provided outside the substrate 700.

<Liquid Crystal Display Device>

FIG. 54B illustrates an example of a circuit configuration of the pixel. Here, a pixel circuit which is applicable to a pixel of a VA liquid crystal display device is illustrated as an example.

This pixel circuit can be applied to a structure in which one pixel includes a plurality of pixel electrode layers. The pixel electrode layers are connected to different transistors, and the transistors can be driven with different gate signals. Accordingly, signals applied to individual pixel electrode layers in a multi-domain pixel can be controlled independently.

A scan line 712 of a transistor 716 and a scan line 713 of a transistor 717 are separated so that different gate signals can be supplied thereto. In contrast, a signal line 714 is shared by the transistors 716 and 717. The transistor described in Embodiment 1 can be used as appropriate as each of the transistors 716 and 717. Thus, a highly reliable liquid crystal display device can be provided.

A first pixel electrode is electrically connected to the transistor 716 and a second pixel electrode is electrically connected to the transistor 717. The first pixel electrode and the second pixel electrode are separated. There is no particular limitation on the shapes of the first pixel electrode and the second pixel electrode. For example, the first pixel electrode may have a V-like shape.

A gate electrode of the transistor 716 is connected to the scan line 712, and a gate electrode of the transistor 717 is connected to the scan line 713. When different gate signals are supplied to the scan line 712 and the scan line 713, operation timings of the transistors 716 and 717 can be varied. As a result, alignment of liquid crystals can be controlled.

Further, a storage capacitor may be formed using a capacitor wiring 710, a gate insulating layer of a transistor functioning as a dielectric, and a capacitor electrode electrically connected to the first pixel electrode or the second pixel electrode.

The multi-domain pixel includes a first liquid crystal element 718 and a second liquid crystal element 719. The first liquid crystal element 718 includes the first pixel electrode, a counter electrode layer, and a liquid crystal layer therebetween. The second liquid crystal element 719 includes the second pixel electrode, a counter electrode layer, and a liquid crystal layer therebetween.

Note that a pixel circuit of the present invention is not limited to that illustrated in FIG. 54B. For example, a switch, a resistor, a capacitor, a transistor, a sensor, a logic circuit, or the like may be added to the pixel circuit illustrated in FIG. 54B.

FIGS. 55A and 55B are examples of a top view and a cross-sectional view of a liquid crystal display device. Note that FIG. 55A illustrates a typical structure including a display device 20, a display region 21, a peripheral circuit 22, and flexible printed circuits (FPCs) 42. The display panel illustrated in FIGS. 55A and 55B uses a reflective liquid crystal element.

FIG. 55B is a cross-sectional view taken along dashed lines A-A′, B-B′, C-C′, and D-D′ in FIG. 55A. The cross section taken along dashed line A-A′ illustrates the peripheral circuit portion, the cross section taken along dashed line B-B′ illustrates the display region, and the cross sections taken along dashed line C-C′ and dashed line D-D′ illustrate portions connected to the FPCs.

The display device 20 using the liquid crystal element includes the following in addition to transistors 50 and 52 (the transistor 10 described in Embodiment 1): the conductive layer 165, a conductive layer 197, an insulating layer 420, a liquid crystal layer 490, a liquid crystal element 80, capacitors 60 and 62, an insulating layer 430, a spacer 440, a coloring layer 460, a bonding layer 470, a conductive layer 480, a light-shielding layer 418, a substrate 400, bonding layers 473, 474, 475, and 476, polarizing plates 103 and 403, protective substrates 105 and 402, and an anisotropic conductive layer 510.

<Organic EL Display Device>

FIG. 54C illustrates another example of a circuit configuration of the pixel. Here, a pixel structure of a display device using an organic EL element is shown.

In an organic EL element, by application of voltage to a light-emitting element, electrons are injected from one of a pair of electrodes and holes are injected from the other of the pair of electrodes, into a layer containing a light-emitting organic compound; thus, current flows. The electrons and holes are recombined, and thus, the light-emitting organic compound is excited. The light-emitting organic compound returns to a ground state from the excited state, thereby emitting light. Owing to such a mechanism, this light-emitting element is referred to as a current-excitation light-emitting element.

FIG. 54C illustrates an applicable example of a pixel circuit. Here, one pixel includes two n-channel transistors. Furthermore, digital time grayscale driving can be employed for the pixel circuit.

The configuration of the applicable pixel circuit and operation of a pixel employing digital time grayscale driving are described.

A pixel 720 includes a switching transistor 721, a driver transistor 722, a light-emitting element 724, and a capacitor 723. A gate electrode of the switching transistor 721 is connected to a scan line 726, a first electrode (one of a source electrode and a drain electrode) of the switching transistor 721 is connected to a signal line 725, and a second electrode (the other of the source electrode and the drain electrode) of the switching transistor 721 is connected to a gate electrode of the driver transistor 722. The gate electrode of the driver transistor 722 is connected to a power supply line 727 through the capacitor 723, a first electrode of the driver transistor 722 is connected to the power supply line 727, and a second electrode of the driver transistor 722 is connected to a first electrode (a pixel electrode) of the light-emitting element 724. A second electrode of the light-emitting element 724 corresponds to a common electrode 728. The common electrode 728 is electrically connected to a common potential line formed over the same substrate as the common electrode 728.

As the switching transistor 721 and the driver transistor 722, the transistor described in Embodiment 1 can be used as appropriate. In this manner, a highly reliable organic EL display device can be provided.

The potential of the second electrode (the common electrode 728) of the light-emitting element 724 is set to be a low power supply potential. Note that the low power supply potential is lower than a high power supply potential supplied to the power supply line 727. For example, the low power supply potential can be GND, 0 V, or the like. The high power supply potential and the low power supply potential are set to be higher than or equal to the forward threshold voltage of the light-emitting element 724, and the difference between the potentials is applied to the light-emitting element 724, whereby current is supplied to the light-emitting element 724, leading to light emission. The forward voltage of the light-emitting element 724 refers to a voltage which is required for obtaining a desired luminance and includes at least a forward threshold voltage.

Note that gate capacitance of the driver transistor 722 may be used as a substitute for the capacitor 723, so that the capacitor 723 can be omitted.

Next, a signal input to the driver transistor 722 is described. In the case of a voltage-input voltage driving method, a video signal for sufficiently turning on or off the driver transistor 722 is input to the driver transistor 722. In order for the driver transistor 722 to operate in a linear region, voltage higher than the voltage of the power supply line 727 is applied to the gate electrode of the driver transistor 722. Note that voltage higher than or equal to voltage which is the sum of the voltage of the power supply line 727 and the threshold voltage Vth of the driver transistor 722 is applied to the signal line 725.

In the case of performing analog grayscale driving, a voltage higher than or equal to a voltage which is the sum of the forward voltage of the light-emitting element 724 and the threshold voltage Vth of the driver transistor 722 is applied to the gate electrode layer of the driver transistor 722. A video signal by which the driver transistor 722 is operated in a saturation region is input, so that current is supplied to the light-emitting element 724. In order for the driver transistor 722 to operate in a saturation region, the potential of the power supply line 727 is set higher than the gate potential of the driver transistor 722. When an analog video signal is used, it is possible to supply current to the light-emitting element 724 in accordance with the video signal and perform analog grayscale driving.

Note that the configuration of the pixel circuit is not limited to that shown in FIG. 54C. For example, a switch, a resistor, a capacitor, a sensor, a transistor, a logic circuit, or the like may be added to the pixel circuit illustrated in FIG. 54C.

In the case where the transistor described in the above embodiment is used for the circuit illustrated in FIGS. 54A to 54C, the source electrode (the first electrode) is electrically connected to the low potential side and the drain electrode (the second electrode) is electrically connected to the high potential side. Furthermore, the potential of the first gate electrode may be controlled by a control circuit or the like, and the potential described above as an example, for example, a potential lower than the potential applied to the source electrode, may be input to the second gate electrode through a wiring that is not illustrated.

FIGS. 56A and 56B are examples of a top view and a cross-sectional view of a display device using a light-emitting element. Note that FIG. 56A illustrates a typical structure including a display device 24, the display region 21, the peripheral circuit 22, and the flexible printed circuit (FPCs) 42.

FIG. 56B is a cross-sectional view taken along dashed lines A-A′, B-B′, and C-C′ in FIG. 56A. The cross section taken along dashed line A-A′ illustrates the peripheral circuit portion, the cross section taken along dashed line B-B′ illustrates the display region, and the cross section taken along dashed line C-C′ illustrates a portion connected to the FPC.

The display device 24 using the light-emitting element includes the following in addition to the transistors 50 and 52 (the transistor 10 described in Embodiment 1): the insulating layer 420, the conductive layer 197, a conductive layer 410, an optical adjustment layer 530, an EL layer 450, a conductive layer 415, a light-emitting element 70, the capacitors 60 and 62, the insulating layer 430, the spacer 440, the coloring layer 460, the bonding layer 470, a partition wall 445, the light-shielding layer 418, the substrate 400, and the anisotropic conductive layer 510.

In this specification, a display element, a display device which is a device including a display element, a light-emitting element, and a light-emitting device which is a device including a light-emitting element can employ a variety of modes or can include a variety of elements, for example. A display element, a display device, a light-emitting element, or a light-emitting device include at least one of the following, for example: an EL (electroluminescent) element (e.g., an EL element including organic and inorganic materials, an organic EL element, or an inorganic EL element), an LED (e.g., a white LED, a red LED, a green LED, or a blue LED), a quantum dot, a transistor (a transistor which emits light depending on current), an electron emitter, a liquid crystal element, electronic ink, an electrophoretic element, a grating light valve (GLV), a plasma display panel (PDP), micro electro mechanical systems (MEMS), a digital micromirror device (DMD), a digital micro shutter (DMS), an interferometric modulator (IMOD) element, an electrowetting element, a piezoelectric ceramic display, and a display element using a carbon nanotube. Other than the above, display media whose contrast, luminance, reflectivity, transmittance, or the like is changed by electric or electromagnetic action may be included. Note that examples of display devices having EL elements include an EL display. Examples of display devices including electron emitters include a field emission display (FED) and an SED-type flat panel display (SED: surface-conduction electron-emitter display). Examples of display devices including liquid crystal elements include a liquid crystal display (e.g., a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct-view liquid crystal display, or a projection liquid crystal display). Examples of display devices including electronic ink or electrophoretic elements include electronic paper.

Note that this embodiment can be combined as appropriate with any of the other embodiments and an example in this specification.

Embodiment 9

In this embodiment, a display module using a semiconductor device of one embodiment of the present invention is described with reference to FIG. 57.

<Display Module>

In a display module 6000 in FIG. 57, a touch panel 6004 connected to an FPC 6003, a display panel 6006 connected to an FPC 6005, a backlight unit 6007, a frame 6009, a printed circuit board 6010, and a battery 6011 are provided between an upper cover 6001 and a lower cover 6002. Note that the backlight unit 6007, the battery 6011, the touch panel 6004, and the like are not provided in some cases.

The semiconductor device of one embodiment of the present invention can be used for the display panel 6006, an integrated circuit mounted on a printed circuit board 6010, or the like.

The shapes and sizes of the upper cover 6001 and the lower cover 6002 can be changed as appropriate in accordance with the sizes of the touch panel 6004 and the display panel 6006.

The touch panel 6004 can be a resistive touch panel or a capacitive touch panel and may be formed to overlap with the display panel 6006. A counter substrate (sealing substrate) of the display panel 6006 can have a touch panel function. A photosensor may be provided in each pixel of the display panel 6006 so that an optical touch panel function is added. An electrode for a touch sensor may be provided in each pixel of the display panel 6006 so that a capacitive touch panel function is added.

The backlight unit 6007 includes a light source 6008. The light source 6008 may be provided at an end portion of the backlight unit 6007 and a light diffusing plate may be used.

The frame 6009 protects the display panel 6006 and also functions as an electromagnetic shield for blocking electromagnetic waves generated from the printed circuit board 6010. The frame 6009 may function as a radiator plate.

The printed circuit board 6010 has a power supply circuit and a signal processing circuit for outputting a video signal and a clock signal. As a power source for supplying power to the power supply circuit, an external commercial power source or the battery 6011 provided separately may be used. Note that the battery 6011 is not necessary in the case where a commercial power source is used.

The display module 6000 can be additionally provided with a member such as a polarizing plate, a retardation plate, or a prism sheet.

Note that this embodiment can be combined with any of the other embodiments in this specification as appropriate.

Embodiment 10

In this embodiment, application examples of the semiconductor device of one embodiment of the present invention will be described.

<Package Using a Lead Frame Interposer>

FIG. 58A is a perspective view illustrating a cross-sectional structure of a package using a lead frame interposer. In the package illustrated in FIG. 58A, a chip 1751 corresponding to the semiconductor device of one embodiment of the present invention is connected to a terminal 1752 over an interposer 1750 by wire bonding. The terminal 1752 is placed on a surface of the interposer 1750 on which the chip 1751 is mounted. The chip 1751 may be sealed by a mold resin 1753, in which case the chip 1751 is sealed such that part of each of the terminals 1752 is exposed.

FIG. 58B illustrates the structure of a module of an electronic device (mobile phone) in which a package is mounted on a circuit board. In the module of the mobile phone in FIG. 58B, a package 1802 and a battery 1804 are mounted on a printed wiring board 1801. The printed wiring board 1801 is mounted on a panel 1800 including a display element by an FPC 1803.

Note that this embodiment can be combined with any of the other embodiments in this specification as appropriate.

Embodiment 11

In this embodiment, electronic devices and lighting devices of one embodiment of the present invention will be described with reference to drawings.

<Electronic Device>

Electronic devices and lighting devices can be fabricated using the semiconductor device of one embodiment of the present invention. In addition, highly reliable electronic devices and lighting devices can be fabricated using the semiconductor device of one embodiment of the present invention. Furthermore, electronic devices and lighting devices including touch sensors with improved detection sensitivity can be fabricated using the semiconductor device of one embodiment of the present invention.

Examples of electronic devices include a television set (also referred to as a television or a television receiver), a monitor of a computer or the like, a digital camera, a digital video camera, a digital photo frame, a mobile phone (also referred to as a mobile phone device), a portable game machine, a portable information terminal, an audio reproducing device, and a large game machine such as a pachinko machine.

In the case of having flexibility, the electronic device or lighting device of one embodiment of the present invention can be incorporated along a curved inside/outside wall surface of a house or a building or a curved interior/exterior surface of a car.

Furthermore, the electronic device of one embodiment of the present invention may include a secondary battery. It is preferable that the secondary battery be capable of being charged by non-contact power transmission.

Examples of the secondary battery include a lithium ion secondary battery such as a lithium polymer battery using a gel electrolyte (lithium ion polymer battery), a lithium-ion battery, a nickel-hydride battery, a nickel-cadmium battery, an organic radical battery, a lead storage battery, an air secondary battery, a nickel-zinc battery, and a silver-zinc battery.

The electronic device of one embodiment of the present invention may include an antenna. When a signal is received by the antenna, an image, data, or the like can be displayed on a display portion. When the electronic device includes a secondary battery, the antenna may be used for non-contact power transmission.

FIG. 59A illustrates a portable game machine including a housing 7101, a housing 7102, a display portion 7103, a display portion 7104, a microphone 7105, speakers 7106, an operation key 7107, a stylus 7108, and the like. The semiconductor device of one embodiment of the present invention can be used for an integrated circuit, a CPU, or the like incorporated in the housing 7101. When a normally-off CPU is used as the CPU, power consumption can be reduced, allowing a user to enjoy playing a game for longer than before. When the light-emitting device of one embodiment of the present invention is used as the display portion 7103 or 7104, it is possible to provide a user-friendly portable game machine with quality that hardly deteriorates. Although the portable game machine illustrated in FIG. 59A includes two display portions, the display portion 7103 and the display portion 7104, the number of display portions included in the portable game machine is not limited to two.

FIG. 59B illustrates a smart watch, which includes a housing 7302, a display panel 7304, operation buttons 7311 and 7312, a connection terminal 7313, a band 7321, a clasp 7322, and the like. The semiconductor device of one embodiment of the present invention can be used for a memory, a CPU, or the like incorporated in the housing 7302. Note that when the display is a reflective liquid crystal panel and the CPU is a normally-off CPU in FIG. 59B, power consumption can be reduced, leading to a reduction in the number of times of daily charging.

The display panel 7304 mounted in the housing 7302 serving as a bezel includes a non-rectangular display region. The display panel 7304 may have a rectangular display region. The display panel 7304 can display an icon 7305 indicating time, another icon 7306, and the like.

FIG. 59C illustrates a portable information terminal, which includes a display portion 7502 incorporated in a housing 7501, operation buttons 7503, an external connection port 7504, a speaker 7505, a microphone 7506, a display portion 7502, and the like. The semiconductor device of one embodiment of the present invention can be used for a mobile memory, a CPU, or the like incorporated in the housing 7501. Note that when a normally-off CPU is used, the number of times of charging can be reduced. Note that the display portion 7502 is small- or medium-sized but can perform full high vision, 4K, or 8K display because it has greatly high definition; therefore, a significantly clear image can be obtained.

FIG. 59D illustrates a video camera including a first housing 7701, a second housing 7702, a display portion 7703, operation keys 7704, a lens 7705, a joint 7706, and the like. The operation keys 7704 and the lens 7705 are provided for the first housing 7701, and the display portion 7703 is provided for the second housing 7702. The first housing 7701 and the second housing 7702 are connected to each other with the joint 7706, and the angle between the first housing 7701 and the second housing 7702 can be changed with the joint 7706. Images displayed on the display portion 7703 may be switched in accordance with the angle at the joint 7706 between the first housing 7701 and the second housing 7702. The imaging device of one embodiment of the present invention can be used in a portion corresponding to a focus of the lens 7705. The semiconductor device of one embodiment of the present invention can be used for an integrated circuit, a CPU, or the like incorporated in the first housing 7701.

FIG. 59E illustrates a digital signage, which includes a display portion 7902 provided on a utility pole 7901. The semiconductor device of one embodiment of the present invention can be used for a display panel of the display portion 7902 and an incorporated control circuit.

FIG. 60A illustrates a notebook personal computer, which includes a housing 8121, a display portion 8122, a keyboard 8123, a pointing device 8124, and the like. The semiconductor device of one embodiment of the present invention can be used for a CPU, a memory, or the like incorporated in the housing 8121. Note that the display portion 8122 is small- or medium-sized but can perform 8 k display because it has greatly high resolution; therefore, a significantly clear image can be obtained.

FIG. 60B is an external view of an automobile 9700. FIG. 60C illustrates a driver's seat of the automobile 9700. The automobile 9700 includes a car body 9701, wheels 9702, a dashboard 9703, lights 9704, and the like. The semiconductor device of one embodiment of the present invention can be used in a display portion and a control integrated circuit of the automobile 9700. For example, the semiconductor device of one embodiment of the present invention can be used in display portions 9710 to 9715 illustrated in FIG. 60C.

The display portion 9710 and the display portion 9711 are display devices or input/output devices provided in an automobile windshield. The display device or input/output device of one embodiment of the present invention can be a see-through display device or input/output device, through which the opposite side can be seen, by using a light-transmitting conductive material for its electrodes. Such a see-through display device or input/output device does not hinder driver's vision during the driving of the automobile 9700. Therefore, the display device or input/output device of one embodiment of the present invention can be provided in the windshield of the automobile 9700. Note that in the case where a transistor or the like for driving the display device or input/output device is provided in the display device or input/output device, a transistor having light-transmitting properties, such as an organic transistor using an organic semiconductor material or a transistor using an oxide semiconductor, is preferably used.

The display portion 9712 is a display device or input/output device provided on a pillar portion. For example, the display portion 9712 can compensate for the view hindered by the pillar portion by showing an image taken by an imaging unit provided on the car body. The display portion 9713 is a display device or input/output device provided on the dashboard. For example, the display portion 9713 can compensate for the view hindered by the dashboard portion by showing an image taken by an imaging unit provided on the car body. That is, showing an image taken by an imaging unit provided on the outside of the car body leads to elimination of blind areas and enhancement of safety. In addition, showing an image so as to compensate for the area which a driver cannot see makes it possible for the driver to confirm safety easily and comfortably.

FIG. 60D illustrates the inside of a car in which bench seats are used for a driver seat and a front passenger seat. A display portion 9721 is a display device or input/output device provided in a door portion. For example, the display portion 9721 can compensate for the view hindered by the door portion by showing an image taken by an imaging unit provided on the car body. A display portion 9722 is a display device or input/output device provided in the middle of a seating face of the bench seat. A display portion 9723 is a display device or input/output device provided in the middle of a seating face of the bench seat. Note that the display device or input/output device can be used as a seat heater by providing the display device or input/output device on the seating face or backrest and by using heat generated by the display device or input/output device as a heat source.

The display portion 9714, the display portion 9715, and the display portion 9722 can display a variety of kinds of information such as navigation data, a speedometer, a tachometer, a mileage, a fuel meter, a gearshift indicator, and air-condition setting. The content, layout, or the like of the display on the display portions can be changed freely by a user as appropriate. The information listed above can also be displayed on the display portions 9710 to 9713, 9721, and 9723. The display portions 9710 to 9715 and 9721 to 9723 can also be used as lighting devices. The display portions 9710 to 9715 and 9721 to 9723 can also be used as heating devices.

FIG. 61A illustrates an external view of a camera 8000. The camera 8000 includes a housing 8001, a display portion 8002, an operation button 8003, a shutter button 8004, a connection portion 8005, and the like. A lens 8006 can be put on the camera 8000.

The connection portion 8005 includes an electrode to connect a finder 8100, which is described below, a stroboscope, or the like.

Although the lens 8006 of the camera 8000 here is detachable from the housing 8001 for replacement, the lens 8006 may be included in the housing 8001.

Images can be taken at the press of the shutter button 8004. In addition, images can be taken at the touch of the display portion 8002 which serves as a touch panel.

The display device or input/output device of one embodiment of the present invention can be used in the display portion 8002.

FIG. 61B shows the camera 8000 with the finder 8100 connected.

The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

The housing 8101 includes a connection portion for engagement with the connection portion 8005 of the camera 8000 so that the finder 8100 can be connected to the camera 8000. The connection portion includes an electrode, and an image or the like received from the camera 8000 through the electrode can be displayed on the display portion 8102.

The button 8103 functions as a power supply button. With the button 8103, the display portion 8102 can be turned on and off.

The semiconductor device of one embodiment of the present invention can be used for an integrated circuit and an image sensor included in the housing 8101.

Although the camera 8000 and the finder 8100 are separate and detachable electronic devices in FIGS. 61A and 61B, the housing 8001 of the camera 8000 may include a finder having the display device or input/output device of one embodiment of the present invention.

FIG. 61C illustrates an external view of a head-mounted display 8200.

The head-mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, a cable 8205, and the like. The mounting portion 8201 includes a battery 8206.

Power is supplied from the battery 8206 to the main body 8203 through the cable 8205. The main body 8203 includes a wireless receiver or the like to receive video data, such as image data, and display it on the display portion 8204. The movement of the eyeball and the eyelid of a user is captured by a camera in the main body 8203 and then coordinates of the points the user looks at are calculated using the captured data to utilize the eye of the user as an input means.

The mounting portion 8201 may include a plurality of electrodes so as to be in contact with the user. The main body 8203 may be configured to sense current flowing through the electrodes with the movement of the user's eyeball to recognize the direction of his or her eyes. The main body 8203 may be configured to sense current flowing through the electrodes to monitor the user's pulse. The mounting portion 8201 may include sensors, such as a temperature sensor, a pressure sensor, or an acceleration sensor so that the user's biological information can be displayed on the display portion 8204. The main body 8203 may be configured to sense the movement of the user's head or the like to move an image displayed on the display portion 8204 in synchronization with the movement of the user's head or the like.

The semiconductor device of one embodiment of the present invention can be used for an integrated circuit included in the main body 8203.

At least part of this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate.

Embodiment 12

In this embodiment, application examples of an RF tag using the semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 62A to 62F.

<Application Examples of RF Tag>

The RF tag is widely used and can be provided for, for example, products such as bills, coins, securities, bearer bonds, documents (e.g., driver's licenses or resident's cards, see FIG. 62A), vehicles (e.g., bicycles, see FIG. 62B), packaging containers (e.g., wrapping paper or bottles, see FIG. 62C), recording media (e.g., DVD or video tapes, see FIG. 62D), personal belongings such as bags and glasses, foods, plants, animals, human bodies, cloths, household goods, electronic appliances, medical supplies such as medicine and chemicals, electronic devices (e.g., liquid crystal display devices, EL display devices, television sets, or cellular phones), or tags on products (see FIGS. 62E and 62F).

An RF tag 4000 of one embodiment of the present invention is fixed to a product by being attached to a surface thereof or embedded therein. For example, the RF tag 4000 is fixed to each product by being embedded in paper of a book, or embedded in an organic resin of a package. Since the RF tag 4000 of one embodiment of the present invention can be reduced in size, thickness, and weight, it can be fixed to a product without spoiling the design of the product. Furthermore, bills, coins, securities, bearer bonds, documents, or the like can have an identification function by being provided with the RF tag 4000 of one embodiment of the present invention, and the identification function can be utilized to prevent counterfeiting. Moreover, the efficiency of a system such as an inspection system can be improved by providing the RF tag of one embodiment of the present invention for packaging containers, recording media, personal belongings, foods, clothing, household goods, electronic appliances, or the like. Vehicles can also have a higher level of security against theft or the like by being provided with the RF tag of one embodiment of the present invention.

As described above, by using the RF tag including the semiconductor device of one embodiment of the present invention for each application described in this embodiment, power for operation such as writing or reading of data can be reduced, which results in an increase in the maximum communication distance. Moreover, data can be held for an extremely long period even in the state where power is not supplied; thus, the RF tag can be preferably used for application in which data is not frequently written or read.

This embodiment can be implemented in combination with any of the other embodiments in this specification as appropriate.

This application is based on Japanese Patent Application serial no. 2016-009178 filed with Japan Patent Office on Jan. 20, 2016, the entire contents of which are hereby incorporated by reference.

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Patent Valuation

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31.0/100 Score

Market Attractiveness

It shows from an IP point of view how many competitors are active and innovations are made in the different technical fields of the company. On a company level, the market attractiveness is often also an indicator of how diversified a company is. Here we look into the commercial relevance of the market.

41.0/100 Score

Market Coverage

It shows the sizes of the market that is covered with the IP and in how many countries the IP guarantees protection. It reflects a market size that is potentially addressable with the invented technology/formulation with a legal protection which also includes a freedom to operate. Here we look into the size of the impacted market.

71.94/100 Score

Technology Quality

It shows the degree of innovation that can be derived from a company’s IP. Here we look into ease of detection, ability to design around and significance of the patented feature to the product/service.

41.0/100 Score

Assignee Score

It takes the R&D behavior of the company itself into account that results in IP. During the invention phase, larger companies are considered to assign a higher R&D budget on a certain technology field, these companies have a better influence on their market, on what is marketable and what might lead to a standard.

23.02/100 Score

Legal Score

It shows the legal strength of IP in terms of its degree of protecting effect. Here we look into claim scope, claim breadth, claim quality, stability and priority.

Citation

Patents Cited in This Cited by
Title Current Assignee Application Date Publication Date
Chemical compound of ingazn6o9 with hexagonal system layer structure KAGAKU GIJUTSUCHO MUKIZAISHITSU KENKYUSHOCHO 27 February 1987 08 September 1988
Thin film transistor FUJITSU KK 23 March 1984 08 October 1985
Compound having laminar structure of hexagonal crystal system expressed by ingazn4o7 and its production KAGAKU GIJUTSUCHO MUKIZAISHITSU KENKYUSHOCHO 24 February 1987 31 August 1988
Compound having laminar structure of hexagonal crystal system expressed by ingazn3o6 and its production KAGAKU GIJUTSUCHO MUKIZAISHITSU KENKYUSHOCHO 24 February 1987 31 August 1988
Compound having laminar structure of hexagonal crystal system expressed by ingazn5o8 and its production KAGAKU GIJUTSUCHO MUKIZAISHITSU KENKYUSHOCHO 24 February 1987 31 August 1988
Title Current Assignee Application Date Publication Date
Semiconductor device and method for manufacturing semiconductor device SEMICONDUCTOR ENERGY LABORATORY CO., LTD. 23 February 2018 09 April 2019
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